NTMD6P02R2G

NTMD6P02, NVMD6P02 MOSFET – Power, Dual, P-Channel, SOIC-8 6 A, 20 V Features • • • • • • • • Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Miniature Dual SOIC−8 Surface Mount Package Diode Exhibits High Speed, Soft Recovery Avalanche Energy Specified These Devices are Pb−Free and are RoHS Compliant NVMD Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable www.onsemi.com 6 AMPERES, 20 VOLTS P−Channel D G Applications • Power Management in Portable and Battery−Powered Products, S i.e.: Cellular and Cordless Telephones, and PCMCIA Cards MAXIMUM RATINGS Rating Symbol Value Unit Drain−to−Source Voltage VDSS −20 V Gate−to−Source Voltage − Continuous VGS "12 V Thermal Resistance − Junction−to−Ambient (Note 1) Total Power Dissipation @ TA = 25°C Continuous Drain Current @ TA = 25°C Continuous Drain Current @ TA = 70°C Maximum Operating Power Dissipation Maximum Operating Drain Current Pulsed Drain Current (Note 4) RqJA PD ID ID PD ID IDM 62.5 2.0 −7.8 −5.7 0.5 −3.89 −40 °C/W W A A W A A Thermal Resistance − Junction−to−Ambient (Note 2) Total Power Dissipation @ TA = 25°C Continuous Drain Current @ TA = 25°C Continuous Drain Current @ TA = 70°C Maximum Operating Power Dissipation Maximum Operating Drain Current Pulsed Drain Current (Note 4) RqJA PD ID ID PD ID IDM 98 1.28 −6.2 −4.6 0.3 −3.01 −35 °C/W W A A W A A Thermal Resistance − Junction−to−Ambient (Note 3) Total Power Dissipation @ TA = 25°C Continuous Drain Current @ TA = 25°C Continuous Drain Current @ TA = 70°C Maximum Operating Power Dissipation Maximum Operating Drain Current Pulsed Drain Current (Note 4) RqJA PD ID ID PD ID IDM 166 0.75 −4.8 −3.5 0.2 −2.48 −30 °C/W W A A W A A Operating and Storage Temperature Range TJ, Tstg −55 to +150 °C EAS 500 mJ TL 260 °C Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = −20 Vdc, VGS = −5.0 Vdc, Peak IL = −5.0 Apk, L = 40 mH, RG = 25 W) Maximum Lead Temperature for Soldering Purposes for 10 seconds MARKING DIAGRAM & PIN ASSIGNMENT D1 D1 D2 D2 8 1 8 E6P02 AYWW G G SOIC−8 CASE 751 STYLE 11 1 S1 G1 S2 G2 E6P02 A Y WW G = Specific Device Code = Assembly Location = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Package Shipping† NTMD6P02R2G SOIC−8 (Pb−Free) 2500 / Tape & Reel NVMD6P02R2G SOIC−8 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Mounted onto a 2″ square FR−4 Board (1 in sq, 2 oz. Cu 0.06″ thick single sided), t = 10 seconds. © Semiconductor Components Industries, LLC, 2015 May, 2019 − Rev. 5 1 Publication Order Number: NTMD6P02R2/D NTMD6P02, NVMD6P02 2. Mounted onto a 2″ square FR−4 Board (1 in sq, 2 oz. Cu 0.06″ thick single sided), t = steady state. 3. Minimum FR−4 or G−10 PCB, t = steady state. 4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%. www.onsemi.com 2 NTMD6P02, NVMD6P02 ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)* Symbol Characteristic Min Typ Max Unit −20 − − −11.6 − − − − − − −1.0 −5.0 − − −100 − − 100 −0.6 − −0.88 2.6 −1.20 − − − − 0.027 0.038 0.038 0.033 0.050 − gFS − 15 − Mhos Ciss − 1380 1700 pF Coss − 515 775 Crss − 250 450 td(on) − 15 25 tr − 20 50 td(off) − 85 125 OFF CHARACTERISTICS V(BR)DSS Drain−to−Source Breakdown Voltage (VGS = 0 Vdc, ID = −250 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = −20 Vdc, VGS = 0 Vdc, TJ = 25°C) (VDS = −20 Vdc, VGS = 0 Vdc, TJ = 70°C) IDSS Gate−Body Leakage Current (VGS = −12 Vdc, VDS = 0 Vdc) IGSS Gate−Body Leakage Current (VGS = +12 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C mAdc nAdc nAdc ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = −250 mAdc) Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−State Resistance (VGS = −4.5 Vdc, ID = −6.2 Adc) (VGS = −2.5 Vdc, ID = −5.0 Adc) (VGS = −2.5 Vdc, ID = −3.1 Adc) RDS(on) Forward Transconductance (VDS = −10 Vdc, ID = −6.2 Adc) Vdc mV/°C W DYNAMIC CHARACTERISTICS Input Capacitance (VDS = −16 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 5 and 6) Turn−On Delay Time (VDD = −10 Vdc, ID = −1.0 Adc, VGS = −10 Vdc, RG = 6.0 W) Rise Time Turn−Off Delay Time Fall Time Turn−On Delay Time (VDD = −16 Vdc, ID = −6.2 Adc, VGS = −4.5 Vdc, RG = 6.0 W) Rise Time Turn−Off Delay Time Fall Time Total Gate Charge (VDS = −16 Vdc, VGS = −4.5 Vdc, ID = −6.2 Adc) Gate−Source Charge Gate−Drain Charge tf − 50 110 td(on) − 17 − tr − 65 − td(off) − 50 − tf − 80 − Qtot − 20 35 Qgs − 4.0 − Qgd − 8.0 − ns ns nC BODY−DRAIN DIODE RATINGS (Note 5) Diode Forward On−Voltage (IS = −1.7 Adc, VGS = 0 Vdc) (IS = −1.7 Adc, VGS = 0 Vdc, TJ = 125°C) VSD − − −0.80 −0.65 −1.2 − Vdc Diode Forward On−Voltage (IS = −6.2 Adc, VGS = 0 Vdc) (IS = −6.2 Adc, VGS = 0 Vdc, TJ = 125°C) VSD − − −0.95 −0.80 − − Vdc trr − 50 80 ns ta − 20 − tr − 30 − QRR − 0.04 − Reverse Recovery Time (IS = −1.7 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) Reverse Recovery Stored Charge 5. Indicates Pulse Test: Pulse Width = 300 ms max, Duty Cycle = 2%. 6. Switching characteristics are independent of operating junction temperature. *Handling precautions to protect against electrostatic discharge are mandatory. www.onsemi.com 3 mC NTMD6P02, NVMD6P02 −4.5 V −3.8 V −10 V 10 10 −2.1 V −ID, DRAIN CURRENT (AMPS) −ID, DRAIN CURRENT (AMPS) 12 TJ = 25°C 8.0 −3.1 V −2.5 V 6.0 −1.8 V 4.0 2.0 0 −1.5 V VGS = −1.3 V 0 VDS ≥ −10 V 8.0 6.0 100°C 2.0 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 25°C 4.0 0 1.0 1.5 2.0 2.5 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 2. Transfer Characteristics 0.05 ID = −6.2 A TJ = 25°C 0.03 0.02 0.01 0 0 2.0 4.0 6.0 8.0 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 10 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) Figure 1. On−Region Characteristics 0.04 0.05 TJ = 25°C VGS = −2.5 V 0.04 −2.7 V 0.03 −4.5 V 0.02 0.01 0 1.6 1000 ID = −6.2 A VGS = −4.5 V 1.2 1 0.8 0.6 −50 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) 2.0 8.0 10 4.0 6.0 −ID, DRAIN CURRENT (AMPS) 12 14 Figure 4. On-Resistance versus Drain Current and Gate Voltage −I DSS , LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) Figure 3. On−Resistance versus Gate−To−Source Voltage 1.4 TJ = −55°C 150 VGS = 0 V TJ = 125°C 100 100°C 10 1 25°C 0.1 0.01 4 Figure 5. On−Resistance Variation with Temperature 8 12 16 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 20 Figure 6. Drain−To−Source Leakage Current versus Voltage www.onsemi.com 4 VDS = 0 V C, CAPACITANCE (pF) 4500 4000 VGS = 0 V TJ = 25°C Ciss 3500 3000 Crss 2500 2000 Ciss 1500 1000 500 0 Coss Crss 10 5.0 0 5.0 10 15 20 −VGS −VDS 5 4 16 VDS 3 Q1 VGS 12 Q2 8 2 ID = −6.2 A VDS = −16 V VGS = −4.5 V TJ = 25°C 1 0 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation 1000 5.0 0 10 20 15 4 25 0 Qg, TOTAL GATE CHARGE (nC) Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge 1000 VDD = −16 V ID = −1.0 A VGS = −10 V VDD = −16 V ID = −6.2 A VGS = −4.5 V td(off) tf t, TIME (ns) t, TIME (ns) 20 QT V DS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 5000 VGS , GATE−TO−SOURCE VOLTAGE (VOLTS) NTMD6P02, NVMD6P02 100 tr 100 tf tr td(off) td(on) 10 1 10 td(on) 10 100 1 10 100 RG, GATE RESISTANCE (OHMS) RG, GATE RESISTANCE (OHMS) Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Resistive Switching Time Variation versus Gate Resistance DRAIN−TO−SOURCE DIODE CHARACTERISTICS 100 VGS = 0 V TJ = 25°C 4 −ID , DRAIN CURRENT (AMPS) −IS, SOURCE CURRENT (AMPS) 5 3 2 1 0 0 0.2 0.4 0.6 0.8 1.0 ms 10 10 ms 1 0.1 1.2 1.0 VGS = 2.5 V SINGLE PULSE TC = 25°C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 dc 10 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) −VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 11. Diode Forward Voltage versus Current Figure 12. Maximum Rated Forward Biased Safe Operating Area www.onsemi.com 5 100 NTMD6P02, NVMD6P02 di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 13. Diode Reverse Recovery Waveform TYPICAL ELECTRICAL CHARACTERISTICS Rthja(t) , EFFECTIVE TRANSIENT THERMAL RESISTANCE 10 1 0.1 0.01 D = 0.5 0.2 0.1 0.05 Normalized to qja at 10s. 0.02 0.01 Chip SINGLE PULSE 0.001 1.0E−05 1.0E−04 1.0E−03 1.0E−02 0.0175 W 0.0710 W 0.2706 W 0.5776 W 0.7086 W 0.0154 F 0.0854 F 0.3074 F 1.7891 F 107.55 F 1.0E−01 1.0E+00 t, TIME (s) Figure 14. Thermal Response www.onsemi.com 6 1.0E+01 1.0E+02 Ambient 1.0E+03 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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