NTMFS4833NS
Power MOSFET
30 V, 156 A, Single N−Channel, SO−8 FL
Features
•
•
•
•
•
Accurate, Lossless Current Sensing
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
Optimized Gate Charge to Minimize Switching Losses
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
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V(BR)DSS
30 V
Applications
RDS(ON) MAX
ID MAX
2.2 mW @ 10 V
156 A
3.4 mW @ 4.5 V
127 A
• CPU Power Delivery
• DC−DC Converters
• Low Side Switching
DRAIN
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
30
V
Gate−to−Source Voltage
VGS
±20
V
ID
26
A
Continuous Drain
Current RqJA
(Note 1)
TA = 25°C
Power Dissipation
RqJA (Note 1)
TA = 25°C
PD
2.31
W
Continuous Drain
Current RqJA
(Note 2)
TA = 25°C
ID
16
A
Power Dissipation
RqJA (Note 2)
TA = 85°C
Steady
State
TA = 85°C
0.9
W
Continuous Drain
Current RqJC
(Note 1)
TC = 25°C
ID
156
A
Power Dissipation
RqJC (Note 1)
TC = 25°C
TC = 85°C
Operating Junction and Storage
Temperature
Source Current (Body Diode)
SENSE SOURCE
MARKING
DIAGRAM
S
SO−8 FLAT LEAD S
S
CASE 506BQ
G
1
11.6
PD
TA = 25°C,
tp = 10 ms
Kelvin
18
TA = 25°C
Pulsed Drain
Current
GATE
113
PD
86.2
W
IDM
312
A
TJ, TSTG
−55 to
+150
°C
IS
86
A
Drain to Source DV/DT
dV/dt
6
V/ns
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, VDD = 30 V, VGS = 10 V,
IL = 35 Apk, L = 1.0 mH, RG = 25 W)
EAS
612.5
mJ
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
TL
260
°C
A
Y
W
ZZ
(Do Not Connect)
NC
4833NS
SENSE
AYWZZ
KELVIN
K1
(Do Not Connect)
D
D
= Assembly Location
= Year
= Work Week
= Lot Traceability
ORDERING INFORMATION
Package
Shipping†
NTMFS4833NST1G
SO−8 FL
(Pb−Free)
1500 Tape / Reel
NTMFS4833NST3G
SO−8 FL
(Pb−Free)
5000 Tape / Reel
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
© Semiconductor Components Industries, LLC, 2012
May, 2017 − Rev. 2
1
Publication Order Number:
NTMFS4833NS/D
NTMFS4833NS
THERMAL RESISTANCE MAXIMUM RATINGS
Symbol
Value
Junction−to−Case (Drain)
Parameter
RqJC
1.45
Junction−to−Ambient – Steady State (Note 3)
RqJA
54
Junction−to−Ambient – Steady State (Note )
RqJA
138.7
Unit
°C/W
3. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
4. Surface−mounted on FR4 board using the minimum recommended pad size.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
IDSS
V
30
VGS = 0 V,
VDS = 24 V
mV/°C
TJ = 25 °C
1
TJ = 125°C
10
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
mA
±100
nA
2.5
V
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient
Drain−to−Source On Resistance
VGS(TH)/TJ
RDS(on)
6.8
VGS = 10 V
VGS = 4.5 V
Forward Transconductance
1.5
gFS
ID = 30 A
1.4
ID = 15 A
1.3
ID = 30 A
2.3
ID = 15 A
2.3
VDS = 15 V, ID = 15 A
mV/°C
2.2
3.4
100
mW
S
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
5250
VGS = 0 V, f = 1 MHz, VDS = 12 V
1080
CRSS
500
Total Gate Charge
QG(TOT)
36
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Total Gate Charge
VGS = 4.5 V, VDS = 15 V; ID = 30 A
3.8
15
pF
63
nC
13
QG(TOT)
VGS = 11.5 V, VDS = 15 V;
ID = 30 A
86
nC
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
21
tr
td(OFF)
VGS = 4.5 V, VDS = 15 V, ID = 15 A,
RG = 3.0 W
tf
60
37
44
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
7. With 0V potential from sense lead to source lead, i.e. using a virtual ground.
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2
ns
NTMFS4833NS
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
11
tr
td(OFF)
34
VGS = 11.5 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
ns
53
tf
34
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
TJ = 25°C
0.80
TJ = 125°C
0.67
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 30 A
1.2
V
36
18
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 30 A
ns
18
QRR
32
nC
Source Inductance
LS
0.65
nH
Drain Inductance
LD
0.005
nH
Gate Inductance
LG
1.84
nH
Gate Resistance
RG
1.4
W
PACKAGE PARASITIC VALUES
TA = 25°C
CURRENT SENSE CHARACTERISTICS
Current Sensing Ratio
Iratio
VGS = 5 V, 0-70°C, 5-20 A
357
387
417
Current Sensing Ratio
Iratio
VGS = 5 V, 0-70°C, 1−5 A
351
387
423
Current Sense Temperature Coefficient
(Note 7)
Mirror Resistance
rm(on)
VGS = 5 V
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
7. With 0V potential from sense lead to source lead, i.e. using a virtual ground.
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3
0.006
%/°C
0.80
W
NTMFS4833NS
TYPICAL CHARACTERISTIC CURVES
ID, DRAIN CURRENT (AMPS)
3.6 V
140
120
3.4 V
100
80
3.2 V
60
40
3.0 V
20
2.8 V
0
1
2
4
3
125
100
75
TJ = 125°C
50
TJ = 25°C
25
5
TJ = −55°C
2
2.5
3
3.5
4
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
ID = 30 A
TJ = 25°C
0.014
0.012
0.010
0.008
0.006
0.004
0.002
0
2
6
4
8
10
12
0.004
4.5
TJ = 25°C
0.003
VGS = 4.5 V
0.002
VGS = 10 V
0.001
0
0
10
20
30
40
50
60
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
1.80
1.60
150
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.016
0
VDS ≥ 10 V
175
0
1.5
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
3.8 V
TJ = 25°C
160
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
200
4.0 V thru 6.0 V
180
100,000
VGS = 0 V
ID = 30 A
VGS = 10 V
IDSS, LEAKAGE (nA)
ID, DRAIN CURRENT (AMPS)
200
TJ = 150°C
10,000
1.40
1.20
1.00
TJ = 125°C
1,000
0.80
0.60
−50
100
−25
0
25
50
75
100
125
150
0
5
10
15
20
25
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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4
30
NTMFS4833NS
TYPICAL CHARACTERISTIC CURVES
10
5000
4000
TJ = 25°C
VGS = 0 V
f = 1 MHz
3000
2000
Coss
1000
0
Crss
0
10
5
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
Ciss
15
20
25
30
DRAIN−TO−SOURCE VOLTAGE (VOLTS)
15
8
VDS
10
QGS
4
5
2
0
ID = 30 A
TJ = 25°C
0
IS, SOURCE CURRENT (AMPS)
tr
td(on)
10
1
1
10
50
20
30
60
70
40
QG, TOTAL GATE CHARGE (nC)
10
RG, GATE RESISTANCE (W)
20
15
10
5
0
0.4
100
VGS = 0 V
0.5
0.6
0.8
0.9
1.0
Figure 10. Diode Forward Voltage vs. Current
100
1 ms
10
10 ms
VGS = 20 V
SINGLE PULSE
TC = 25°C
0.01
0.01
0.7
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
1000
0.1
0
90
TJ = 25°C
25
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
1
80
30
tf
100
QGD
Figure 8. Gate−To−Source and Drain−To−Source
Voltage vs. Total Charge
td(off)
I D, DRAIN CURRENT (AMPS)
t, TIME (ns)
VGS = 11.5 V
VDD = 15 V
ID = 15 A
VGS
6
Figure 7. Capacitance Variation
1000
20
QT
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
12
6000
100 ms
1 ms
10 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
dc
0.1
1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
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5
100
NTMFS4833NS
R(t), EFFECTIVE TRANSIENT THERMAL RESPONSE
TYPICAL CHARACTERISTIC CURVES
100
50% (DUTY CYCLE)
10
1.0
0.1
20%
10%
5.0%
2.0%
1.0%
SINGLE PULSE
RqJA = 54°C/W
0.01
0.000001
0.00001
0.0001
0.001
0.1
0.01
t, TIME (s)
Figure 12. FET Thermal Response
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6
1.0
10
100
1000
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN8 5x6, 1.27P
CASE 506BQ
ISSUE C
1
2X
SCALE 2:1
0.20 C
D
A
B
D1
8
7
6
2X
0.20 C
5
E1 E
PIN ONE
IDENTIFIER
NOTE 7
DATE 12 APR 2012
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL
AS THE TERMINAL.
5. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.
4X
1
2
3
c
4
GENERIC
MARKING DIAGRAM*
A1
TOP VIEW
1
0.10 C
A
NOTE 4
SEATING
PLANE
NOTE 6
C
SIDE VIEW
XXXXXX
AYWZZ
DETAIL A
0.10 C
DETAIL A
XXXXXX= Specific Device Code
A
= Assembly Location
Y
= Year
W
= Work Week
ZZ
= Lot Traceability
D2
1
8X
M
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
h
K
L
M
N
h
4
L
N
K
8
e
MILLIMETERS
MAX
MIN
1.10
0.90
−−−
0.05
0.33
0.51
0.20
0.33
5.15 BSC
4.50
5.10
3.90
4.30
6.15 BSC
5.50
6.10
3.00
3.50
1.27 BSC
0.80
1.20
−−−
12 _
0.20
−−−
0.51
0.71
3.25
3.75
1.80
2.20
*This information is generic. Please refer
to device data sheet for actual part
marking.
E2
G
5
SOLDERING FOOTPRINT*
8X
b
BOTTOM VIEW
1.27
PITCH
8X
0.10
C A B
0.05
c
0.75
4X
0.92
NOTE 3
4.84
4X
0.90
2.00
6.59
3.70
0.99
4X
1.00
4.56
5.55
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON38888E
DFN8 5X6, 1.27P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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