NUP4202W1

NUP4202W1 Transient Voltage Suppressors ESD Protection Diodes with Low Clamping Voltage The NUP4202W1 transient voltage suppressor is designed to protect high speed data lines from ESD, EFT, and lightning. Features http://onsemi.com • • • • • • • • • • • Low Clamping Voltage Stand−Off Voltage: 5 V Low Leakage Protection for the Following IEC Standards: IEC 61000−4−2 Level 4 ESD Protection UL Flammability Rating of 94 V−0 This is a Pb−Free Device High Speed Communication Line Protection USB 1.1 and 2.0 Power and Data Line Protection Digital Video Interface (DVI) and HDMI Monitors and Flat Panel Displays MP3 SC−88 LOW CAPACITANCE DIODE TVS ARRAY 500 WATTS PEAK POWER 6 VOLTS PIN CONFIGURATION AND SCHEMATIC I/O 1 VN 2 I/O 3 6 I/O 5 VP 4 I/O Typical Applications MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Peak Power Dissipation 8 x 20 mS @ TA = 25°C (Note 1) Operating Junction Temperature Range Storage Temperature Range Lead Solder Temperature − Maximum (10 Seconds) Human Body Model (HBM) Machine Model (MM) IEC 61000−4−2 Air (ESD) IEC 61000−4−2 Contact (ESD) IEC 61000−4−4 (5/50 ns) Symbol Ppk TJ Tstg TL ESD Value 500 − 40 to +125 − 55 to +150 260 16000 400 20000 20000 40 Unit W °C °C °C V 1 1 SC−88 CASE 419B PLASTIC MARKING DIAGRAM 6 63 MG G EFT A Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Nonrepetitive current pulse per Figure 5 (Pin 5 to Pin 2). 63 = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device Package Shipping See Application Note AND8308/D for further description of survivability specs. NUP4202W1T2G SC−88 3000/Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2009 September, 2009 − Rev. 3 1 Publication Order Number: NUP4202W1/D NUP4202W1 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol IPP VC VRWM IR VBR IT IF VF Ppk C Parameter Maximum Reverse Peak Pulse Current Clamping Voltage @ IPP Working Peak Reverse Voltage Maximum Reverse Leakage Current @ VRWM Breakdown Voltage @ IT Test Current Forward Current Forward Voltage @ IF Peak Power Dissipation Capacitance @ VR = 0 and f = 1.0 MHz IPP VC VBR VRWM IR VF IT V IF I Uni−Directional TVS *See Application Note AND8308/D for detailed explanations of datasheet parameters. ELECTRICAL CHARACTERISTICS (TJ=25°C unless otherwise specified) Parameter Reverse Working Voltage Breakdown Voltage Reverse Leakage Current Clamping Voltage Clamping Voltage Maximum Peak Pulse Current Junction Capacitance Junction Capacitance Clamping Voltage Clamping Voltage Symbol VRWM VBR IR VC VC IPP CJ CJ VC VC (Note 2) IT = 1 mA, (Note 3) VRWM = 5 V IPP = 5 A (Note 4) IPP = 8 A (Note 4) 8x20 ms Waveform (Note 4) VR = 0 V, f = 1 MHz between I/O Pins and GND VR = 0 V, f = 1 MHz between I/O Pins @ IPP = 1 A (Notes 5 and 6) Per IEC 61000−4−2 (Note 7) 3.0 1.5 14.5 Figure 1 and 2 8.5 8.9 6.0 5.0 12.5 20 28 5.0 3.0 Conditions Min Typ Max 5.0 Unit V V mA V V A pF pF V V 2. TVS devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal or greater than the DC or continuous peak operating voltage level. 3. VBR is measured at pulse test current IT. 4. Nonrepetitive current pulse per Figure 5 (Pin 5 to Pin 2). 5. Nonrepetitive current pulse per Figure 5 (Any I/O Pins). 6. Surge current waveform per Figure 5. 7. For test procedure see Figures 3 and 4 and Application Note AND8307/D. Figure 1. ESD Clamping Voltage Screenshot Positive 8 kV Contact per IEC61000−4−2 Figure 2. ESD Clamping Voltage Screenshot Negative 8 kV Contact per IEC61000−4−2 http://onsemi.com 2 NUP4202W1 IEC 61000−4−2 Spec. Test Voltage (kV) 2 4 6 8 First Peak Current (A) 7.5 15 22.5 30 Current at 30 ns (A) 4 8 12 16 Current at 60 ns (A) 2 4 6 8 I @ 60 ns 10% tP = 0.7 ns to 1 ns I @ 30 ns IEC61000−4−2 Waveform Ipeak 100% 90% Level 1 2 3 4 Figure 3. IEC61000−4−2 Spec ESD Gun TVS Oscilloscope 50 W Cable 50 W Figure 4. Diagram of ESD Test Setup The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger 100 % OF PEAK PULSE CURRENT 90 80 70 60 50 40 30 20 10 0 0 20 tP tr systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. PEAK VALUE IRSM @ 8 ms PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms HALF VALUE IRSM/2 @ 20 ms Figure 5. 8 X 20 ms Pulse Waveform 40 t, TIME (ms) 60 80 http://onsemi.com 3 NUP4202W1 TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) 100 PEAK POWER DISSIPATION (%) 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 150 175 200 TA, AMBIENT TEMPERATURE (°C) Figure 6. Pulse Derating Curve 5.0 JUNCTION CAPACITANCE (pF) 4.5 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 1 2 3 4 5 I/O lines I/O−Ground CLAMPING VOLTAGE (V) 4.0 20 18 16 14 12 10 8 6 4 2 0 0 10 20 30 40 50 VBR, REVERSE VOLTAGE (V) PEAK PULSE CURRENT (A) Figure 7. Junction Capacitance vs Reverse Voltage Figure 8. Clamping Voltage vs. Peak Pulse Current (8 x 20 ms Waveform) http://onsemi.com 4 NUP4202W1 APPLICATIONS INFORMATION The new NUP4202W1 is a low capacitance TVS diode array designed to protect sensitive electronics such as communications systems, computers, and computer peripherals against damage due to ESD events or transient overvoltage conditions. Because of its low capacitance, it can be used in high speed I/O data lines. The integrated design of the NUP4202W1 offers surge rated, low capacitance steering diodes and a TVS diode integrated in a single package (SC−88). If a transient condition occurs, the steering diodes will drive the transient to the positive rail of the power supply or to ground. The TVS device protects the power line against overvoltage conditions to avoid damage to the power supply and any downstream components. NUP4202W1 Configuration Options The NUP4202W1 is able to protect up to four data lines against transient overvoltage conditions by driving them to a fixed reference point for clamping purposes. The steering diodes will be forward biased whenever the voltage on the protected line exceeds the reference voltage (Vf or VCC + Vf). The diodes will force the transient current to bypass the sensitive circuit. Data lines are connected at pins 1, 3, 4 and 6. The negative reference is connected at pin 2. This pin must be connected directly to ground by using a ground plane to minimize the PCB’s ground inductance. It is very important to reduce the PCB trace lengths as much as possible to minimize parasitic inductances. Option 1 Protection of four data lines and the power supply using VCC as reference. I/O 1 I/O 2 1 2 3 I/O 3 I/O 4 6 5 4 VCC Option 2 Protection of four data lines with bias and power supply isolation resistor. I/O 1 I/O 2 VCC 1 2 3 I/O 3 I/O 4 6 5 4 10 k The NUP4202W1 can be isolated from the power supply by connecting a series resistor between pin 5 and VCC. A 10 kW resistor is recommended for this application. This will maintain a bias on the internal TVS and steering diodes, reducing their capacitance. Option 3 Protection of four data lines using the internal TVS diode as reference. I/O 1 I/O 2 1 2 3 I/O 3 I/O 4 6 5 4 NC In applications lacking a positive supply reference or those cases in which a fully isolated power supply is required, the internal TVS can be used as the reference. For these applications, pin 5 is not connected. In this configuration, the steering diodes will conduct whenever the voltage on the protected line exceeds the working voltage of the TVS plus one diode drop (Vc = Vf + VTVS). ESD Protection of Power Supply Lines When using diodes for data line protection, referencing to a supply rail provides advantages. Biasing the diodes reduces their capacitance and minimizes signal distortion. Implementing this topology with discrete devices does have disadvantages. This configuration is shown below: For this configuration, connect pin 5 directly to the positive supply rail (VCC), the data lines are referenced to the supply voltage. The internal TVS diode prevents overvoltage on the supply rail. Biasing of the steering diodes reduces their capacitance. http://onsemi.com 5 NUP4202W1 Power Supply VCC D1 IESDpos Protected Data Line Device IESDpos IESDneg D2 IESDneg VF + VCC −VF Looking at the figure above, it can be seen that when a positive ESD condition occurs, diode D1 will be forward biased while diode D2 will be forward biased when a negative ESD condition occurs. For slower transient conditions, this system may be approximated as follows: For positive pulse conditions: Vc = VCC + VfD1 For negative pulse conditions: Vc = −VfD2 ESD events can have rise times on the order of some number of nanoseconds. Under these conditions, the effect of parasitic inductance must be considered. A pictorial representation of this is shown below. Power Supply VCC Protected Device D1 Data Line D2 VC = VCC + Vf + (L diESD/dt) IESDneg IESDpos IESDneg inductance will provide significant benefits in transient immunity. Even with good board layout, some disadvantages are still present when discrete diodes are used to suppress ESD events across datalines and the supply rail. Discrete diodes with good transient power capability will have larger die and therefore higher capacitance. This capacitance becomes problematic as transmission frequencies increase. Reducing capacitance generally requires reducing die size. These small die will have higher forward voltage characteristics at typical ESD transient current levels. This voltage combined with the smaller die can result in device failure. The ON Semiconductor NUP4202W1 was developed to overcome the disadvantages encountered when using discrete diodes for ESD protection. This device integrates a TVS diode within a network of steering diodes. D1 D3 D5 D7 D2 D4 D6 D8 IESDpos 0 Figure 9. NUP4202W1 Equivalent Circuit During an ESD condition, the ESD current will be driven to ground through the TVS diode as shown below. Power Supply VCC VC = −Vf − (L diESD/ dt) D1 Protected Device IESDpos An approximation of the clamping voltage for these fast transients would be: For positive pulse conditions: Vc = VCC + Vf + (L diESD/dt) For negative pulse conditions: Vc = −Vf – (L diESD/dt) As shown in the formulas, the clamping voltage (Vc) not only depends on the Vf of the steering diodes but also on the L diESD/dt factor. A relatively small trace inductance can result in hundreds of volts appearing on the supply rail. This endangers both the power supply and anything attached to that rail. This highlights the importance of good board layout. Taking care to minimize the effects of parasitic Data Line D2 The resulting clamping voltage on the protected IC will be: Vc = VF + VTVS. The clamping voltage of the TVS diode is provided in Figure 8 and depends on the magnitude of the ESD current. The steering diodes are fast switching devices with unique forward voltage and low capacitance characteristics. http://onsemi.com 6 NUP4202W1 TYPICAL APPLICATIONS UPSTREAM USB PORT VBUS VBUS D+ D− GND VBUS USB Controller RT RT VBUS CT CT NUP4202W1 VBUS VBUS D+ D− GND DOWNSTREAM USB PORT VBUS NUP2202W1 RT RT CT CT VBUS D+ D− GND DOWNSTREAM USB PORT Figure 10. ESD Protection for USB Port RJ45 Connector TX+ TX+ TX− TX− PHY Ethernet (10/100) RX+ Coupling Transformers RX+ RX− RX− NUP4202W1 VCC GND N/C N/C Figure 11. Protection for Ethernet 10/100 (Differential Mode) http://onsemi.com 7 NUP4202W1 R1 RTIP R2 VCC R3 T1 RRING T1/E1 TRANCEIVER NUP4202W1 R4 TTIP R5 T2 TRING Figure 12. TI/E1 Interface Protection http://onsemi.com 8 NUP4202W1 PACKAGE DIMENSIONS SC−88/SC70−6/SOT−363 CASE 419B−02 ISSUE W D e NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 419B−01 OBSOLETE, NEW STANDARD 419B−02. DIM A A1 A3 b C D E e L HE MILLIMETERS MIN NOM MAX 0.80 0.95 1.10 0.00 0.05 0.10 0.20 REF 0.10 0.21 0.30 0.10 0.14 0.25 1.80 2.00 2.20 1.15 1.25 1.35 0.65 BSC 0.10 0.20 0.30 2.00 2.10 2.20 INCHES NOM MAX 0.037 0.043 0.002 0.004 0.008 REF 0.004 0.008 0.012 0.004 0.005 0.010 0.070 0.078 0.086 0.045 0.049 0.053 0.026 BSC 0.004 0.008 0.012 0.078 0.082 0.086 MIN 0.031 0.000 6 5 4 HE 1 2 3 −E− b 6 PL 0.2 (0.008) M E M A3 C A SOLDERING FOOTPRINT* 0.50 0.0197 A1 L 0.65 0.025 0.65 0.025 0.40 0.0157 1.9 0.0748 SCALE 20:1 mm inches SC−88/SC70−6/SOT−363 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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