MOSFET - Power, Single
N-Channel
100 V, 3.6 mW, 132 A
NVMFS3D6N10MCL
Features
•
•
•
•
•
•
Small Footprint (5x6 mm) for Compact Design
Low RDS(on) to Minimize Conduction Losses
Low QG and Capacitance to Minimize Driver Losses
NVMFWS3D6N10MCL − Wettable Flank Option for Enhanced
Optical Inspection
AEC−Q101 Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
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V(BR)DSS
RDS(ON) MAX
ID MAX
3.6 mW @ 10 V
100 V
132 A
5.8 mW @ 4.5 V
D (5,6)
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
100
V
Gate−to−Source Voltage
VGS
±20
V
ID
132
A
Continuous Drain
Current RqJC
(Notes 1, 3)
Steady
State
Power Dissipation
RqJC (Note 1)
Steady
State
TC = 25°C
TC = 100°C
TC = 25°C
Steady
State
Power Dissipation
RqJA (Notes 1, 2)
Steady
State
Pulsed Drain Current
TA = 25°C, tp = 10 ms
TA = 25°C
PD
N−CHANNEL MOSFET
W
139
56
ID
TA = 100°C
TA = 25°C
PD
D
1
W
3.2
1.3
IDM
888
A
TJ, Tstg
−55 to
+175
°C
IS
116
A
Single Pulse Drain−to−Source Avalanche
Energy (IAS = 9.2 A)
EAS
739
mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
Source Current (Body Diode)
MARKING
DIAGRAM
A
20
13
TA = 100°C
Operating Junction and Storage Temperature
Range
S (1,2,3)
84
TC = 100°C
Continuous Drain
Current RqJA
(Notes 1, 2, 3)
G (4)
DFN5
CASE 488AA
STYLE 1
S
S
S
G
D
XXXXXX
AYWZZ
D
D
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
W
= Work Week
ZZ
= Lot Traceability
ORDERING INFORMATION
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Junction−to−Case − Steady State
RqJC
0.9
°C/W
Junction−to−Ambient − Steady State (Note 2)
RqJA
39
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2019
November, 2020 − Rev. 3
1
Publication Order Number:
NVMFS3D6N10MCL/D
NVMFS3D6N10MCL
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
100
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
V
60
VGS = 0 V,
VDS = 100 V
mV/°C
TJ = 25 °C
1.0
TJ = 125°C
250
IGSS
VDS = 0 V, VGS = 20 V
VGS(TH)
VGS = VDS, ID = 270 mA
100
mA
nA
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
Threshold Temperature Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
Forward Transconductance
RDS(on)
1
1.5
3
−5.0
VGS = 10 V
ID = 48 A
3.0
3.6
VGS = 4.5 V
ID = 39 A
4.4
5.8
gFS
VDS =5 V, ID = 48 A
163
VGS = 0 V, f = 1 MHz, VDS = 50 V
V
mV/°C
mW
S
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
CISS
4411
Output Capacitance
COSS
1808
Reverse Transfer Capacitance
CRSS
pF
29
Total Gate Charge
QG(TOT)
VGS = 4.5 V, VDS = 50 V; ID = 48 A
29
nC
Total Gate Charge
QG(TOT)
VGS = 10 V, VDS = 50 V; ID = 48 A
60
nC
Threshold Gate Charge
QG(TH)
6
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Plateau Voltage
VGP
3
td(ON)
14.6
VGS = 10 V, VDS = 50 V; ID = 48 A
10
nC
7
V
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
tr
td(OFF)
VGS = 10 V, VDS = 50 V,
ID = 48 A, RG = 6.0 W
tf
7
ns
62.3
20.2
DRAIN−SOURCE DIODE CHARACTERISTICS
Source to Drain Diode Forward Voltage
VSD
Reverse Recovery Time
trr
Reverse Recovery Charge
Qrr
Reverse Recovery Time
trr
Reverse Recovery Charge
Qrr
VGS = 0 V, IS = 2 A
0.65
1.2
VGS = 0 V, IS = 48 A
0.83
1.3
IF = 24 A, di/dt = 300 A/ms
IF = 24 A, di/dt = 1000 A/ms
V
34
ns
73
nC
28
ns
183
nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
NVMFS3D6N10MCL
TYPICAL CHARACTERISTICS
6.0 V
10 V
300
VGS = 4.5 V
250
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
300
3.5 V
8.0 V
200
3.0 V
150
100
50
0
0
1
2
3
4
200
150
100
5
1
2
4
3
Figure 2. Transfer Characteristics
7
8
VGS = 4.5 V
RDS(on), DRAIN−SOURCE
ON−RESISTANCE (mW)
12
8
TJ = 25°C
4
2.2
6
Figure 1. On−Region Characteristics
16
2.4
5
VGS, GATE−TO−SOURCE VOLTAGE (V)
ID = 48 A
0
VDS = 5 V
TJ = −55°C
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
0
1
2
3
4
5
6
7
8
9
6
4
VGS = 10 V
2
0
10
0
50
100
150
200
150
VGS, GATE−TO−SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current
ID = 48 A
VGS = 10 V
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
−75 −50 −25
0
25
50
75
100 125 150 175
IDSS, REVERSE LEAKAGE CURRENT (A)
RDS(on), ON−RESISTANCE (mW)
TJ = 175°C
50
0
20
RDS(on), NORMALIZED DRAIN−SOURCE ON−RESISTANCE
TJ = 25°C
250
300
1E−03
TJ = 175°C
1E−04
TJ = 150°C
1E−05
TJ = 125°C
1E−06
TJ = 100°C
1E−07
TJ = 85°C
1E−08
TJ = 55°C
1E−09
TJ = 25°C
1E−10
5
25
45
65
85
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
NVMFS3D6N10MCL
10K
CISS
C, CAPACITANCE (pF)
1K
COSS
100
CRSS
10
0.1
1000
100
10
1
t, TIME (ns)
6
4
QGS
QGD
VDS = 50 V
ID = 48 A
TJ = 25°C
2
0
10
0
VGS = 10 V
VDS = 50 V
ID = 48 A
td(off)
30
40
60
50
VGS = 0 V
100
tf
tr
10
1
0.1 TJ = 175°C
0.01
TJ = 25°C
0.001
0
20
Figure 8. Gate−to−Source Voltage vs. Total
Charge
10
20
10
30
40
50
0.2
0
0.4
TJ = −55°C
0.6
0.8
1.0
1.2
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
IPEAK, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
8
Figure 7. Capacitance Variation
td(on)
100
10
TC = 25°C
Single Pulse
VGS ≤ 10 V
1
0.1
QG(tot)
QG, TOTAL GATE CHARGE (nC)
100
1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
IS, SOURCE CURRENT (A)
1
VGS = 0 V
f = 1 MHz
VDS = 50 V
VGS, GATE−TO−SOURCE VOLTAGE (V)
TYPICAL CHARACTERISTICS
RDS(on) Limit
Thermal Limit
Package Limit
0.1
1
10
10 ms
0.5 ms
1 ms
10 ms
100
1000
TJ(initial) = 25°C
10
TJ(initial) = 100°C
1
0.00001
0.0001
0.001
0.01
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
TIME IN AVALANCHE (s)
Figure 11. Safe Operating Area
Figure 12. Maximum Drain Current vs. Time in
Avalanche
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4
NVMFS3D6N10MCL
TYPICAL CHARACTERISTICS
100
R(t) (°C/W)
50% Duty Cycle
10 20%
10%
5%
1 2%
1%
0.1
0.01
Single Pulse
0.000001
0.00001
0.0001
0.001
0.01
1
0.1
10
100
1000
t, PULSE TIME (s)
Figure 13. Junction−to−Ambient Transient Thermal Response
DEVICE ORDERING INFORMATION
Marking
Package
Shipping†
NVMFS3D6N10MCLT1G
3D6L10
DFN5
(Pb−Free)
1500 / Tape & Reel
NVMFWS3D6N10MCLT1G
3D6W10
DFN5
(Pb−Free, Wettable Flanks)
1500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA
ISSUE N
1
DATE 25 JUN 2018
SCALE 2:1
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
0.20 C
D
A
2
B
D1
2X
0.20 C
4X
E1
2
q
E
c
1
2
3
A1
4
TOP VIEW
C
DETAIL A
0.10 C
SEATING
PLANE
A
0.10 C
SIDE VIEW
MILLIMETERS
MIN
NOM
MAX
0.90
1.00
1.10
0.00
−−−
0.05
0.33
0.41
0.51
0.23
0.28
0.33
5.00
5.15
5.30
4.70
4.90
5.10
3.80
4.00
4.20
6.00
6.30
6.15
5.70
5.90
6.10
3.45
3.65
3.85
1.27 BSC
0.51
0.575
0.71
1.20
1.35
1.50
0.51
0.575
0.71
0.125 REF
3.00
3.40
3.80
0_
−−−
12 _
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
K
L
L1
M
q
GENERIC
MARKING DIAGRAM*
DETAIL A
1
0.10
b
C A B
0.05
c
8X
XXXXXX
AYWZZ
e/2
e
L
1
4
K
RECOMMENDED
SOLDERING FOOTPRINT*
E2
PIN 5
(EXPOSED PAD)
L1
M
2X
0.495
4.560
2X
1.530
G
D2
2X
BOTTOM VIEW
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
W
= Work Week
ZZ
= Lot Traceability
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
0.475
3.200
4.530
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
1.330
STYLE 2:
2X
PIN 1. ANODE
0.905
2. ANODE
3. ANODE
4. NO CONNECT
0.965
5. CATHODE
1
4X
1.000
4X 0.750
1.270
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON14036D
DFN5 5x6, 1.27P (SO−8FL)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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