NVMFS6H801NWFT1G

MOSFET – Power, Single, N-Channel 80 V, 2.8 mW, 157 A NVMFS6H801N Features • • • • • • Small Footprint (5x6 mm) for Compact Design Low RDS(on) to Minimize Conduction Losses Low QG and Capacitance to Minimize Driver Losses NVMFS6H801NWF − Wettable Flank Option for Enhanced Optical Inspection AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant www.onsemi.com V(BR)DSS RDS(ON) MAX ID MAX 80 V 2.8 mW @ 10 V 157 A D (5) MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Symbol Value Unit Drain−to−Source Voltage VDSS 80 V Gate−to−Source Voltage VGS ±20 V ID 157 A Parameter Continuous Drain Current RqJC (Notes 1, 3) TC = 25°C Power Dissipation RqJC (Note 1) Continuous Drain Current RqJA (Notes 1, 2, 3) Steady State TC = 100°C TC = 25°C TC = 100°C TA = 25°C Power Dissipation RqJA (Notes 1, 2) Pulsed Drain Current Steady State W 166 ID PD D W 3.8 1.9 IDM 900 A TJ, Tstg −55 to +175 °C IS 138 A Single Pulse Drain−to−Source Avalanche Energy (IL(pk) = 12.2 A) EAS 960 mJ Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C Operating Junction and Storage Temperature Range Source Current (Body Diode) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. THERMAL RESISTANCE MAXIMUM RATINGS Parameter MARKING DIAGRAM A 23 16 TA = 100°C TA = 25°C, tp = 10 ms N−CHANNEL MOSFET 83 TA = 100°C TA = 25°C S (1,2,3) 111 PD G (4) Symbol Value Unit Junction−to−Case − Steady State RqJC 0.9 °C/W Junction−to−Ambient − Steady State (Note 2) RqJA 39 1 DFN5 (SO−8FL) CASE 488AA STYLE 1 S S S G D XXXXXX AYWZZ D D XXXXXX = 6H801N XXXXXX = (NVMFS6H801N) or XXXXXX = 801NWF XXXXXX = (NVMFS6H801NWF) A = Assembly Location Y = Year W = Work Week ZZ = Lot Traceability ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 5 of this data sheet. 1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad. 3. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. © Semiconductor Components Industries, LLC, 2016 August, 2020 − Rev. 3 1 Publication Order Number: NVMFS6H801N/D NVMFS6H801N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 80 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/ TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current V 38 VGS = 0 V, VDS = 80 V mV/°C TJ = 25 °C 10 TJ = 125°C 100 IGSS VDS = 0 V, VGS = 20 V VGS(TH) VGS = VDS, ID = 250 mA 100 mA nA ON CHARACTERISTICS (Note 4) Gate Threshold Voltage Threshold Temperature Coefficient VGS(TH)/TJ Drain−to−Source On Resistance Forward Transconductance RDS(on) 2.0 4.0 7.2 VGS = 10 V gFS ID = 50 A VDS =15 V, ID = 50 A 2.3 V mV/°C 2.8 128 mW S CHARGES, CAPACITANCES & GATE RESISTANCE Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS 4120 VGS = 0 V, f = 1 MHz, VDS = 40 V 586 pF 22 Total Gate Charge QG(TOT) VGS = 10 V, VDS = 40 V; ID = 50 A Threshold Gate Charge QG(TH) 11 Gate−to−Source Charge QGS 19 Gate−to−Drain Charge QGD Plateau Voltage VGP 5.0 td(ON) 25 VGS = 10 V, VDS = 40 V; ID = 50 A 64 nC 13 V SWITCHING CHARACTERISTICS (Note 5) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time tr td(OFF) VGS = 10 V, VDS = 64 V, ID = 50 A, RG = 2.5 W tf 74 ns 70 19 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD TJ = 25°C 0.8 TJ = 125°C 0.7 tRR Charge Time ta Discharge Time tb Reverse Recovery Charge VGS = 0 V, IS = 50 A 1.2 V 64 VGS = 0 V, dIS/dt = 100 A/ms, IS = 50 A QRR 36 ns 28 98 nC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 5. Switching characteristics are independent of operating junction temperatures. www.onsemi.com 2 NVMFS6H801N TYPICAL CHARACTERISTICS 300 VGS = 6.0 V to 10 V 250 VGS = 5.5 V 200 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 300 5.0 V 150 100 4.5 V 50 VDS = 10 V 250 200 150 100 TJ = 25°C 50 TJ = 125°C 4.0 V 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 0 8.0 4 5 6 Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 12 TJ = 25°C ID = 50 A 11 10 9 8 7 6 5 4 3 2 5 6 7 8 9 10 VGS, GATE−TO−SOURCE VOLTAGE (V) 7 4.0 TJ = 25°C 3.5 3.0 VGS = 10 V 2.5 2.0 1.5 1.0 5 10 15 20 25 30 35 40 45 50 ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 1.E+06 2.4 2.2 VGS = 10 V ID = 50 A 2.0 TJ = 150°C TJ = 175°C 1.E+05 IDSS, LEAKAGE (nA) RDS(on), NORMALIZED DRAIN−TO− SOURCE RESISTANCE 3 VGS, GATE−TO−SOURCE VOLTAGE (V) 13 1 2 TJ = −55°C VDS, DRAIN−TO−SOURCE VOLTAGE (V) RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW) RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW) 0 1.8 TJ = 125°C 1.E+04 1.6 TJ = 85°C 1.E+03 1.4 1.2 TJ = 25°C 1.E+02 1.0 0.8 1.E+01 0.6 0.4 −50 1.E+00 −25 0 25 50 75 100 125 150 175 5 15 25 35 45 55 65 75 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage www.onsemi.com 3 NVMFS6H801N TYPICAL CHARACTERISTICS C, CAPACITANCE (pF) CISS 1.E+03 COSS 1.E+02 1.E+01 VGS = 0 V TJ = 25°C f = 1 MHz 0 CRSS 10 20 30 40 50 60 70 6 QGD QGS 5 4 3 2 1 0 0 10.05 20.1 30.15 40.2 50.25 60.3 Figure 7. Capacitance Variation Figure 8. Gate−to−Source vs. Total Charge 100 IS, SOURCE CURRENT (A) VGS = 0 V tf 100 tr td(on) td(off) 1 10 10 1 TJ = −55°C TJ = 25°C 0.1 100 TJ = 125°C 0.3 0.4 0.5 0.6 0.7 0.8 0.9 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current TC = 25°C VGS ≤ 10 V Single Pulse 100 IPEAK, (A) t, TIME (ns) 7 QG, TOTAL GATE CHARGE (nC) 1K ID, DRAIN CURRENT (A) 8 VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS = 10 V VDS = 64 V ID = 50 A 10 ms 10 1 0.1 VDS = 40 V TJ = 25°C ID = 50 A 9 80 1000 10 10 VGS, GATE−TO−SOURCE VOLTAGE (V) 1.E+04 RDS(on) Limit Thermal Limit Package Limit 0.1 1 10 TJ (initial) = 25°C TJ (initial) = 100°C 0.5 ms 1 ms 10 ms 1K 100 VDS, DRAIN−TO−SOURCE VOLTAGE (V) TIME IN AVALANCHE (s) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. IPEAK vs. Time in Avalanche www.onsemi.com 4 1 NVMFS6H801N 100 50% Duty Cycle RqJA(t) (°C/W) 10 1 20% 10% 5% 2% 1% 0.1 0.01 0.001 1.E−06 Single Pulse 1.E−05 1.E−04 1.E−03 1.E−02 1.E−01 1.E+00 1.E+01 1.E+02 1.E+03 PULSE TIME (sec) Figure 13. Thermal Characteristics DEVICE ORDERING INFORMATION Device Marking Package Shipping† NVMFS6H801NT1G 6H801N DFN5 (Pb−Free) 1500 / Tape & Reel NVMFS6H801NT3G 6H801N DFN5 (Pb−Free) 5000 / Tape & Reel NVMFS6H801NWFT1G 801NWF DFN5 (Pb−Free, Wettable Flanks) 1500 / Tape & Reel NVMFS6H801NWFT3G 801NWF DFN5 (Pb−Free, Wettable Flanks) 5000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFN5 5x6, 1.27P (SO−8FL) CASE 488AA ISSUE N 1 DATE 25 JUN 2018 SCALE 2:1 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS. 0.20 C D A 2 B D1 2X 0.20 C 4X E1 2 q E c 1 2 3 A1 4 TOP VIEW C DETAIL A 0.10 C SEATING PLANE A 0.10 C SIDE VIEW MILLIMETERS MIN NOM MAX 0.90 1.00 1.10 0.00 −−− 0.05 0.33 0.41 0.51 0.23 0.28 0.33 5.00 5.15 5.30 4.70 4.90 5.10 3.80 4.00 4.20 6.00 6.30 6.15 5.70 5.90 6.10 3.45 3.65 3.85 1.27 BSC 0.51 0.575 0.71 1.20 1.35 1.50 0.51 0.575 0.71 0.125 REF 3.00 3.40 3.80 0_ −−− 12 _ DIM A A1 b c D D1 D2 E E1 E2 e G K L L1 M q GENERIC MARKING DIAGRAM* DETAIL A 1 0.10 b C A B 0.05 c 8X XXXXXX AYWZZ e/2 e L 1 4 K RECOMMENDED SOLDERING FOOTPRINT* E2 PIN 5 (EXPOSED PAD) L1 M 2X 0.495 4.560 2X 1.530 G D2 2X BOTTOM VIEW XXXXXX = Specific Device Code A = Assembly Location Y = Year W = Work Week ZZ = Lot Traceability *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Some products may not follow the Generic Marking. 0.475 3.200 4.530 STYLE 1: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 1.330 STYLE 2: 2X PIN 1. ANODE 0.905 2. ANODE 3. ANODE 4. NO CONNECT 0.965 5. CATHODE 1 4X 1.000 4X 0.750 1.270 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON14036D DFN5 5x6, 1.27P (SO−8FL) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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