NVMYS8D0N04CTWG

NVMYS8D0N04C MOSFET – Power, Single N-Channel 40 V, 8.1 mW, 49 A Features • • • • • • www.onsemi.com Small Footprint (5x6 mm) for Compact Design Low RDS(on) to Minimize Conduction Losses Low QG and Capacitance to Minimize Driver Losses LFPAK4 Package, Industry Standard AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant V(BR)DSS RDS(ON) MAX ID MAX 40 V 8.1 mW @ 10 V 49 A D (5,6) MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Symbol Value Unit Drain−to−Source Voltage VDSS 40 V Gate−to−Source Voltage VGS ±20 V ID 49 A Parameter Continuous Drain Current RqJC (Notes 1, 3) Steady State Power Dissipation RqJC (Note 1) Continuous Drain Current RqJA (Notes 1, 2, 3) TC = 100°C TC = 25°C Power Dissipation RqJA (Notes 1, 2) TA = 25°C PD S (1,2,3) W 38 ID PD W 3.8 1.9 IDM 255 A TJ, Tstg −55 to +175 °C IS 31 A Single Pulse Drain−to−Source Avalanche Energy (IL(pk) = 2.9 A) EAS 81 mJ Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C TA = 25°C, tp = 10 ms Source Current (Body Diode) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. THERMAL RESISTANCE MAXIMUM RATINGS Parameter MARKING DIAGRAM A 16 11 TA = 100°C Operating Junction and Storage Temperature Range N−CHANNEL MOSFET 19 TA = 100°C TA = 25°C G (4) 35 TC = 100°C Steady State Pulsed Drain Current TC = 25°C Symbol Value Unit Junction−to−Case − Steady State RqJC 4.0 °C/W Junction−to−Ambient − Steady State (Note 2) RqJA 39 LFPAK4 CASE 760AB 8D0N04C A WL Y W 8D0N04 C AWLYW = Specific Device Code = Assembly Location =Wafer Lot = Year = Work Week ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 5 of this data sheet. 1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad. 3. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. © Semiconductor Components Industries, LLC, 2018 July, 2019 − Rev. 0 1 Publication Order Number: NVMYS8D0N04C/D NVMYS8D0N04C ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 40 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/ TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current V 23 VGS = 0 V, VDS = 40 V mV/°C TJ = 25 °C 10 TJ = 125°C 250 IGSS VDS = 0 V, VGS = 20 V VGS(TH) VGS = VDS, ID = 30 mA 100 mA nA ON CHARACTERISTICS (Note 4) Gate Threshold Voltage Threshold Temperature Coefficient VGS(TH)/TJ Drain−to−Source On Resistance Forward Transconductance RDS(on) 2.5 3.5 −7 VGS = 10 V gFS ID = 15 A 6.7 V mV/°C 8.1 mW VDS =15 V, ID = 15 A 29 S VGS = 0 V, f = 1 MHz, VDS = 25 V 625 pF CHARGES, CAPACITANCES & GATE RESISTANCE Input Capacitance CISS Output Capacitance COSS 335 Reverse Transfer Capacitance CRSS 15 Total Gate Charge QG(TOT) Threshold Gate Charge VGS = 10 V, VDS = 32 V; ID = 15 A 10 nC QG(TH) 2.2 nC Gate−to−Source Charge QGS 3.5 Gate−to−Drain Charge QGD 1.8 Plateau Voltage VGP 4.8 V 9.5 ns SWITCHING CHARACTERISTICS (Note 5) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(ON) tr VGS = 10 V, VDS = 32 V, ID = 15 A, RG = 1 W 24 td(OFF) 19 tf 6 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD tRR VGS = 0 V, IS = 15 A TJ = 25°C 0.84 TJ = 125°C 0.71 VGS = 0 V, dIS/dt = 100 A/ms, IS = 15 A 24 Charge Time ta Discharge Time tb 12 QRR 11 Reverse Recovery Charge 1.2 V ns 11 nC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 5. Switching characteristics are independent of operating junction temperatures. www.onsemi.com 2 NVMYS8D0N04C TYPICAL CHARACTERISTICS 50 6V 35 30 25 20 5V 15 10 5 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW) ID, DRAIN CURRENT (A) 40 45 0 1 2 VDS = 3 V 40 35 30 25 20 15 TJ = 25°C 10 5 4V 0 3 TJ = 125°C 3.0 5.0 4.5 5.5 Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics TJ = 25°C ID = 15 A 35 30 25 20 15 10 5 0 4 5 6 7 9 8 10 VGS, GATE−TO−SOURCE VOLTAGE (V) 6.0 10 VGS = 10 V 9 8 7 6 5 4 3 0 10 20 30 40 50 60 70 90 100 80 ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 10K 1.9 VGS = 10 V ID = 15 A TJ = 150°C IDSS, LEAKAGE (nA) RDS(on), NORMALIZED DRAIN−TO− SOURCE RESISTANCE TJ = −55°C 4.0 VGS, GATE−TO−SOURCE VOLTAGE (V) 40 1.7 3.5 VDS, DRAIN−TO−SOURCE VOLTAGE (V) RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW) ID, DRAIN CURRENT (A) 50 10 V to 7 V 45 1.5 1.3 1.1 TJ = 125°C 1K TJ = 85°C 100 0.9 0.7 −50 −25 0 25 50 75 100 125 150 175 10 5 10 15 20 25 30 35 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage www.onsemi.com 3 40 NVMYS8D0N04C TYPICAL CHARACTERISTICS VGS, GATE−TO−SOURCE VOLTAGE (V) 1000 C, CAPACITANCE (pF) CISS COSS 100 CRSS 10 1 VGS = 0 V TJ = 25°C f = 1 MHz 0 5 10 15 20 25 30 40 35 10 9 8 7 6 QGD QGS 5 4 3 VDS = 32 V ID = 15 A TJ = 25°C 2 1 0 0 2 1 3 4 5 6 7 8 9 VDS, DRAIN−TO−SOURCE VOLTAGE (V) QG, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation Figure 8. Gate−to−Source Voltage vs. Total Charge 10 100 IS, SOURCE CURRENT (A) VGS = 0 V t, TIME (ns) tr td(off) 10 td(on) tf 1 VGS = 10 V VDS = 32 V 1 5.5 0.5 10 TJ = 125°C 0.3 0.4 0.5 0.7 0.8 0.9 1.0 Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 100 IPEAK, (A) 10 TC = 25°C VGS ≤ 10 V Single Pulse 1 RDS(on) Limit Thermal Limit Package Limit 0.1 TJ (initial) = 25°C 10 10 ms 0.1 0.6 VSD, SOURCE−TO−DRAIN VOLTAGE (V) 100 1 TJ = −55°C TJ = 25°C RG, GATE RESISTANCE (W) 1000 ID, DRAIN CURRENT (A) 10.5 1 10 TJ (initial) = 100°C 0.5 ms 1 ms 10 ms 0.1 1000 100 0.00001 0.0001 0.001 VDS, DRAIN−TO−SOURCE VOLTAGE (V) TIME IN AVALANCHE (s) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. IPEAK vs. Time in Avalanche www.onsemi.com 4 0.01 NVMYS8D0N04C TYPICAL CHARACTERISTICS 100 50% Duty Cycle R(t) (°C/W) 10 1 20% 10% 5% 2% 1% 0.1 0.01 Single Pulse 0.001 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 PULSE TIME (sec) Figure 13. Thermal Characteristics DEVICE ORDERING INFORMATION Device NVMYS8D0N04CTWG Marking Package Shipping† 8D0N04C LFPAK4 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS LFPAK4 5x6 CASE 760AB ISSUE C GENERIC MARKING DIAGRAM* XXXXXX XXXXXX AWLYW DOCUMENT NUMBER: DESCRIPTION: 98AON82777G LFPAK4 5x6 XXXXXX A WL Y W DATE 19 NOV 2019 = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week *This information is generic. Please refer to device data sheet for actual part marking. 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