PCA9517ADMR2G

PCA9517A Level-Translating I2C-Bus Repeater The PCA9517A is an I2C−bus repeater that provides level shifting between low voltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) for I2C−bus or SMBus applications. www.onsemi.com Features • 2 Channel, Bidirectional Buffer Isolates Capacitance and Allows MARKING DIAGRAMS 400 pF on Either Side of the Device • Voltage Level Translation from 0.9 V to 5.5 V and from 2.7 V to • • • • • • • • • • • • • • 5.5 V Footprint and Functional Replacement for PCA9515/15A I2C−bus and SMBus Compatible Active HIGH Repeater Enable Open−Drain Inputs/Outputs Lock−up Free Operation Supports Arbitration and Clock Stretching Across the Repeater, and Multiple Masters I2C and SMBus SCL Clock Frequency up to 1 MHz (The maximum system operating frequency may be less than 1 MHz because of the delays added by the repeater.) Powered−Off High−Impedance I2C−bus Pins A Side Operating Supply Voltage Range of 0.9 V to 5.5 V B Side Operating Supply Voltage Range of 2.7 V to 5.5 V 5 V Tolerant I2C−bus and Enable Pins Available in: Micro−8, SOIC8 ESD Performance: 8 kV HBM, 700 V MM, 2000 V CDM These are Pb−Free Devices © Semiconductor Components Industries, LLC, 2014 May, 2018 − Rev. 2 1 8 Micro8] DM SUFFIX CASE 846A 9517 AYWG G 1 8 9517 AYWW G SOIC−8 CASE 751 8 1 1 A L M Y W G = Assembly Location = Wafer Lot = Date Code = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information on page 12 of this data sheet. Publication Order Number: PCA9517A/D PCA9517A General Description PCA9515A, PCA9516A, PCA9517A (port B), or PCA9518. The A side of two or more PCA9517As can be connected together, however, to allow a star topology with the A side on the common bus, and the A side can be connected directly to any other buffer with static or dynamic offset voltage. Multiple PCA9517As can be connected in series, A side to B side, with no build−up in offset voltage with only time−of−flight delays to consider. The PCA9517A drivers are not enabled unless the bus is idle, VCC(A) is above 0.8 V and VCC(B) is above 2.5 V. The EN pin can also be used to turn the drivers on and off under system control. Caution should be observed to only change the state of the enable pin when the bus is idle. The output pull−down on the B side internal buffer LOW is set for approximately 0.5 V, while the input threshold of the internal buffer is set about 70 mV lower (0.43 V). When the B side I/O is driven LOW internally, the LOW is not recognized as a LOW by the input. This prevents a lock−up condition from occurring. The output pull−down on the A side drives a hard LOW and the input level is set at 0.3 VCC(A) to accommodate the need for a lower LOW level in systems where the low voltage side supply voltage is as low as 0.9 V. The PCA9517A is an I2C−bus repeater that provides level shifting between low voltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) for I2C−bus or SMBus applications. While retaining all the operating modes and features of the I2C−bus system during the level shifts, it also permits extension of the I2C−bus by providing bidirectional buffering for both the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF. Using the PCA9517A enables the system designer to isolate two halves of a bus for both voltage and capacitance. The SDA and SCL pins are overvoltage tolerant and are high−impedance when the PCA9517A is unpowered. The 2.7 V to 5.5 V bus B side drivers behave much like the drivers on the PCA9515A device, while the adjustable voltage bus A side drivers drive more current and eliminate the static offset voltage. This results in a LOW on the B side translating into a nearly 0 V LOW on the A side which accommodates smaller voltage swings of lower voltage logic. The static offset design of the B side PCA9517A I/O drivers prevents them from being connected to another device that has a rise time accelerator including the PCA9510, PCA9511, PCA9512, PCA9513, PCA9514, BLOCK DIAGRAM Figure 1. Block Diagram of PCA9517A www.onsemi.com 2 PCA9517A PIN ASSIGNMENT PCA9517A Figure 2. SOIC8 / Micro8 PIN DESCRIPTIONS Symbol Pin VCC(A) 1 A−Side Supply Voltage (0.9 V to 5.5 V) Description SCLA 2 Open−Drain I/O, Serial Clock A−Side Bus SDAA 3 Open−Drain I/O, Serial Data A−Side Bus GND 4 Ground EN 5 Active−HIGH Repeater Enable SDAB 6 Open−Drain I/O, Serial Data B−Side Bus SCLB 7 Open−Drain I/O, Serial Clock B−Side Bus VCC(B) 8 B−Side Supply Voltage (2.7 V to 5.5 V) FUNCTIONAL DESCRIPTION Please refer to Figure 1 “Block Diagram of PCA9517A”. The PCA9517A enables I2C−bus or SMBus translation down to VCC(A) as low as 0.9 V without degradation of system performance. The PCA9517A contains two bidirectional open−drain buffers specifically designed to support up−translation/down−translation between the low voltage (as low as 0.9 V) and a 3.3 V or 5 V I2C−bus or SMBus. All inputs and I/Os are overvoltage tolerant to 5.5 V even when the device is unpowered (VCC(B) and/or VCC(A) = 0 V). The PCA9517A includes a power−up circuit that keeps the output drivers turned off until VCC(B) is above 2.5 V and the VCC(A) is above 0.8 V. VCC(B) and VCC(A) can be applied in any sequence at power−up. After power−up and with the enable (EN) HIGH, a LOW level on port A (below 0.3 VCC(A)) turns the corresponding port B driver (either SDA or SCL) on and drives port B down to about 0.5 V. When port A rises above 0.3 VCC(A), the port B pull−down driver is turned off and the external pull−up resistor pulls the pin HIGH. When port B falls first and goes below 0.3VCC(B), the port A driver is turned on and port A pulls down to 0 V. The port B pull−down is not enabled unless the port B voltage goes below 0.4 V. If the port B low voltage does not go below 0.5 V, the port A driver will turn off when port B voltage is above 0.7 VCC(B). If the port B low voltage goes below 0.4 V, the port B pull−down driver is enabled and port B will only be able to rise to 0.5 V until port A rises above 0.3 VCC(A), then port B will continue to rise being pulled up by the external pull−up resistor. The VCC(A) is only used to provide the 0.3 VCC(A) reference to the port A input comparators and for the power good detect circuit. The PCA9517A logic and all I/Os are powered by the VCC(B) pin. Enable Pin (EN) The EN pin is active HIGH with an internal pull−up to VCC(B) and allows the user to select when the repeater is active. This can be used to isolate a badly behaved slave on power−up until after the system power−up reset. It should never change state during an I2C−bus operation because disabling during a bus operation will hang the bus and enabling part way through a bus cycle could confuse the I2C−bus parts being enabled. The EN pin should only change state when the global bus and the repeater port are in an idle state to prevent system failures. I2C−Bus Systems As with the standard I2C−bus system, pull−up resistors are required to provide the logic HIGH levels on the buffered bus (standard open−collector configuration of the I2C−bus). The size of these pull−up resistors depends on the system, but each side of the repeater must have a pull−up resistor. www.onsemi.com 3 PCA9517A 3 mA in a generic I2C−bus system where Standard−mode devices and multiple masters are possible. Under certain conditions, higher termination currents can be used. This part designed to work with Standard−mode, Fast−mode and Fast−mode+ I2C−bus devices, in addition to SMBus devices. Standard−mode I2C−bus devices only specify 3 mA output drive; this limits the termination current to APPLICATION DESIGN−IN INFORMATION A typical application is shown in Figure 3. In this example, the system master is running on a 3.3 V I2C−bus while the slave is connected to a 1.2 Vbus. Both buses run at 400 kHz. Master devices can be placed on either bus. Figure 3. Typical Application causes the internal driver on the A side to turn on and pull the A side pin down to ground. In order to illustrate what would be seen in a typical application, refer to Figures 4 and 5. If the bus master in Figure 3 were to write to the slave through the PCA9517A, waveforms shown in Figure 4 would be observed on the A bus. This looks like a normal I2C−bus transmission except that the HIGH level may be as low as 0.9 V, and the turn on and turn off of the acknowledge signals are slightly delayed. The PCA9517A is 5 V tolerant, so it does not require any additional circuitry to translate between 0.9 V to 5.5 V bus voltages and 2.7 V to 5.5 V bus voltages. When the A side of the PCA9517A is pulled LOW by a driver on the I2C−bus, a comparator detects the falling edge when it goes below 0.3 VCC(A) and causes the internal driver on the B side to turn on, causing the B side to pull down to about 0.5 V. When the B side of the PCA9517A falls, first a CMOS hysteresis type input detects the falling edge and Figure 4. Bus A (0.9 V to 5.5 V Bus) Waveform while the A bus side rises above 0.3VCC(A), then it continues HIGH. It is important to note that any arbitration or clock stretching events require that the LOW level on the B bus side at the input of the PCA9517A (VIL) be at or below 0.4 V to be recognized by the PCA9517A and then transmitted to the A bus side. On the B bus side of the PCA9517A (Figure 5), the clock and data lines would have a positive offset from ground equal to the VOL of the PCA9517A. After the 8th clock pulse, the data line will be pulled to the VOL of the slave device, which is very close to ground in this example. At the end of the acknowledge, the level rises only to the LOW level set by the driver in the PCA9517A for a short delay www.onsemi.com 4 PCA9517A Figure 5. Bus B (2.7 V to 5.5 V Bus) Waveform Multiple PCA9517A A sides can be connected in a star configuration (Figure 6), allowing all nodes to communicate with each other. Figure 6. Typical Star Application Multiple PCA9517As can be connected in series (Figure 7) as long as the A side is connected to the B side. I2C−bus slave devices can be connected to any of the bus segments. The number of devices that can be connected in series is limited by repeater delay/time−of−flight considerations on the maximum bus speed requirements. www.onsemi.com 5 PCA9517A Figure 7. Typical Series Application Figure 8. Typical Application of PCA9517A Driving a Short Cable www.onsemi.com 6 PCA9517A MAXIMUM RATINGS Symbol Value Unit VCC(B) Supply Voltage Port B −0.5 to +7.0 V VCC(A) Supply Voltage Port A −0.5 to +7.0 V VI/O Input/Output Pin Voltage SDAB, SCLB, EN −0.5 to +7.0 V II/O Input/Output Current SDAA, SDAB, SCLA, SCLB ±50 mA Input Current EN ±50 mA II Parameter ICC DC Supply Current ±100 mA IGND DC Ground Current ±100 mA TSTG Storage Temperature Range −65 to +150 °C TL Lead Temperature, 1 mm from Case for 10 Seconds 260 °C TJ Junction Temperature Under Bias 150 °C qJA Thermal Resistance SOIC8 (Note 1) MIicro8 146 205 °C/W PD Power Dissipation in Still Air at 85°C SOIC8 MIicro8 856 609 mW MSL FR VESD ILATCHUP Moisture Sensitivity Level 1 Flammability Rating Oxygen Index: 28 to 34 ESD Withstand Voltage UL 94 V−0 @ 0.125 in Human Body Mode (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) Latchup Performance Above VCC and Below GND at 125°C (Note 5) > 8000 > 700 >2000 V ±100 mA Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow. 2. Tested to EIA / JESD22−A114−A. 3. Tested to EIA / JESD22−A115−A. 4. Tested to JESD22−C101−A. 5. Tested to EIA / JESD78. RECOMMENDED OPERATING CONDITIONS Symbol Min Max Unit VCC(B) Supply Voltage Port B 2.7 5.5 V VCC(A) (Note 6) Supply Voltage Port A 0.9 5.5 V 0 5.5 V −40 +85 °C VI/O TA Parameter Input/Output Pin Voltage Operating Free−Air Temperature 6. Low Level Supply Voltage. www.onsemi.com 7 PCA9517A DC CHARACTERISTICS VCC(B), VCC(A) = 2.7 V to 5.5 V, unless otherwise specified. TA = −405C to +855C Symbol Parameter Conditions Min Typ Max Unit 1 mA SUPPLIES ICC(A) Supply Current Port A ICCH HIGH−Level Supply Current Both Channels HIGH; VCC = 5.5 V; SDAn = SCLn = VCC 1.5 5 mA LOW−Level Supply Current Both Channels LOW; VCC = 5.5 V; One SDA and SCL = GND; Other SDA and SCL Open 1.5 5 mA VCC = 5.5 V; SDAn = SCLn = VCC 1.5 5 mA ICCL ICC(A)c Contention Port A Supply Current Pin VCC(A) INPUT / OUTPUT SDAB, SCLB VIH High−Level Input Voltage VIL (Note 7) Low−Level Input Voltage VILc Contention Low−Level Input Voltage VIK Input Clamping Voltage VOL LOW−Level Output Voltage VOL − VILc (Note 8) 0.7 x VCC(B) 0.3 x VCC(B) −0.5 Input Leakage Current IIL LOW−Level Input Current ILOH HIGH−Level Output Leakage Current CI/O Input/Output Capacitance 0.4 II = −18 mA IOL = 100 mA or 6 mA 0.43 0.52 V V −1.2 V 0.6 V mV Difference between LOW−Level Output Voltage and LOW−Level Input Voltage Contention ILI V 80 VI = 3.6 V ±1 mA SDA, SCL, VI = 0.2 V 10 mA VO = 3.6 V 10 mA VI = 3 V or 0 V; VCC = 3.3 V 5 7 VI = 3 V or 0 V; VCC = 0 V 5 7 pF INPUT / OUTPUT SDAA, SCLA 0.7 x VCC(A) VIH High−Level Input Voltage VIL (Note 9) Low−Level Input Voltage VIK Input Clamping Voltage II = −18 mA VOL LOW−Level Output Voltage IOL = 6 mA ILI Input Leakage Current IIL LOW−Level Input Current ILOH HIGH−Level Output Leakage Current CI/O Input/Output Capacitance V 0.1 0.3 x VCC(A) V −1.2 V 0.2 V VI = 3.6 V ±1 mA SDA, SCL, VI = 0.2 V 10 mA VO = 3.6 V 10 mA VI = 3 V or 0 V; VCC = 3.3 V 5 7 VI = 3 V or 0 V; VCC = 0 V 5 7 pF INPUT EN VIH 0.7 x VCC(B) High−Level Input Voltage V 7. VIL specification is for the first LOW level seen by the SDAB/SCLB lines. VILc is for the second and subsequent LOW levels seen by the SDAB/SCLB lines. 8. Guaranteed by design, not production tested. 9. VIL for port A with envelope noise must be below 0.3 VCC(A) for stable performance. www.onsemi.com 8 PCA9517A DC CHARACTERISTICS VCC(B), VCC(A) = 2.7 V to 5.5 V, unless otherwise specified. TA = −405C to +855C Symbol Parameter Conditions Min Typ Max Unit 0.3 x VCC(B) V ±1 mA INPUT EN VIL Low−Level Input Voltage ILI Input Leakage Current IIL LOW−Level Input Current CI Input Capacitance VI = VCC VI = 0.2 V, EN; VCC = 3.6 V −10 −35 mA VI = 3 V or 0 V 6 7 pF 7. VIL specification is for the first LOW level seen by the SDAB/SCLB lines. VILc is for the second and subsequent LOW levels seen by the SDAB/SCLB lines. 8. Guaranteed by design, not production tested. 9. VIL for port A with envelope noise must be below 0.3 VCC(A) for stable performance. www.onsemi.com 9 PCA9517A AC CHARACTERISTICS VCC = 2.7 V to 5.5 V, unless otherwise specified. (Notes 10 and 11) TA = −405C to +855C Parameter Symbol Conditions Min Typ (Note 12) Max Unit 100 170 250 ns tPLH (Note 13) LOW−to−HIGH Propagation Delay B−Side to A−Side; Figure 11 tPHL (Note 14) HIGH−to−LOW Propagation Delay B−Side to A−Side; Figure 9 tTLH (Note 14) tTHL (Note 14) LOW−to−HIGH Output Transition Time HIGH−to−LOW Output Transition Time ns VCC(A) ≤ 2.7 V 10 80 110 VCC(A) ≥ 3.0 V 5 66 300 A−Side; Figure 9 10 20 30 VCC(A) < 2.7 V 5 20 30 VCC(A) > 3.0 V 10 50 70 ns ns A−Side; Figure 9 VCC(A) ≤ 2.7 V 77 105 VCC(A) > 3.0 V 70 105 tPLH (Note 15) LOW−to−HIGH Propagation Delay A−Side to B−Side; Figure 10 25 53 150 ns tPHL (Note 15) HIGH−to−LOW Propagation Delay A−Side to B−Side; Figure 10 60 79 230 ns tTLH LOW−to−HIGH Output Transition Time B−Side; Figure 10 120 140 170 ns tTHL HIGH−to−LOW Output Transition Time B−Side; Figure 10 1 48 90 ns tsu (Note 16) Setup Time EN HIGH Before START Condition 100 ns th (Note 16) Hold Time EN HIGH After STOP Condition 160 ns 10. Times are specified with loads indicated in Figure 12. Different load resistance and capacitance will alter the RC time constant, thereby changing the propagation delay and transition times. 11. Pull−up voltages are VCC(A) on the A side and VCC(B) on the B side. 12. Typical values were measured with VCC(A) = 3.3 V at Tamb = 25°C, unless otherwise noted. 13. The tPLH delay data from B side to A side is measured at 0.5 V on the B side to 0.5 VCC(A) on the A side when VCC(A) is less than 2 V, and 1.5 V on the A side if VCC(A) is greater than 2 V. 14. Typical value measured with VCC(A) = 2.7 V at Tamb = 25°C. 15. The propagation delay data from A side to B side is measured at 0.3 VCC(A) on the A side to 1.5 V on the B side. 16. The enable pin, EN, should only change state when the global bus and the repeater port are in an idle state. AC WAVEFORMS Figure 9. Propagation Delay and Transition Times; B−Side to A−Side Figure 10. Propagation Delay and Transition Times; A−Side to B−Side www.onsemi.com 10 PCA9517A Figure 11. Propagation Delay; B−Side to A−Side TEST SETUP VCC(A) RL Pulse Generator CL RT VCC(B) RL Pulse Generator VCC(A) VCC(B) VCC(A) CL RT Figure 12. Test Circuit for Open−Drain Outputs www.onsemi.com 11 PCA9517A ORDERING INFORMATION Package Shipping PCA9517ADR2G Device SOIC8 (Pb−Free) 3000 / Tape & Reel PCA9517ADMR2G Micro−8 (Pb−Free) 4000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 12 PCA9517A PACKAGE DIMENSIONS Micro8t CASE 846A−02 ISSUE J D HE PIN 1 ID NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. 846A-01 OBSOLETE, NEW STANDARD 846A-02. E b 8 PL 0.08 (0.003) −T− DIM A A1 b c D E e L HE e M T B S A S SEATING PLANE A 0.038 (0.0015) A1 MILLIMETERS NOM MAX −− 1.10 0.08 0.15 0.33 0.40 0.18 0.23 3.00 3.10 3.00 3.10 0.65 BSC 0.40 0.55 0.70 4.75 4.90 5.05 MIN −− 0.05 0.25 0.13 2.90 2.90 L c RECOMMENDED SOLDERING FOOTPRINT* 8X 8X 0.48 0.80 5.25 0.65 PITCH DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 13 INCHES NOM −− 0.003 0.013 0.007 0.118 0.118 0.026 BSC 0.016 0.021 0.187 0.193 MIN −− 0.002 0.010 0.005 0.114 0.114 MAX 0.043 0.006 0.016 0.009 0.122 0.122 0.028 0.199 PCA9517A PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 K −Y− G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X S J MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Micro8 is a trademark of International Rectifier. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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