SN74LS76AN

SN74LS76A Dual JK Flip-Flop with Set and Clear The SN74LS76A offers individual J, K, Clock Pulse, Direct Set and Direct Clear inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The Logic Level of the J and K inputs will perform according to the Truth Table as long as minimum set-up times are observed. Input data is transferred to the outputs on the HIGH-to-LOW clock transitions. http://onsemi.com LOW POWER SCHOTTKY MODE SELECT – TRUTH TABLE OPERATING MODE Set Reset (Clear) *Undetermined Toggle Load “0” (Reset) Load “1” (Set) Hold * INPUTS SD L H L H H H H CD H L L H H H H J X X X h l h l K X X X h h l l OUTPUTS Q H L H q L H q Q L H H q H L q 16 1 Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable if SD and CD go HIGH simultaneously. PLASTIC N SUFFIX CASE 648 H, h = HIGH Voltage Level L, I = LOW Voltage Level X = Immaterial l, h (q) = Lower case letters indicate the state of the referenced input i, h (q) = (or output) one setup time prior to the HIGH–to–LOW clock transition 16 1 SOIC D SUFFIX CASE 751B GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4.75 0 Typ 5.0 25 Max 5.25 70 –0.4 8.0 Unit V °C mA mA ORDERING INFORMATION Device SN74LS76AN SN74LS76AD SN74LS76ADR2 Package 16 Pin DIP SOIC–16 SOIC–16 Shipping 2000 Units/Box 38 Units/Rail 2500/Tape & Reel © Semiconductor Components Industries, LLC, 2001 1 October, 2001 – Rev. 7 Publication Order Number: SN74LS76A/D SN74LS76A LOGIC DIAGRAM 2 Q Q 16 1 CLEAR (CD) J SET (SD) K 4 K CP JC Q D 3 VCC = PIN 5 GND = PIN 13 CLOCK (CP) 14 SD Q 15 12 6 9 K CP JC Q D 8 10 LOGIC SYMBOL 7 SD Q 11 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.7 –0.65 3.5 0.25 VOL Output Output LOW Voltage 0.35 J, K Clear Clock IIH Input Input HIGH Current J, K Clear Clock Input LOW Current Short Circuit Current (Note 1) J, K Clear, Clock –20 0.1 0.3 0.4 –0.4 –0.8 –100 mA VCC = MAX, VIN = 7.0 V 0.5 20 60 80 V µA 0.4 Min 2.0 0.8 –1.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = –18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MAX, VIN = 2.7 V IIL IOS mA mA VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX ICC Power Supply Current 6.0 mA Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits Symbol fMAX tPLH tPHL Parameter Maximum Clock Frequency Clock, Clear Clock Clear, Set to Output Output 15 20 ns Min 30 Typ 45 15 20 Max Unit MHz ns VCC = 5.0 V 15 CL = 15 pF Test Conditions AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol tW tW ts th Parameter Clock Pulse Width High Clear Set Pulse Width Setup Time Hold Time Min 20 25 20 0 Typ Max Unit ns ns ns ns VCC = 5 0 V 5.0 Test Conditions http://onsemi.com 2 SN74LS76A PACKAGE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 648–08 ISSUE R –A– 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 B 1 8 F S C L –T– H G D 16 PL SEATING PLANE K J TA M M 0.25 (0.010) M D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J –A– 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 –B– 1 8 P 8 PL 0.25 (0.010) M B S G F K C –T– SEATING PLANE R X 45 _ M D 16 PL M J 0.25 (0.010) TB S A S http://onsemi.com 3 SN74LS76A ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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