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or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
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STK551U3A2A-E
Intelligent Power Module (IPM)
600 V, 20 A
Overview
This “Inverter Power IPM” is highly integrated device containing all High
Voltage (HV) control from HV-DC to 3-phase outputs in a single SIP
module (Single-In line Package). Output stage uses IGBT / FRD
technology and implements Under Voltage Protection (UVP) and Over
Current Protection (OCP) with a Fault Detection output flag. Internal
Boost diodes are provided for high side gate boost drive.
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Function
Single control power supply due to Internal bootstrap circuit for high side
pre-driver circuit
All control input and status output are at low voltage levels directly
compatible with microcontrollers
Built-in dead time for shoot-thru protection
Externally accessible embedded thermistor for substrate temperature
measurement
The level of the over-current protection current is adjustable with the
external resistor, “RSD”
Certification
UL1557 (File Number : E339285)
Specifications
Absolute Maximum Ratings at Tc = 25C
Supply voltage
Parameter
Symbol
VCC
V+ to V-, surge < 500 V
Conditions
Collector-emitter voltage
VCE
V+ to U, V, W or U, V, W to V-
Output current
Io
Output peak current
Iop
Ratings
*1
Unit
450
V
600
V
V+, V-, U, V, W terminal current
±20
A
V+, V-, U, V, W terminal current at Tc = 100C
±10
A
V+, V-, U, V, W terminal current for a Pulse width of 1 ms.
±40
A
Pre-driver voltage
VD1, 2, 3, 4
VB1 to U, VB2 to V, VB3 to W, VDD to VSS
20
V
Input signal voltage
VIN
HIN1, 2, 3, LIN1, 2, 3
*2
0.3 to VDD
V
FAULT terminal voltage
VFAULT
FAULT terminal
0.3 to VDD
V
Maximum power dissipation
Pd
IGBT per channel
39
W
Junction temperature
Tj
IGBT, FRD
150
C
40 to +125
C
Storage temperature
Tstg
Operating case temperature
Tc
Tightening torque
IPM case temperature
Case mounting screws
*3
40 to +100
C
1.0
Nm
Withstand voltage
Vis
50 Hz sine wave AC 1 minute
*4
2000
Reference voltage is “VSS” terminal voltage unless otherwise specified.
*1: Surge voltage developed by the switching operation due to the wiring inductance between + and U-(V-, W-) terminal.
*2: Terminal voltage: VD1 = VB1 to U, VD2 = VB2 to V, VD3 = VB3 to W, VD4 = VDD to VSS
*3: Flatness of the heat-sink should be 0.15 mm and below.
*4: Test conditions : AC 2500 V, 1 second.
VRMS
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
ORDERING INFORMATION
See detailed ordering and shipping information on page 15 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
December 2016 - Rev. 3
1
Publication Order Number :
STK551U3A2A-E/D
STK551U3A2A-E
Electrical Characteristics at Tc 25C, VD1, VD2, VD3, VD4 = 15 V
Parameter
Symbol
Conditions
Test
circuit
Ratings
Unit
min
typ
max
-
-
0.1
mA
-
-
0.1
mA
-
1.9
2.7
-
2.3
3.1
-
1.6
-
Power output section
Collector-emitter cut-off
current
Bootstrap diode reverse
current
Collector to emitter saturation
voltage
ICE
IR(BD)
VCE(SAT)
VCE = 600 V
Fig.1
VR(BD)
Io = 20 A
Tj = 25C
Upper side
Io = 10 A
Tj = 100C
Upper side
Lower side *1
Fig.2
Lower side *1
-
1.8
-
Io = 20 A
Tj = 25C
Upper side
-
2.1
2.8
-
2.5
3.2
Io = 10 A
Tj = 100C
Upper side
-
1.6
-
-
1.8
-
Lower side *1
Diode forward voltage
VF
Fig.3
Junction to case
thermal resistance
θj-c(T)
IGBT
-
-
3.2
θj-c(D)
FRD
-
-
5
Lower side *1
V
V
C/W
Control (Pre-driver) section
Pre-driver power dissipation
ID
High level Input voltage
Vin H
Low level Input voltage
Input threshold voltage
hysteresis*1
Logic 1 input leakage current
Logic 0 input leakage current
FAULT terminal input electric
current
FAULT clear time
Vin L
Vinth(hys)
VD1, 2, 3 = 15 V
Fig.4
VD4 = 15 V
HIN1, HIN2, HIN3,
LIN1, LIN2, LIN3 to VSS
0.08
0.4
1.6
4
2.5
-
-
V
-
-
0.8
V
0.5
0.8
-
V
mA
IIN+
VIN = +3.3 V
-
100
143
A
IIN-
VIN = 0 V
-
-
2
A
-
2
-
mA
18
-
80
ms
10.5
11.1
11.7
V
10.3
10.9
11.5
V
0.14
0.2
-
A
IoSD
FLTCLR
FAULT : ON / VFAULT = 0.1 V
Fault output latch time.
VCC and VS undervoltage
positive going threshold.
VCC and VS undervoltage
negative going threshold.
VCC and VS undervoltage
hysteresis
Over current protection level
VCCUV+
VSUV+
VCCUVVSUVVCCUVH
VSUVHISD
PW = 100 μs, RSD = 0 Ω
Output level for current monitor
ISO
Io = 20 A
Rt
Thermistor Resistance
at 25C (Vth)
Thermistor for substrate
temperature
-
Reference voltage is “VSS” terminal voltage unless otherwise specified.
*1 : The lower side’s VCE(SAT) and VF include a loss by the shunt resistance
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2
Fig.5
32.7
-
41.5
A
0.37
0.40
0.43
V
90
100
110
kΩ
STK551U3A2A-E
Parameter
Symbol
Conditions
Test
circuit
Ratings
Unit
min
typ
max
0.3
0.4
1.1
-
0.7
1.4
-
295
-
J
Switching Character
Switching time
tON
tOFF
Io = 20 A
Inductive load
Turn-on switching loss
Eon
Turn-off switching loss
Eoff
Total switching loss
Etot
Ic = 10 A, V = 300 V,
VDD = 15 V, L = 3.9mH
Tc = 25C
Turn-on switching loss
Eon
+
Turn-off switching loss
Eoff
Total switching loss
Etot
Diode reverse recovery energy
Erec
Diode reverse recovery time
Trr
IF = 10 A, V = 400 V, VDD = 15 V,
L = 3.9 mH, Tc = 100C
RBSOA
Io = 40 A, VCE = 450 V
SCSOA
VCE = 400 V, Tc = 100C
dv/dt
Between U, V, W to U-, V-, W-
Reverse bias safe operating
area
Short circuit safe operating
area
Allowable offset voltage slew
rate
+
Ic = 10 A, V = 300 V,
VDD = 15 V, L = 3.9 mH
Tc = 100C
+
Fig.6
s
-
230
-
J
-
525
-
J
-
365
-
J
-
290
-
J
-
655
-
J
-
13
-
J
-
57
-
ns
Full square
4
-
-
50
-
50
s
V/ns
Reference voltage is “VSS” terminal voltage unless otherwise specified.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
Notes :
1.
When the internal protection circuit operates, a Fault signal is turned ON (When the Fault terminal is low level, Fault signal is ON
state : output form is open DRAIN) but the Fault signal does not latch. After protection operation ends,it returns automatically within
about 18 ms to 80 ms and resumes operation beginning condition. So, after Fault signal detection, set all input signals to OFF (Low)
at once.However, the operation of pre-drive power supply low voltage protection (UVLO : with hysteresis about 0.2 V) is as follows.
Upper side :
The gate is turned off and will return to regular operation when recovering to the normal voltage, but the latch will continue till the
input signal will turn ‘low’.
Lower side :
The gate is turned off and will automatically reset when recovering to normal voltage. It does not depend on input signal voltage.
2.
3.
When assembling the IPM on the heat sink with M3 type screw, tightening torque range is 0.6 Nm to 0.9 Nm.
The pre-drive low voltage protection is the feature to protect devices when the pre-driver supply voltage falls due to an operating
malfunction.
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3
STK551U3A2A-E
Module Pin-Out Description
Pin No.
Name
Description
1
VB3
High Side Floating Supply Voltage 3
2
W, VS3
Output 3 - High Side Floating Supply Offset Voltage
3
―
Without Pin
4
―
Without Pin
5
VB2
High Side Floating Supply voltage 2
6
V,VS2
Output 2 - High Side Floating Supply Offset Voltage
7
―
Without Pin
8
―
Without Pin
9
VB1
High Side Floating Supply voltage 1
10
U,VS1
Output 1 - High Side Floating Supply Offset Voltage
11
―
Without Pin
12
―
none
13
V+
Positive Bus Input Voltage
14
NA
none
15
NA
none
16
V-
Negative Bus Input Voltage
17
HIN1
Logic Input High Side Gate Driver - Phase 1
18
HIN2
Logic Input High Side Gate Driver - Phase V
19
HIN3
Logic Input High Side Gate Driver - Phase W
20
LIN1
Logic Input Low Side Gate Driver - Phase U
21
LIN2
Logic Input Low Side Gate Driver - Phase V
22
LIN3
Logic Input Low Side Gate Driver - Phase W
23
FLTEN
Enable input / Fault output
24
ISO
Current monitor output
25
VDD
+15 V Main Supply
26
VSS
Negative Main Supply
27
ISD
Over current detection and setting
28
RCIN
Fault clear time setting output
29
TH
Thermistor output
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4
STK551U3A2A-E
Equivalent Block Diagram
VB3(1)
W,VS3(2)
VB2(5)
V,VS2(6)
VB1(9)
U,VS1(10)
+(13)
DB
DB DB
U.V.
U.V.
U.V.
Shunt - Resistor
-(16)
RCIN(28)
Latch time
TH(29)
Level
Shifter
Level
Shifter
Level
Shifter
HIN1(17)
HIN2(18)
HIN3(19)
Logic
LIN1(20)
LIN2(21)
LIN3(22)
FAULT(23)
ISO(24)
VDD(25)
Thermistor
Latch
Over- Current
VSS(26)
VDD- UnderVoltage
ISD(27)
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5
Logic
Logic
STK551U3A2A-E
Test Circuit
(The tested phase : U+ shows the upper side of the U phase and U- shows the lower side of the U phase.)
■ ICE / IR(BD)
ICE
U+
V+
W+
U-
V-
W-
M
13
13
13
10
6
2
N
10
6
2
16
16
16
9
M
A
VD1=15V
10
5
VD2=15V
6
VCE
1
U(BD)
V(BD)
W(BD)
M
9
5
1
N
26
26
26
VD3=15V
2
25
VD4=15V
26
N
Fig. 1
9
5V
VD1=15V
■ VCE(SAT) (Test by pulse)
M
10
5
U+
V+
W+
U-
V-
W-
M
13
13
13
10
6
2
6
N
10
6
2
16
16
16
1
m
17
18
19
20
21
22
VD2=15V
V
VD3=15V
Io
VCE(SAT)
2
25
VD4=15V
m
26
27
N
Fig. 2
■ VF (Test by pulse)
U+
V+
W+
U-
V-
W-
M
13
13
13
10
6
2
N
10
6
2
16
16
16
M
V
N
Fig. 3
■ ID
VD1
VD2
VD3
VD4
M
9
5
1
25
N
10
6
2
26
ID
A
M
VD*
N
Fig. 4
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6
VF
Io
STK551U3A2A-E
■ ISD
9
Input signal
10
VD1=15V
10
(0 to 5 V)
5
VD2=15V
6
Io
1
VD3=15V
2
25
VD4=15V
Io
ISD
Input signal
20
26
27
16
100 μs
Fig. 5
■ Switching time (The circuit is a representative example of the lower side U phase.)
9
13
VD1=15V
10
Input signal
(0 to 5 V)
5
VD2=15V
6
10
1
Vcc
CS
VD3=15V
2
25
90%
Io
VD4=15V
10%
tON
Input signal
Io
20
26
27
16
tOFF
Fig. 6
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7
STK551U3A2A-E
Logic Timing Chart
VBS undervoltage protection reset signal
ON
HIN1,2,3
OFF
LIN1,2,3
*2
VDD
VDD undervoltage protection reset voltage
*3
VBS undervoltage protection reset voltage
VB1,2,3
*4
-------------------------------------------------------ISD operation current level-------------------------------------------------------
-terminal
(BUS line)
Current
FAULT terminal
Voltage
(at pulled-up)
ON
*1
Upper
U, V, W
OFF
*1
Lower
U ,V, W
Automatically reset after protection
(18ms to 80ms)
Fig. 7
Notes
*1 : Diagram shows the prevention of shoot-through via control logic. More dead time to account for switching delay
needs to be added externally.
*2 : When VDD decreases all gate output signals will go low and cut off all of 6 IGBT outputs. part. When VDD rises the
operation will resume immediately.
*3 : When the upper side gate voltage at VB1, VB2 and VB3 drops only, the corresponding upper side output is turned off.
The outputs return to normal operation immediately after the upper side gat voltage rises.
*4 : In case of over current detection, all IGBT’s are turned off and the FAULT output is asserted. Normal operation
resumes in 18 to 80 ms after the over current condition is removed.
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8
STK551U3A2A-E
Logic level table
V+
Ho
HIN1,2,3
(15,16,17)
IC
Driver
LIN1,2,3
(18,19,20)
U,V,W
(8,5,2)
Lo
FLTEN
Itrip
HIN1,2,3
LIN1,2,3
U,V,W
1
0
1
0
Vbus
1
0
0
1
0
1
0
0
0
Off
1
0
1
1
Off
1
1
X
X
Off
0
X
X
X
Off
Fig. 8
Sample Application Circuit
STK551U3A2A-E
VB1: 9
+ : 13
U,VS1:10
VCC
CB
VD1
CB
VD2
CB
VD3
CS1
CS2
VB2: 5
V,VS2: 6
- : 16
VB3: 1
W,VS3: 2
RCIN:28
U,VS1:10
HIN1:17
HIN2:18
V,VS2: 6
HIN3:19
Control
LIN1:20
Circuit
LIN2:21
(5V)
LIN3:22
ISO:24
FAULT:23
TH:29
W,VS3: 2
VDD:25
Vss:26
RP
CD4
RP
VD=15V
ISD:27
RSD
Fig. 9
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9
STK551U3A2A-E
Recommended Operating Conditions at Tc = 25C
Item
Symbol
Ratings
Conditions
+ to U-(V-,W-)
min
typ
max
0
280
450
12.5
15
17.5
13.5
15
16.5
Unit
Supply voltage
VCC
Pre-driver
supply voltage
VD1,2,3
VB1 to U, VB2 to V, VB3 to W
VD4
VDD to VSS
ON-state input voltage
VIN(ON)
3.0
-
5.0
OFF-state input voltage
VIN(OFF)
HIN1, HIN2, HIN3,
LIN1, LIN2, LIN3
0
-
0.3
1
-
20
kHz
2
-
-
s
1
-
-
s
0.6
-
0.9
Nm
*1
PWM frequency
fPWM
Dead time
DT
Turn-off to turn-on
Allowable input pulse width
PWIN
ON and OFF
Tightening torque
‘M3’ type screw
V
V
V
*1 : Pre-drive power supply (VD4 = 15 ±1.5 V) must be have the capacity of Io = 20 mA (DC), 0.5 A (Peak).
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
Usage Precautions
1.
This IPM includes bootstrap diode and resistors. Therefore, by adding a capacitor “CB”, a high side drive voltage is generated; each
phase requires an individual bootstrap capacitor. The recommended value of CB is in the range of 1 to 47 μF, however this value
needs to be verified prior to production. If selecting the capacitance more than 47μF (±20%), connect a resistor (about 20 Ω) in
series between each 3-phase upper side power supply terminals (VB1, 2, 3) and each bootstrap capacitor. When not using the
bootstrap circuit, each upper side pre-drive power supply requires an external independent power supply.
2.
It is essential that wirning length between terminals in the snubber circuit be kept as short as possible to reduce the effect of surge
voltages. Recommended value of “CS” is in the range of 0.1 to 10 μF.
3.
“ISO” (pin 24) is terminal for current monitor. When the pull-down resistor is used, please select it more than 5.6 kΩ
4.
“FAULT” (pin 23) is open DRAIN output terminal (Active Low). Pull up resistor is recommended more than 5.6 kΩ.
5.
Inside the IPM, a thermistor used as the temperature monitor for internal subatrate is connected between VSS terminal and TH
terminal, therefore, an external pull up resistor connected between the TH terminal and an external power supply should be used.
The temperature monitor example application is as follows, please refer the Fig.10, and Fig.11 below.
6.
Pull down resistor of 33 kΩ is provided internally at the signal input terminals. An external resistor of 2.2 k to 3.3 kΩ should be added
to reduce the influence of external wiring noise.
7.
The over-current protection feature is not intended to protect in exceptional fault condition. An external fuse is recommended for
safety.
8.
When “-” and “VSS” terminal are short-circuited on the outside, level that over-current protection (ISD) might be changed from
designed value as IPM. Please check it in your set (“N” terminal and “VSS” terminal are connected in IPM).
9.
The over-current protection function operates normally when an external resistor RSD is connected between ISD and VSS
terminals. Be sure to connect this resistor. The level of the overcurrent protection can be changed according to the RSD value.
10.
When input pulse width is less than 1.0 μs, an output may not react to the pulse. (Both ON signal and OFF signal)
This data shows the example of the application circuit, does not guarantee a design as the mass production set.
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10
STK551U3A2A-E
The characteristic of thermistor
Parameter
Symbol
Condition
Min
Typ.
Max
Unit
Resistance
R25
Tc = 25C
97
100
103
kΩ
Resistance
R100
Tc = 100C
4.93
5.38
5.88
kΩ
4165
4250
4335
k
40
-
+125
C
B-Constant (25 to 50C)
B
Temperature Range
Fig. 10
Case Temperature(Tc) - TH to Vss voltage characteristic
min
TH - Vss terminal voltage, VTH-V
typ
max
Condition
Pull-up resistor = 39 kΩ
Pull-up voltage of TH = 5 V
Case temperature, Tc-degC
Fig. 11
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11
STK551U3A2A-E
The characteristic of PWM switching frequency
Maximum sinusoidal phase current as function of switching frequency (VBUS = 400 V, Tc = 100C)
Fig.12
Switching waveform
IGBT Turn-on. Typical turn-on waveform @Tc = 100C, VBUS = 400 V
X (200 ns/div)
VCE (100 V/div)
Turn on
Io (5 A/div)
Fig. 13
IGBT Turn-off. Typical turn-off waveform @Tc = 100C, VBUS = 400 V
X (200 ns/div)
Io (5 A/div)
Turn off
VCE (100 V/div)
Fig. 14
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12
STK551U3A2A-E
CB capacitor value calculation for bootstrap circuit
Calculate condition
Item
Upper side power supply
Total gate charge of output power IGBT at 15 V
Symbol
Value
Unit
VBS
15
V
Qg
153
nC
Upper side power supply low voltage protection
UVLO
12
V
Upper side power dissipation
IDmax
400
μA
Ton-max
-
s
ON time required for CB voltage to fall from 15 V to UVLO
Capacitance calculation formula
CB must not be discharged below to the upper limit of the UVLO - the maximum allowable on-time (Ton-max) of the
upper side is calculated as follows:
VBS CB – Qg – IDmax Ton-max = UVLO CB
CB = (Qg + IDmax * Ton-max) / (VBS – UVLO)
The relationship between Ton-max and CB becomes as follows. CB is recommended to be approximately 3 times
the value calculated above. The recommended value of CB is in the range of 1 to 47 μF, however, the value needs
to be verified prior to production.
Tonmax-Cb characteristic
Fig. 15
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13
STK551U3A2A-E
Package Dimensions
unit : mm
SIP29 56x21.8
CASE 127BW
ISSUE O
missing pin : 3, 4, 7, 8, 11, 12, 14, 15
13.9
(10.9)
1
5.0
R1.7
3.2
0.5
0.6
1.27
0.5
29
1.27 28 = 35.56
2.0
5.7
46.2
50.0
62.0
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14
6.7
21.8
3.4
56.0
STK551U3A2A-E
ORDERING INFORMATION
Device
STK551U3A2A-E
Package
Shipping (Qty / Packing)
SIP29 56x21.8
(Pb-Free)
8 / Tube
ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries
in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other
intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON
Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or
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