STK5F1U3E2D-E
Advance Information
Intelligent Power Module (IPM)
600 V, 50 A
Overview
This “Inverter Power IPM” is highly integrated device containing all High
Voltage (HV) control from HV-DC to 3-phase outputs in a single DIP module
(Dual-In line Package). Output stage uses IGBT / FRD technology and
implements Under Voltage Protection (UVP) and Over Current Protection
(OCP) with a Fault Detection output flag. Internal Boost diodes are provided
for high side gate boost drive.
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Function
Single control power supply due to Internal bootstrap circuit for high side
pre-driver circuit
All control input and status output are at low voltage levels directly
compatible with microcontrollers
Cross conduction prevention
Externally accessible embedded thermistor for substrate temperature
measurement
The level of the over-current protection current is adjustable with the
external resistor, “RSD”
Certification
UL1557 (File Number : E339285)
Specifications
Absolute Maximum Ratings at Tc = 25C
Parameter
Supply voltage
Collector-emitter voltage
Output current
Output peak current
Pre-driver supply voltage
Input signal voltage
Symbol
VCC
VCE
Io
Iop
VD1, 2, 3, 4
VIN
FAULT terminal voltage
VFAULT
Maximum loss
Junction temperature
Storage temperature
Operating temperature
Tightening torque
Withstand voltage
Pd
Tj
Tstg
Tc
MT
Vis
Remarks
P to N, surge < 500 V *1
P to U, V, W or U, V, W to N
P, N, U, V, W terminal current
HIN1, 2, 3, LIN1, 2, 3
Ratings
450
600
±50
±25
±76
20
0.3 to VDD
FAULT terminal
0.3 to VDD
V
67.5
150
W
P, N, U, V, W terminal current, Tc = 100C
P, N, U, V, W terminal current, PW = 1 ms
VB1 to VS1, VB2 to VS2, VB3 to VS3, VDD to VSS *2
IGBT per channel
IGBT,FRD
IPM case
A screw part at use M4 type screw *3
50 Hz sine wave AC 1 minute *4
40 to +125
20 to +100
1.17
2000
Unit
V
V
A
A
V
V
C
C
C
Nm
VRMS
Reference voltage is N terminal = VSS terminal voltage unless otherwise specified.
*1 : Surge voltage developed by the switching operation due to the wiring inductance between the P and N terminals.
*2 : Terminal voltage : VD1 = VB1 to VS1, VD2 = VB2 to VS2, VD3 = VB3 to VS3, VD4 = VDD to VSS.
*3 : Flatness of the heat-sink should be 0.25 mm and below.
*4 : Test conditions : AC 2500 V, 1 s.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
ORDERING INFORMATION
See detailed ordering and shipping information on page 14 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
October 2016 - Rev. P2
1
Publication Order Number :
STK5F1U3E2D-E/D
STK5F1U3E2D-E
Electrical Characteristics at Tc 25C, VD1, VD2, VD3, VD4 = 15 V
Parameter
Power output section
Collector to emitter cut-off current
Bootstrap diode reverse current
Collector to emitter saturation
voltage
Symbol
Conditions
ICE
VCE = 600 V
IR(BD)
VR(BD) = 600 V
VCE(sat)
IF = 50 A
Diode forward voltage
Max.
-
1.7
2.3
100
100
2.6
3.2
-
1.35
-
Lower side
-
1.75
-
Upper side
-
1.8
2.7
-
2.4
3.3
-
1.45
-
Fig.1
Lower side
VF
Upper side
IF = 25 A,
Tj = 100C
Junction to case thermal resistance
Typ.
Upper side
Ic = 25 A,
Tj = 100C
Ratings
Min.
Upper side
Lower side
Ic = 50 A
Test
circuit
Fig.2
Fig.3
Lower side
Unit
μA
μA
V
V
-
1.85
θj-c(T)
IGBT
-
-
1.5
-
C/W
θj-c(D)
FWD
-
-
1.8
-
C/W
-
0.05
0.4
-
1.0
4.0
2.5
-
100
0.8
195
1
V
V
μA
μA
57
-
76
A
10.6
11.1
11.6
V
10.4
10.9
11.4
V
Control (Pre-driver) section
Pre-drive power supply consumption
current
ID
VD1, 2, 3 = 15 V
VD4 = 15 V
Fig.4
High level input voltage
Low level input voltage
Logic 1 input leakage current
Logic 0 input leakage current
Protection section
Over-current protection electric
current
VDD and VBx supply undervoltage
positive going input threshold
VDD and VBx supply undervoltage
negative going input threshold
VDD and VBx supply undervoltage
Ilockout hysteresis
FAULT terminal input electric current
Vin H
Vin L
IIN+
IIN-
VIN = +3.3 V
VIN = 0 V
ISD
PW = 100 μs, RSD = 0 Ω
VddUV+
VBxUV+
VddUVVBxUVVddUVH
VBxUVH
IOSD
VFAULT = 0.1 V
-
1
1.5
-
mA
FAULT clearance delay time
FLTCLR
From time fault condition clear
-
18
-
80
ms
Thermistor for substrate temperature
monitor
Rt
Resistance between the TH(18)
and VSS(20) terminals
-
90
-
110
kΩ
-
0.7
1.5
μs
HIN1, HIN2, HIN3,
LIN1, LIN2, LIN3 to VSS
-
mA
Fig.5
0.2
V
Switching character
Switching time
tON
tOFF
Io = 50 A, Inductive load
Turn-on switching loss
Turn-off switching loss
Total switching loss
Turn-on switching loss
Turn-off switching loss
Total switching loss
Diode reverse recovery energy
Eon
Eoff
Etot
Eon
Eoff
Etot
Erec
Diode reverse recovery time
Trr
Reverse bias safe operating area
RBSOA
Io = 25 A, VCC = 300 V,
VD = 15 V, L = 280 μH,
Tc = 100C
Io = 25 A, VCC = 300 V,
VD = 15 V, L = 280 μH,
Tc = 100C
Io = 76 A, VCE = 450 V
Short circuit safe operating area
SCSOA
VCE = 400 V, Tc = 100C
Electric current output signal level
ISO
Io = 50 A
Io = 50 A, VCC = 300 V,
VD = 15 V, L = 280 μH
Fig.6
-
1.1
2.1
μs
-
1100
1220
2320
620
790
1410
27
-
μJ
μJ
μJ
μJ
μJ
μJ
μJ
-
80
-
ns
Full square
4
-
0.427
μs
0.45
0.474
V
Reference voltage is N terminal = VSS terminal voltage unless otherwise specified.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
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2
STK5F1U3E2D-E
Notes
1. When the internal protection circuit operates, a Fault signal is turned ON (When the Fault terminal is low level, Fault
signal is ON state : output form is open DRAIN) but the Fault signal does not latch. After protection operation ends,
it returns automatically within about 18 ms to 80 ms and resumes operation beginning condition. So, after Fault
signal detection, set all input signals to OFF (Low) at once.However, the operation of pre-drive power supply low
voltage protection (UVLO : with hysteresis about 0.2 V) is as follows.
Upper side :
The gate is turned off and will return to regular operation when recovering to the normal voltage, but the latch will
continue till the input signal will turn ‘low’.
Lower side :
The gate is turned off and will automatically reset when recovering to normal voltage. It does not depend on input
signal voltage.
2. When assembling the IPM on the heat sink with M4 type screw, tightening torque range is 0.79 Nm to 1.17 Nm.
3. The pre-drive low voltage protection is the feature to protect devices when the pre-driver supply voltage falls due to an
operating malfunction.
Pin Assignment
Pin No.
1
Name
Description
Pin No.
Name
Description
VB1
High side floating supply voltage 1
44
P
Positive bus input voltage
2
VS1
High side floating supply offset voltage
43
P
Positive bus input voltage
3
-
Without pin
42
P
Positive bus input voltage
4
VB2
High side floating supply voltage 2
41
-
Without pin
5
VS2
High side floating supply offset voltage
40
N
Negative bus input voltage
6
-
Without pin
39
N
Negative bus input voltage
7
VB3
High side floating supply voltage 3
38
N
Negative bus input voltage
8
VS3
High side floating supply offset voltage
37
-
Without pin
9
-
Without pin
36
U
U-phase output
10
HIN1
Logic input high side driver-Phase1
35
U
U-phase output
11
HIN2
Logic input high side driver-Phase2
34
U
U-phase output
12
HIN3
Logic input high side driver-Phase3
33
-
Without pin
13
LIN1
Logic input low side driver-Phase1
32
V
V-phase output
14
LIN2
Logic input low side driver-Phase2
31
V
V-phase output
15
LIN3
Logic input low side driver-Phase3
30
V
V-phase output
16
FAULT
Fault out (open drain)
29
-
Without pin
17
ISO
Current monitor pin
28
W
W-phase output
18
TH
Thermistor out
27
W
W-phase output
19
VDD
+15 V main supply
26
W
W-phase output
20
VSS
Negative main supply
25
-
Without pin
21
ISD
Over-current protection level setting pin
24
NC
-
22
NC
-
23
NC
-
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3
STK5F1U3E2D-E
Block Diagram
NC(23,24)
U(34,35,36)
V(30,31,32)
W(26,27,28)
VB1(1)
VS1(2)
VB2(4)
VS2(5)
VB3(7)
VS3(8)
P
(42,43,44)
DB
DB DB
U.V.
U.V.
U.V.
RB
N
(38,39,40)
Shunt-Resistor
ISO(17)
Thermistor
TH(18)
Level
Shifter
Level
Shifter
Level
Shifter
HIN1(10)
HIN2(11)
HIN3(12)
Logic
Logic
Logic
LIN1(13)
LIN2(14)
LIN3(15)
Shutdown
VDD(19)
S
+
Under voltage
Q
-
Detect
Timer
VSS(20)
R
Vref
Latch time about 18 to 80ms
ISD(21)
FAULT(16)
NC(22)
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4
STK5F1U3E2D-E
Test Circuit
(The tested phase : U+ shows the upper side of the U phase and U shows the lower side of the U phase)
ICE / IR(BD)
M
N
U+
42
34
V+
42
30
W+
42
26
M
N
U(BD)
1
20
V(BD)
4
20
W(BD)
7
20
U34
38
V30
38
W26
38
ICE
1
M
A
VD1=15V
2
4
VD2=15V
5
VCE
7
VD3=15V
8
19
VD4=15V
20
N
Fig.1
VCE(sat) (Test by pulse)
M
N
m
U+
42
34
10
V+
42
30
11
W+
42
26
12
U34
17
13
V30
19
14
W26
21
15
1
M
VD1=15V
2
4
VD2=15V
5
V
Ic
7
VD3=15V
VCE(SAT)
8
19
VD4=15V
5V
m
20
21
Fig.2
VF (Test by pulse)
M
N
U+
42
34
V+
42
30
N
W+
42
26
U34
38
V30
38
W26
38
M
V
N
Fig.3
ID
M
N
VD1
1
2
VD2
4
5
VD3
7
8
VD4
19
20
ID
A
M
VD*
N
Fig.4
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5
VF
IF
STK5F1U3E2D-E
ISD
VD1=15V
Input signal
(0 to 5 V)
VD2=15V
1
34
2
4
5
ISD
Io
Io
7
VD3=15V
8
19
VD4=15V
100 μs
Input signal
13
20
38
21
Fig.5
Switching time (The circuit is a representative example of the lower side U phase)
1
Input signal
(0 to 5 V)
VD1=15V
42
2
4
VD2=15V
90%
34
Vcc
7
Io
VD3=15V
CS
8
19
10%
tON
5
VD4=15V
tOFF
Input signal
Io
13
20
38
21
Fig.6
RB-SOA (The circuit is a representative example of the lower side U phase)
Input signal
(0 to 5 V)
42
1
VD1=15V
2
4
VD2=15V
Io
5
34
Vcc
7
VD3=15V
CS
8
19
Io
VD4=15V
Input signal
13
20
38
21
Fig.7
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6
STK5F1U3E2D-E
Logic Timing Chart
VBS undervoltage protection reset signal
ON
HIN1,2,3
OFF
LIN1,2,3
*2
VDD
VDD undervoltage protection reset voltage
*3
VBS undervoltage protection reset voltage
VB1,2,3
*4
-------------------------------------------------------ISD operation current level-------------------------------------------------------
ITRIP-terminal
(BUS line)
Current
FAULT terminal
Voltage
(at pulled-up)
ON
*1
Upper
U, V, W
OFF
*1
Lower
U ,V, W
Automatically reset after protection
(18ms to 80ms)
Fig. 8
Notes
*1 : Diagram shows the prevention of shoot-through via control logic. More dead time to account for switching delay
needs to be added externally.
*2 : When VDD decreases all gate output signals will go low and cut off all of 6 IGBT outputs. part. When VDD rises the
operation will resume immediately.
*3 : When the upper side gate voltage at VB1, VB2 and VB3 drops only, the corresponding upper side output is turned off.
The outputs return to normal operation immediately after the upper side gat voltage rises.
*4 : In case of over current detection, all IGBT’s are turned off and the FAULT output is asserted. Normal operation
resumes in 18 to 80 ms after the over current condition is removed.
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7
STK5F1U3E2D-E
Logic level table
P(42,43,44)
FAULT*
HIN1,2,3
LIN1,2,3
U,V,W
1
1
0
Vbus
1
0
1
0
1
0
0
Off
1
1
1
Off
0
X
X
Off
Ho
HIN1,2,3
(10,11,12)
IC
Driver
LIN1,2,3
(13,14,15)
U,V,W
(34,35,36)
(30,31,32)
(26,27,28)
Lo
* With pulled-up registor
N(38,38,40)
Fig.9
Application Circuit Example
CB
+
P 44
43
42
1 VB1
2 VS1
CB
+
4 VB2
5 VS2
N
CB
+5.0V
+
RFault
7 VB3
8 VS3
U 36
35
34
RTH
10 HIN1
11 HIN2
Control
Circuit
V 32
31
30
12 HIN3
13 LIN1
W 28
27
26
14 LIN2
15 LIN3
16 FAULT
17 ISO
18 TH
VDD=15V
NC
24
23
Rpd
CD
Missing pin
3, 6, 9, 25, 29, 33, 37, 41
40
39
38
RSD
19 VDD
20 VSS1
21 ISD
22 NC
Fig.10
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8
Vcc
+
CS
+
CI
-
STK5F1U3E2D-E
Recommended Operating Conditions at Tc = 25C
Parameter
Supply voltage
Symbol
VCC
Conditions
P to N
Ratings
Min
Typ
Max
0
280
450
Unit
V
VD1, 2, 3
VB1 to VS1, VB2 to VS2, VB3 to VS3
12.5
15
17.5
VD4
VDD to VSS *1
13.5
15
16.5
Input ON voltage
VIN(ON)
VDD
VIN(OFF)
HIN1, HIN2, HIN3,
LIN1, LIN2, LIN3
3.0
Input OFF voltage
0
0.8
PWM frequency
fPWM
1
20
kHz
Dead time
DT
2
μs
1
μs
0.79
1.17
Nm
Pre-driver supply voltage
Turn-off to turn-on (external)
Allowable input pulse width
PWIN
ON pulse width/OFF pulse width
Tightening torque
MT
‘M4’ type screw
V
V
*1 Pre-driver power supply (VD4 = 15 ±1.5 V) must have the capacity of Io = 20 mA (DC), 0.5 A (Peak).
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
Usage Precautions
1. This IPM includes bootstrap diode and resistors. Therefore, by adding a capacitor “CB”, a high side drive voltage is
generated ; each phase requires an individual bootstrap capacitor. The recommended value of CB is in the range of
1 to 47 μF, however this value needs to be verified prior to production. If selecting the capacitance more than 47 μF
(±20%), connect a resistor (about 20 Ω) in series between each 3-phase upper side power supply terminals (VB1, 2,
3) and each bootstrap capacitor.
When not using the bootstrap circuit, each upper side pre-drive power supply requires an external independent
power supply.
2. It is essential that wirning length between terminals in the snubber circuit be kept as short as possible to reduce the
effect of surge voltages. Recommended value of “CS” is in the range of 0.1 to 10 μF.
3. “ISO” (pin 17) is terminal for current monitor. When the pull-down resistor is used, please select it more than 5.6 kΩ.
4. “FAULT” (pin 16) is open DRAIN output terminal. (Active Low). Pull up resistor is recommended more than 5.6 kΩ.
5.
Inside the IPM, a thermistor used as the temperature monitor for internal subatrate is connected between VSS
terminal and TH terminal, therefore, an external pull up resistor connected between the TH terminal and an external
power supply should be used. The temperature monitor example application is as follows, please refer the Fig.11,
and Fig.12 below.
6. The pull down resistor of 33 kΩ is provided internally at the signal input terminals. An external resistor of 2.2 kΩ to
3.3 kΩ should be added to reduce the influence of external wiring noise.
7. The over-current protection feature is not intended to protect in exceptional fault condition. An external fuse is
recommended for safety.
8. When “N” and “VSS” terminal are short-circuited on the outside, level that over-current protection (ISD) might be
changed from designed value as IPM. Please check it in your set (“N” terminal and “VSS” terminal are connected in
IPM).
9. The over-current protection function operates normally when an external resistor RSD is connected between ISD
and VSS terminals. Be sure to connect this resistor. The level of the overcurrent protection can be changed
according to the RSD value.
10. When input pulse width is less than 1.0 μs, an output may not react to the pulse. (Both ON signal and OFF signal)
This data shows the example of the application circuit, does not guarantee a design as the mass production set.
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STK5F1U3E2D-E
The characteristic of thermistor
Parameter
Resistance
Resistance
B-Constant (25 to 50C)
Temperature Range
Symbol
R25
R100
B
Condition
Tc = 25C
Tc = 100C
Min
97
4.93
4165
40
Typ.
100
5.38
4250
Max
103
5.88
4335
+125
Unit
kΩ
kΩ
K
C
Fig.11 Variation of thermistor resistance with temperature
Condition
Pull-up resistor = 39 k +/-1%
Pull-up voltage of TH = 5 V +/-0.3 V
Fig.12 Variation of temperature sense voltage with thermistor temperature
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STK5F1U3E2D-E
Maximum Phase current
Motor Current vs. Frequency
(Sine wave oparation,Vcc=300V,cosθ=0.8,ON Duty=96%)
Phase Current : Io (A rms)
50
40
30
20
10
0
0
5
10
Switching Frequency : fc (KHz)
15
20
Fig.13 Maximum sinusoidal phase current as function of switching frequency
at Tc = 100C, VCC = 300 V
Switching waveform
Turn on
Fig. 14 IGBT Turn-on. Typical turn-on waveform at Tc = 100C, VCC = 300 V, Ic = 25 A
Turn off
Fig. 15 IGBT Turn-off. Typical turn-off waveform Tc = 100C, VCC = 300 V, Ic = 25 A
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STK5F1U3E2D-E
CB capacitor value calculation for bootstrap circuit
Calculate condition
Item
Upper side power supply
Total gate charge of output power IGBT at 15 V
Upper side power supply low voltage protection
Upper side power dissipation
ON time required for CB voltage to fall from 15 V to UVLO
Symbol
VBS
Qg
UVLO
IDmax
Ton-max
Value
15
0.47
12
400
Unit
V
μC
V
μA
s
Capacitance calculation formula
CB must not be discharged below to the upper limit of the UVLO - the maximum allowable on-time (Ton-max) of the
upper side is calculated as follows :
VBS * CB – Qg – IDmax * Ton-max = UVLO * CB
CB = (Qg + IDmax * Ton-max) / (VD – UVLO)
Bootstrap Capacitance Cb (uF)
The relationship between Ton-max and CB becomes as follows. CB is recommended to be approximately 3 times the
value calculated above. The recommended value of CB is in the range of 1 to 47 μF, however, the value needs to be
verified prior to production.
Cb vs ton max
100
10
1
0.1
0.01
0.1
1
10
100
ton max (ms)
Fig.16 Ton-max vs CB characteristic
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12
1000
STK5F1U3E2D-E
PACKAGE DIMENSIONS
unit : mm
TENTATIVE
Missing Pin : 3, 6, 9, 25, 29, 33, 37, 41
4.6
23
note 2
note 1
+0.2
-0.05
0.75
76.0
21×2.54=53.34
note 3
(68.0)
63.4
.3
STK5F1U3E2D
22
2.54
R2
6.0
44
1
3.2
8.0
45.0
0.5
5°
0 to
10.8
+0.2
-0.05
note1 : Mark of mirror surface for No.1 pin
identification.
note2 : The form of a character in this
drawing differs from that of IPM.
note3 : This indicates the Lot code.
49.7
The form of a character in this
drawing differs from that of IPM.
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STK5F1U3E2D-E
ORDERING INFORMATION
Device
STK5F1U3E2D-E
Package
Shipping (Qty / Packing)
TBD
(Pb-Free)
6 / Tube
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Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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