RS2042

Page No. : 1/1 RS2042 Green-Power PWM Controller with Freq. Jittering Description The RS2042 is a low startup current, low cost, current mode PWM controller with Green-Power & burst-mode power-saving operation. The integrated functions such as the leading-edge blanking of the current sensing, internal slope compensation provide the users a high efficiency, low external component counts, and low cost solution for AC/DC power applications. The special Green-Power function provides off-time modulation to linearly decrease the switching frequency under light-load conditions. And under zero-load conditions, the power supply enters burst-mode to further reduce power consumption by shutting off PWM output. When the output of power supply is short or over loaded, the FB voltage will increase, and if the FB voltage is higher than 5.2V for longer than 56msec the PWM output will be turned off. A external NTC resistor connected from pin RT to ground can be applied to over-temperature protection. Pulse by pulse current limit ensures a constant output current even under short circuit. PWM output will be disabled as long as VDD exceeds a threshold. When internal latch circuit is used to latch-off the controller, the latch will be reset when the power supply VDD is disabled. Features Low Cost, Green-Power Burst-Mode PWM Very Low Start-up Current (about 7.5μA) Low Operating Current (about 3.0mA) Current Mode Operation Under Voltage Lockout (UVLO) VDD Over Voltage Protection (OVP) Programmable over-temperature protection Internal Latch Circuit (OTP, OVP) Built-in soft start with 1ms Built-in Frequency jitter for better EMI Signature Soft Clamped gate output voltage 16.5V VDD over voltage protect 25.5V Cycle-by-cycle current limiting Sense Fault Protection Output SCP (Short circuit Protection) Built-in Synchronized Slope Compensation Leading-edge blanking on Sense input Programmable PWM Frequency High-Voltage CMOS Process with ESD DIP-8 & SOP-8 Pb-Free Package Compatible with SG6842J&LD7552&OB2269 & SG6841 & OB2268 Applications Power Adaptor Battery Charger Adapter Open Frame Switching Power Supply LCD Monitor Pin Configurations Name GND FB Description GND Pin Voltage feedback pin. The PWM duty cycle is determined by FB and Sense. This pin is pulled high to the rectified line input through a large resistor for start-up. This pin is also used to detect line voltage to compensate for constant output power limit for universal AC input. By connecting a resistor to ground to set the switching freq.. Increasing the resistor will reduce the switching freq.. An NTC resistor is connected from this pin to ground for over-temperature protection. Current sense pin, The sensed voltage is used for current-mode control and pulseby-pulse current limiting. Power supply voltage pin. Gate drive output to drive the external MOSFET.A soft driving waveform is implemented to improve EMI. 1 2 3 4 GND FB VIN RI GATE VDD SENSE RT 8 7 6 5 VIN RI RT SENSE VDD GATE DS-RS2042-01 May, 2007 www.Orister.com Page No. : 2/2 Typical Application Circuit From bridge rectifier From auxiliary winding 1 2 3 4 GND FB VIN RI GATE VDD SENSE RT 8 7 6 Rs 5 NTC Block Diagram RI VIN 0.9V Current Reference VDD Soft Driver GATE RT OTP PWM LATCH Internal BIAS OSC S R Blanking Circuit SENSE Slope Compensation VDD UVLO OVP Burst Mode Controller Green Mode Controller 56ms Debounce FB 5.2V GND DS-RS2042-01 May, 2007 www.Orister.com Page No. : 3/3 Absolute Maximum Ratings Symbol VDD VFB VSense PD Parameter Supply voltage Pin Voltage Input Voltage to FB Pin Input Voltage to SENSE Pin Power Dissipation ESD Capability, HBM Model ESD Capability, Machine Model DIP-8（10sec） Lead Temperature (Soldering) SOP-8（10sec） Storage Temperature Range Range 40 -0.3 to 6V -0.3 to 6V 1000 2000 200 260 230 -55 to + 150 Units V V V mW V V o o TL TSTG C C Electrical Characteristics (Ta=27°C unless otherwise noted, VDD = 15V.) Symbol Parameter Test Conditions RS2042 Min Typ 7.5 3.0 16.5 10.8 24.5 12.0 Max 30 5 17.0 11.2 25.0 13.0 1.42 6.00 0.76 115 13 354 0.76 67 27 2.05 1.54 5.0 0.32 8.00 240 80 86 70 1.05 26 216 6 0.9 200 460 0.9 70 29 2.15 1.60 Unit Supply Voltage (VDD Pin) IST Startup Current VDD=17 ISS Operating Current VFB= VSENSE = 0V VDD=15 VTH (ON) Start Threshold Voltage -VTH (OFF) Min. Operating Voltage -VDD-OVP VDD Over Voltage Protection (Latch off) VDD Low-Threshold Voltage to Exit Green-OFF VDD-th-g Mode Voltage Feedback (FB Pin) IFB Short Circuit Current VFB=0V VFB Open Loop Voltage VFB=Open Current Sensing (SEN Pin) VTH Threshold voltage for current limit IVIN =0 TPD Delay to Output ZCS Input Impedance Bnk Leading Edge Blanking Time VTH Threshold voltage for current limit IVIN =0 FOSC FOSC-green VN VG Oscillator (RI Pin) Frequency in nominal mode RI=26KΩ Frequency in green mode RI=26 KΩ Beginning of frequency reducing at FB Voltage VDD=15V End of frequency reducing at FB voltage VDD=15V o Frequency Temp. Stability -30-85 C GATE Drive Output (GATE Pin) Output Low Level VDD=12V, IO=50mA Output High Level VDD=12V, IO=50mA Rising Time VDD=15V,CL=1nF Falling Time VDD=13V,CL=1nF Maximum Duty Cycle Over-Temperature Protection Section Output current of pin RT RI=26KΩ Threshold voltage for over-temperature protection. RI Section RI Operating Range Max RI value for Protection 16.0 10.4 23.0 11.0 μA mA V V V V mA V V nsec KΩ nsec V KHz KHz V VG % V V ns ns 260 63 25 1.95 1.50 VOL VOH TR TF DCMAX IRT VOTP RINOR RIMAX RIMIN 0.60 280 90 88 75 1.10 36 7.2 200 30 84 65 1.00 15.5 μA V KΩ KΩ KΩ DS-RS2042-01 May, 2007 www.Orister.com Page No. : 4/4 OPERATION DESCRIPTION Start-Up Current & Operating Current The typical start-up current is only 8μA. This allows a high resistance, low-wattage start-up resistor to be used, to minimize power loss. A 1.5MOhms, 0.25W, start-up resistor and a 10μF/40V VDD hold-up capacitor would be sufficient for an AC/DC adapter with a universal input range. The required operating current has been reduced to 3.4mA. This results in higher efficiency and reduces the VDD hold-up capacitance requirement. Green-Power Mode Operation The proprietary green-power mode function provides off-time modulation to continuously decrease the PWM frequency under light-load conditions. To avoid acoustic-noise problem, the minimum PWM frequency set above 25KHz. This green-power mode function dramatically reduces power consumption under light-load and zero-load conditions. Power supplies using a RS2042 controller can easily meet even the most restrictive international regulations regarding standby power consumption. Oscillator Operation A resistor connected from the RI pin to GND pin generates a constant current source for the RS2042 controller. This current is used to determine the center PWM frequency. Increasing the resistance will reduce PWM frequency. Using a 26KΩ resistor RI results in a corresponding 67KHz PWM frequency. The relationship between RI and the switching frequency is: f PWM = 1742 ( KHz ) R I ( KΩ ) RS2042 also integrates frequency jittering function internally. The frequency variation ranges from around 63KHz to 70KHz for a center frequency 67kHz. The frequency jittering function helps reduce EMI emission of a power supply with minimum line filters. I RT = Leading Edge Blanking 70μA * 26 R I ( KΩ ) Each time the power MOSFET is switched on, a turn-on spike will inevitably occur at the sense-resistor. To avoid premature termination of the switching pulse, a leading-edge blanking time is built in. During this blanking period, the current-limit comparator is disabled, and it cannot switch off the gate drive. Under-Voltage Lockout (UVLO) The turn-on/turn-off thresholds are fixed internally at 12.4V/16.5V. To enable a RS2042 controller during start-up, the hold-up capacitor must first be charged to 16.5V through the start-up resistor. The hold-up capacitor will continue to supply VDD before energy can be delivered from the auxiliary winding of the main transformer. VDD must not drop below 12.4V during this start-up process. This UVLO hysteresis window ensures that the hold-up capacitor can adequately supply VDD during start-up. Gate Output / Soft Driving The RS2042 output stage is a fast totem pole gate driver. Cross-conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 18V Zener diode in order to protect the power MOSFET transistors from any harmful over-voltage gate signals. A soft driving waveform is implemented to minimize EMI. DS-RS2042-01 May, 2007 www.Orister.com Page No. : 5/5 Slope Compensation The sensed voltage across the current sense resistor is used for peak-current-mode control and cycle-by-cycle current limiting. The built-in slope compensation function improves power supply stability and prevents peakcurrent-mode control from causing sub-harmonic oscillations. Within every switching cycle, the RS2042 controller produces a positively sloped, synchronized ramp signal. Constant Output Power Limit When the SENSE voltage across the sense resistor RS reaches the threshold voltage, the output GATE drive will be turned off following a small propagation delay TPD. This propagation delay will result in an additional current proportional to TPD*VIN/LP. The propagation delay is nearly constant regardless of the input line voltage VIN. Higher input line voltages will result in larger additional currents. Thus, under high input-line voltages the output power limit will be higher than under low input-line voltages. The output power limit variation can be significant over a wide range of AC input voltages. To compensate for this, the threshold voltage is adjusted by the current IIN. Since the pin VIN is connected to the rectified input line voltage through the start-up resistor, a higher line voltage will result in a higher current IIN through the pin VIN. The threshold voltage decreases if the current IIN increases. A small threshold voltage will force the output GATE drive to terminate earlier, thus reducing total PWM turn-on time, and making the output power equal to that of the low line input. This proprietary internal compensation feature ensures a constant output power limit over a wide range of AC input voltages (90VAC to 264VAC). VDD Over-voltage Protection VDD over-voltage protection has been built in to prevent damage due to over voltage conditions. When the voltage VDD exceeds the internal threshold due to abnormal conditions, PWM output will be turned off. Over-voltage conditions are usually caused by open feedback loops. Limited Power Control The FB voltage will increase every time the output of the power supply is shorted or over-loaded. If the FB voltage remains higher than a built-in threshold for longer than TLPS, PWM output will then be turned off. As PWM output is turned off, the supply voltage VDD will also begin decreasing. When VDD goes below the turn-off threshold (eg, 12.4V) the controller will be totally shut down. VDD will be charged up to the turn-on threshold voltage of 16.5V through the start-up resistor until PWM output is restarted. This protection feature will continue to be activated as long as the over-loading condition persists. This will prevent the power supply from overheating due to over loading conditions. Thermal Protection An external NTC thermistor can be connected from the RT pin to ground. A fixed current IRT is sourced from the RT pin. Because the impedance of the NTC will decrease at high temperatures, when the voltage of the RT pin drops below 1.065V, PWM output will be disabled. The RT pin output current is related to the PWM frequency programming resistor RI Noise Immunity Noise from the current sense or the control signal may cause significant pulse width jitter, particularly in continuousconduction mode. Slope compensation helps alleviate this problem. Good placement and layout practices should be followed. The designer should avoiding long PCB traces and component leads. Compensation and filter components should be located near the RS2042. Finally, increasing the power-MOS gate resistance is advised. DS-RS2042-01 May, 2007 www.Orister.com Page No. : 6/6 DIP-8L Dimension Marking: 8 7 6 5 DIM A B C D Control Code Min. 6.29 9.22 3.25 3.17 0.38 2.28 7.49 8.56 0.229 o 94 Max. 6.40 9.32 *1.52 *1.27 *0.99 3.35 3.55 0.53 2.79 7.74 *3.00 8.81 0.381 o 97 A 1 2 3 4 Date Code RS 2042 P B F E F G H I J K L M J Note: Green label is used for pb-free packing Material: • Lead solder plating: Sn60/Pb40 (Normal), Sn/3.0Ag/0.5Cu or Pure-Tin (Pb-free) • Mold Compound: Epoxy resin family, flammability solid burning class: UL94V-0 C E D G H α1 K M L I α1 8-Lead DIP-8 Plastic Package Package Code: P *: Typical, Unit: mm SOP-8L Dimension A G Marking: DIM A B C D E F G H I J K L M N O Min. 4.85 3.85 5.80 1.22 0.37 3.74 1.45 4.80 0.05 0.30 0.19 0.37 0.23 0.08 0.00 Max. 5.10 3.95 6.20 1.32 0.47 3.88 1.65 5.10 0.20 0.70 0.25 0.52 0.28 0.13 0.15 8 B 7 6 5 C 4 J H I Pin 1 Index Date Code RS 2042 S Control Code Pin1 Index 2 3 Note: Green label is used for pb-free packing Material: • Lead solder plating: Sn60/Pb40 (Normal), Sn/3.0Ag/0.5Cu or Pure-Tin (Pb-free) • Mold Compound: Epoxy resin family, flammability solid burning class: UL94V-0 D E Part A K L N O Part A M *: Typical, Unit: mm F 8-Lead SO-8 Plastic Surface Mounted Package Package Code: S Ordering Information PART NUMBER RS2042P RS2042S PIN-PACKAGE DIP-8L SOP-8L DS-RS2042-01 May, 2007 www.Orister.com Page No. : 7/7 Soldering Methods for Orister’s Products 1. Storage environment: Temperature=10oC~35oC Humidity=65%±15% 2. Reflow soldering of surface-mount devices Figure 1: Temperature profile tP TP Ramp-up TL Tsmax Temperature tL Critical Zone TL to TP Tsmin tS Preheat Ramp-down 25 t 25oC to Peak Time Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Tsmax to TL - Ramp-up Rate Time maintained above: - Temperature (TL) - Time (tL) Peak Temperature (TP) Time within 5oC of actual Peak Temperature (tP) Ramp-down Rate Time 25oC to Peak Temperature 3. Flow (wave) soldering (solder dipping) Products Pb devices. Pb-Free devices. Sn-Pb Eutectic Assembly