AN12979A

DATA SHEET Part No. Package Code No. AN12979A ULGA020-L-0404 Publication date: October 2008 SDE00031BEB 1 AN12979A Contents Overview Features Package Type ……..……………………………………………………………………………………………………. 3 ……..……………………………………………………………………………………………………. 3 ………………………………………………………………………………………………………. 3 …………………………………...………………………………………………………………………. 3 Applications …………….………………………………………………………………………………………………… 3 …………………..………………………………………………………………………………. 5 ……………………..……………..…………………………......………………… 6 ………………….………………….…………………………………………………. 7 ……………………………………………………. 9 Application Circuit Example (Block Diagram) ……….…………………………………………………………. 4 Pin Descriptions Absolute Maximum Ratings Electrical Characteristics Technical Data Usage Notes Operating Supply Voltage Range …………………………………………..……………………………………. 6 Electrical Characteristics (Reference values for design) …………………………………….………….…………………………………………………. 10 ……….……………………….………………….…………………………………………………. 21 SDE00031BEB 2 AN12979A AN12979A Overview Stereo BTL amplifier IC with built-in AGC (I2C bus-control correspondence) AN12979A is the stereo BTL amplifier which contained the AGC circuit for clip prevention of a speaker output. This IC performs a mode change by the I2C bus control system. (Standby function ON/OFF change etc.) Features Selection by I2C bus control is possible in the on-level of AGC. (3-bit, 8-step) Selection by I2C bus control is possible in an attack/recovery time of AGC. (attack: 2-bit, recovery: 3-bit) The resistance and the capacitor of a detector circuit which were being used for the conventional AGC are unnecessary. In order to realize high efficiency of output power, it adopts CMOS power amplifier circuit . Built-in compulsion shutdown terminal. Applications Audio amplifier for mobile, such as a cellular phone Package 20 pin Fine Pitch Land Grid Array Package (LGA Type) Type Bi-CMOS IC SDE00031BEB 3 AN12979A Application Circuit Example (Block Diagram) VCC 3V 1 μF 15 VREF PREOUT-R 100 pF 0.1 μF IN(R) 10 kΩ 17 10 kΩ FB-R GND 0.1 μF IN(L) 10 kΩ 10 kΩ 100 pF PREOUT-L FB-L 19 20 I2C-BUS Control 1 SD VCC_D * 1 μF 14 13 12 1 μF ROUT (Positive) 11 SPEAKER 8Ω TEST VREFSP 10 GND_SPR 16 ±0 dB +14 dB +6 dB － + AGC +14 dB 9 ROUT (Negative) VCC_SP 18 ±0 dB DET 8 AGC +6 dB 3V 1 μF － + 7 +14 dB LOUT (Negative) GND_SPL 6 +14 dB SPEAKER 8Ω 2 0.1 μF 3 SCL 4 5 LOUT (Positive) 1 μF SDA Operate 2.2 kΩ 2.2 kΩ Shut-down VCC_D 1 pin Operate voltage VCC_D = 1.8 V Operate > 1.62 V Shut-down < 0.18 V VCC_D = 2.6 V Operate > 2.34 V Shut-down < 0.26 V 1.8 V Note) 1. This circuit and these circuit constants show an example and do not guarantee the design as a mass-production set. 2. *: The threshold voltage at 1pin has the VCC_D dependency. SDE00031BEB 4 AN12979A Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 S.D SCL SDA VCC_D LOUT_POS GND_SPL LOUT_NEG VCC_SP ROUT_NEG GND_SPR ROUT_POS VREF_SP TEST1 VCC VREF PREOUT_R FB_R GND FB_L PREOUT_L Pin name Type — Input Input / Output Power Supply Output Ground Output Power Supply Output Ground Output Input — Power Supply Input Output Input Ground Input Output Description Terminal for shut-down (VCC: operate, GND: shut-down) SCL SDA Power supply VCC_D for logic circuit SP amp L-ch. output (+) Ground for SP L-ch. amp system SP amp L-ch. output (–) Power supply VCC_SP for SP output SP amp R-ch. output (–) Ground for SP R-ch. amp system SP amp R-ch. output (+) Terminal of reference voltage for SP output circuit Terminal for testing (please connect to Ground) Power supply VCC Terminal of reference voltage First stage amplifier output R-ch. Negative feedback input stage amplifier R-ch. Ground Negative feedback input stage amplifier L-ch. First stage amplifier output L-ch. SDE00031BEB 5 AN12979A Absolute Maximum Ratings A No. Parameter Symbol VCC 1 Supply voltage VCC_D VCC_SP 2 3 4 5 Supply current Power dissipation Operating ambient temperature Storage temperature ICC PD Topr Tstg Rating 3.6 3.6 5.0 — 222 –20 to +70 –55 to +150 A mW °C °C *2 *3 V *1 Unit Note Note) *1: The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2: The power dissipation shown is the value at Ta = 70°C for the independent (unmounted) IC package without a heat sink. When using this IC, refer to the • PD – Ta diagram in the Technical Data and use under the condition not exceeding the allowable value. *3: Except for the power dissipation, operating ambient temperature, and storage temperature, all ratings are for Ta = 25°C. Operating Supply Voltage Range Parameter Symbol VCC Supply voltage range VCC_D VCC_SP Range 2.7 to 3.3 1.7 to 2.6 1.7 to 3.3 2.7 to 4.5 V *1 *2 Unit Note Note) 1. The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. 2. *1: The values under FAST- mode. *2: The values under STANDARD- mode. SDE00031BEB 6 AN12979A Electrical Characteristics at VCC = 3.0 V , VCC_D = 1.8 V , VCC_SP = 3.0 V Note) Ta = 25°C±2°C unless otherwise specified. B No. Circuit Current 1 2 3 4 5 6 7 8 9 Parameter Symbol Conditions Limits Min Typ Max Unit No te Circuit current 1A at non-signal (VCC) Circuit current 2A at non-signal (VCC_SP) Circuit current 3A at non-signal (VCC_D) Circuit current 1B at non-signal (VCC) Circuit current 2B at non-signal (VCC_SP) Circuit current 3A at non-signal (VCC_D) Circuit current 1C at non-signal (VCC) Circuit current 1C at non-signal (VCC_SP) Circuit current 1C at non-signal (VCC_D) IVCC1A IVCC2A IVCC3A IVCC1B IVCC2B IVCC3B IVCC1C IVCC2C IVCC3C VCC = 3.0 V, Non-signal STB = OFF, SP = ON, AGC = ON VCC_SP = 3.0 V, Non-signal STB = OFF, SP = ON, AGC = ON VCC_D = 1.8V, Non-signal STB = OFF, SP = ON, AGC = ON VCC = 3.0 V, Non-signal STB = ON, SP = OFF, AGC = ON VCC_SP = 3.0 V, Non-signal STB = ON, SP = OFF, AGC = ON VCC_D = 1.8V, Non-signal STB = ON, SP = OFF, AGC = ON VCC = 3.0 V, Non-signal STB = OFF, SP = OFF, AGC = ON VCC_SP = 3.0 V, Non-signal STB = OFF, SP = OFF, AGC = ON VCC_D = 1.8 V, Non-signal STB = OFF, SP = OFF, AGC = ON 1.5 1.0 ⎯ ⎯ ⎯ ⎯ 1.5 ⎯ ⎯ 3.9 13 0.1 0.1 0.1 0.1 3.7 0.3 0.1 6.0 29 10 1.0 1.0 1.0 6.0 1.0 10 mA mA μA μA μA μA mA mA μA Input/output characteristics 11 SP reference output level 12 SP reference output distortion 13 SP reference output noise voltage 14 SP maximum rating output 15 Output level at power save 16 SP AGC output level 1 17 SP AGC output level 2 VSPOL VSPOR THSPOL THSPOR Vin = –34.0 dBV, f = 1 kHz RL = 8 Ω Vin = –34.0 dBV, f = 1 kHz RL = 8 Ω , to THD5th –9.5 ⎯ ⎯ 300 ⎯ 3.0 3.0 –8.0 0.07 –75 500 –114 4.0 4.0 –6.5 0.5 –68 ⎯ –90 5.0 5.0 dBV % dBV mW dBV dBV dBV VNSPOL Non-Signal VNSPOR using A curve filter VMSPOL THD = 10%, f = 1 kHz VMSPOR RL = 8 Ω , AGC = OFF VSSPOL VSSPOR Vin = –34.0 dBV, f = 1 kHz RL = 8 Ω, using A curve filter VSPOA1L Vin = –19.0 dBV, f = 1 kHz VSPOA1R RL = 8 Ω, AGC－SELECT = [011] VSPOA2L Vin = –12.0 dBV, f = 1 kHz VSPOA2R RL = 8 Ω, AGC－SELECT = [011] SDE00031BEB 7 AN12979A Electrical Characteristics at VCC = 3.0 V , VCC_D = 1.8 V , VCC_SP = 3.0 V (continued) Note) Ta = 25°C±2°C unless otherwise specified. B No. I2C interface Parameter Symbol Conditions Limits Min Typ Max 0.3 × VCC_D VCC_D + 0.5 0.2 × VCC_D 10 400 Unit No te 43 SCL,SDA signal input Low Level 44 SCL,SDA signal input Low Level 45 SDA output signal Low Level 46 SCL,SDA Signal Input Current 47 SCL maximum frequency of signal input VIL VIH VOL Ii fSCL ⎯ ⎯ Open corrector, sync current: 3mA Input voltage: 0.1 V to 1.7 V ⎯ – 0.5 0.7 × VCC_D 0 –10 0 ⎯ ⎯ ⎯ ⎯ ⎯ V V V μA kHz The threshold voltage at 1-pin 48 Shut-down input Low Level 49 Shut-down input High Level Vsdlth Vsdhth ⎯ ⎯ ⎯ 0.9 × VCC_D ⎯ ⎯ 0.1 × VCC_D ⎯ V V SDE00031BEB 8 AN12979A Electrical Characteristics (Reference values for design) at VCC = 3.0 V , VCC_D = 1.8 V, VCC_SP = 3.0 V Note) Ta = 25°C±2°C unless otherwise specified. The characteristics listed below are reference values derived from the design of the IC and are not guaranteed by inspection. If a problem does occur related to these characteristics, we will respond in good faith to user concerns. B No. I2C interface 66 67 68 69 70 71 72 73 74 75 Parameter Symbol Conditions Limits Min Typ Max Unit No te Bass free time between a condition of stop and a condition of start Setup time of a condition of start Hold time of a condition for satart "L" time of SCL clock "H" time of SCL clock Rising time of SDA , SCL signal Fall time of SDA,SCL signal Data setup time Data hold time Rising up time of a condition of stop tBUF tSU;STA tHD;STA tLow tHigh tR tF tSU;DAT tHD;DAT tSU;STO ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 1.3 0.6 0.6 1.3 0.6 ⎯ ⎯ 0.1 0 0.6 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0.3 0.3 ⎯ 0.9 ⎯ μs μs μs μs μs μs μs μs μs μs *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 Note) *1: All values are VIHmin (*2) and VILmax (*3) level standard. *2: VIHmin is the minimum limit of the signal input high level. *3: VILmax is the maximum limit of the signal input low level. START CONDITION VIHmin (*2) VILmax (*3) Repeated START CONDITION STOP CONDITION START CONDITION SDA tF tLow tR tSU;DAT tF tBUF tR tHD;STA SCL tHD;STA tHD;DAT tHigh tSU;STA tSU;STO SDE00031BEB 9 AN12979A Technical Data I2C-bus Mode 1. Write Mode SDA SCL SLAVE ADDRESS SUB ADDRESS DATA ACK ACK STOP CONDITION START CONDITION ACK 1011 B 0110 6 0000 0001 1000 8 0000 0 0 1 Example of transmission messages Two transmission messages (i.e., the SCL and SDA) are sent in synchronous serial transmission. The SCL is a clock with fixed frequency. The SDA indicates address data for the control of the reception side, and is sent in parallel in synchronization with the SCL. The data is transmitted in 8-bit, 3 octets (bytes) in principle, where every octet has an acknowledge bit. The following description provides information on the structure of the frame. When the level of the SDA changes to low from high while the level of the SCL is high, the data reception of the receiver will be enabled. When the level of the SDA changes to high from low while the level of the SCL is high, the data reception of the receiver will be aborted. The slave address is a specified one unique to each device. When the address of another device is sent, the reception will be aborted. The sub address is a specified one unique to each function. Data is information under control. The acknowledge bit is used to enable the master to acknowledge the reception of data for each octet. The master acknowledges the data reception of the receiver by transmitting a high-level signal to the receiver and receiving a low-level signal returned from the receiver as shown by the dotted lines in Fig. The communication will be aborted if the low signal is not returned. The SDA will not change when the level of the SCL is high except start or stop conditions are enabled. SDE00031BEB 10 AN12979A Technical Data (continued) I2C-bus Mode (continued) 1. Write Mode (continued) (a) I2C-bus PROTOCOL Slave address: 10110110 (B6Hex) Format (normal) S Start condition Slave address WA Sub address A Data byte A P Stop condition Acknowledge bit Write Mode: 0 (b) Auto increment Sub-address 0*Hex: Auto increment mode (When the data is sent in sequence, the sub address will change one by one and the data will be input.) Auto increment mode S Slave address WA Sub address A Data 1 A Data 2 A Data n A P (c) Initial condition The initial state of the device is not guaranteed. Therefore, the input of 00Hex resister-D0 (Note.1) will be absolutely 0, when the power is turned ON. (d) Sub-address Byte and Data Byte Format Data byte Sub-address MSB D7 D6 D5 LSB D3 D2 SP Save 0 → ON 1 → OFF D1 Standby 0 → ON 1 → OFF D0 D4 *0Hex ＊ ＊ 0 (Note.2) AGC-ON data bit1 0 (Note.2) 0 (Note.2) AGC 0 → OFF 1 → ON 0 (Note.1) *1Hex AGC-ON AGC-ON data bit3 data bit2 0 (Note.2) 0 (Note.2) AGC-REC AGC-REC AGC-REC AGC-ATT AGC-ATT data bit3 data bit2 data bit1 data bit2 data bit1 0 (Note.2) 0 (Note.2) 0 (Note.2) *2Hex ＊ ＊ D0, D4, D5, D6, D7: Always set to 0 D1: Standby ON/OFF switch D2: SP Save ON/OFF switch D3: AGC ON/OFF switch D0, D1 : AGC-attack-time selection D2, D3, D4: AGC-recovery-time selection D5, D6, D7: AGC-on-level selection D0 to D7: Always set to 0 (test&adjust mode) 0 (Note.2) Please use these bit only Data = "0“, because they are used by our company’s final test and fine-tuning AGC-on level. Note that Data = "0" is Not shut-down mode. SDE00031BEB 11 AN12979A Technical Data (continued) I2C-bus Mode (continued) 1. Write Mode (continued) (e) AGC-attack-time selection Write 01Hex Register D1 0 0 1 1 D0 0 1 0 1 Attack time 0.5 ms 1 ms 2 ms 4 ms (f) AGC-recovery-time selection Write 01Hex Register D4 0 0 0 0 1 1 1 1 (g) AGC-on-level selection (at VCC = 3.0 V, VCC_SP = 3.0 V) Write 01Hex Register D7 0 0 0 0 1 1 1 1 D6 0 0 1 1 0 0 1 1 D5 0 1 0 1 0 1 0 1 AGC On Level 1 dBV 2 dBV 3 dBV 4 dBV 5 dBV 6 dBV 7 dBV 8 dBV D3 0 0 1 1 0 0 1 1 D2 0 1 0 1 0 1 0 1 Recovery time 1.0 s 1.5 s 2.0 s 3.0 s 4.0 s 6.0 s 8.0 s 12.0 s Output Po ( RL = 8 W ) 157 mW 198 mW 249 mW 314 mW 395 mW 498 mW 626 mW 789 mW VCC_SP (Recommend) 2.7 V ≤ 2.7 V ≤ 2.7 V ≤ 3.0 V ≤ 3.3 V ≤ 3.7 V ≤ 4.1 V ≤ 4.5 V SDE00031BEB 12 AN12979A Technical Data (continued) I2C-bus Mode (continued) 2. Read Mode (a)I2C-bus PROTOCOL Slave address 10110111(B7Hex) Format S Slave address R A Data 0 A Data 1 A Data 2 A P Read Mode: 1 Note) At the slave address input, it is sequentially output from data 0. There is no necessity for inputting the sub-address. (b) Sub-address Byte and Data Byte Format MSB D7 D6 D5 Sub address *0Hex Latch data [D5] Sub address *1Hex Latch data [D5] Sub address *2Hex Latch data [D5] D4 Data byte D3 D2 Sub address *0Hex Latch data [D2] Sub address *1Hex Latch data [D2] Sub address *2Hex Latch data [D2] D1 Sub address *0Hex Latch data [D1] Sub address *1Hex Latch data [D1] Sub address *2Hex Latch data [D1] LSB D0 Sub address *0Hex Latch data [D0] Sub address *1Hex Latch data [D0] Sub address *2Hex Latch data [D0] Data 0 Sub address Sub address *0Hex *0Hex Latch data Latch data [D6] [D7] Sub address Sub address *1Hex *1Hex Latch data Latch data [D6] [D7] Sub address Sub address *2Hex *2Hex Latch data Latch data [D6] [D7] Sub address Sub address *0Hex *0Hex Latch data Latch data [D3] [D4] Sub address Sub address *1Hex *1Hex Latch data Latch data [D3] [D4] Sub address Sub address *2Hex *2Hex Latch data Latch data [D3] [D4] Data 1 Data 2 Purchase of Panasonic I2C components conveys a license under the Philips I2C patent right to use these components in an I2C systems, provided that the system conforms to the I2C standard specification as defined by Philips. Operating temperature guarantee of I2C-bus Control The performance in the ambient temperature of operation is guaranteed theoretically in the design at normal temperature (25°C) by inspecting it at a speed of the clock that is about 50% earlier regarding the operating temperature guarantee of I2C-bus Control. But the following characteristics are logical values derived from the design of the IC and are not guaranteed by inspection. If a problem does occur related to these characteristics, Panasonic will respond in good faith to customer concerns. SDE00031BEB 13 AN12979A Technical Data (continued) I/O block circuit diagrams and pin function descriptions Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Pin No. Waveform and voltage Internal circuit VCC_D Description Shut-down 1 VCC_D to VCCを印加 1.8 V to 3.0 V 1 IC is shut down by pin1 being shorted to GND.(All I2C Data become 0.) VCC_D SCL 2 Hi-Z 2 I2C-BUS SCL pin VCC_D SDA 3 Hi-Z 3 I2C-BUS SDA pin GND VCC_D 4 1.8 V(typ.) － Power supply pin for I2C-BUS SDE00031BEB 14 AN12979A Technical Data (continued) I/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Pin No. Waveform and voltage Internal circuit VCC_SP Description LOUT_POS 5 DC 1.45 V 400k 5 L-ch. positive speaker output pin GND_SPL 6 GND_SPL － Ground pin for L-ch. speaker output VCC_SP LOUT_NEG 7 DC 1.45 V 400k 7 L-ch. negative speaker output pin GND_SPL VCC_SP 8 3.0 V(typ.) － Power supply pin for speaker output SDE00031BEB 15 AN12979A Technical Data (continued) I/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Pin No. Waveform and voltage Internal circuit VCC_SP Description ROUT_NEG 9 DC 1.45 V 400k 9 R-ch. negative speaker output pin GND_SPR 10 GND_SPR － GND pin for R-ch. speaker output VCC_SP ROUT_POS 11 DC 1.45 V 400k GND_SPR 11 R-ch. positive speaker output pin VCC_SP VREF_SP 12 DC 1.45 V 12 10k 1k 150k Reference voltage pin for output stage 150k SDE00031BEB 16 AN12979A Technical Data (continued) I/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Pin No. Waveform and voltage Internal circuit Description 13 TEST1 13 Hi-Z Please connect to GND. Test mode pin VCC 14 3.0 V(typ.) － Power supply pin VCC VREF 15 DC 1.45 V 15 10k 1k 150k Reference voltage pin 150k VCC PREOUT_R 16 DC 1.45 V 10k 1k 16 First stage amplifier R-ch. output pin SDE00031BEB 17 AN12979A Technical Data (continued) I/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Pin No. Waveform and voltage Internal circuit Description 17 FB_R 17 DC 1.45 V 10k Negative feedback pin for input stage amplifier R-ch. 18 GND － Ground pin 19 FB_L 19 DC 1.45 V 10k Negative feedback pin for input stage amplifier L-ch. VCC PREOUT_L 20 DC 1.45 V 10k 1k 20 First stage amplifier L-ch. output pin SDE00031BEB 18 AN12979A Technical Data (continued) Power supply and logic sequence Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. The timing control of power-ON/OFF and each logic according to the procedure below should be recommended for the best pop performance caused in switching. 1. The sequence of the power supply and each logic Please first bring up the power supply, and then the standby off. The basic procedure at the power-on 1. The power OFF condition Both the standby and the SP_Save are in the ON condition. 2. Power ON 3. Standby Off 4. SP_Save Off VCC,VCC_SP, VCC_D, SD Power supply Off On On Off Off Standby On Off SP_Save On 20 ms or more * Off Off On The basic procedure at the power-off 1. The power ON condition Both the standby and the SP_Save are in the OFF condition. 2. SP_Save On ( = Standby On) 3. Standby On 4. Power Off On 0 ms or more After at least 20 ms has passed after the standby off, please off SP_Save. Please control Standby On to simultaneous with SP_Save On, or the back. Note) *: This IC contains the pre-charge circuit. It is time until each bias is stabilized from Standby Off. It depends for this time on the capacity value linked to a reference voltage terminal (VREF and VREFSP), and the capacity value and resistance linked to an input terminal (IN_R and IN_L). It is a recommendation value in a constant given in the example of Application Circuit Example (Block Diagram). 2．The sequence of VCC and VCC_SP and VCC_D This IC have not a standup and falling order in VCC and VCC_SP. A standup and falling time of VCC and VCC_SP recommend 1 or more ms. VCC VCC_SP VCC_D On Off On Off 1 ms or more 1 ms or more SDE00031BEB 19 AN12979A Technical Data (continued) PD ⎯ Ta diagram SDE00031BEB 20 AN12979A Usage Notes 1. Please take notice in the use of this product that it might break or occasionally smoke when an abnormal state occurs such as SP output pin (Pin5, Pin7, Pin9, Pin11 ) – power supply pin short, SP output pin(Pin5, Pin7, Pin9, Pin11 ) – GND short, or SP output (Pin5, Pin7, Pin9, Pin11) -to-SP output-pin short (load short). 2. Please absolutely do not mount the IC in the reverse direction on to the printed-circuit-board. It damaged when the electricity is turned on. 3. Please do not make it open, because the open SDpin(Pin1) is not fixed. SDE00031BEB 21 Request for your special attention and precautions in using the technical information and semiconductors described in this book (1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. (2) The technical information described in this book is intended only to show the main characteristics and application circuit examples of the products. No license is granted in and to any intellectual property right or other right owned by Panasonic Corporation or any other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book. (3) The products described in this book are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: – Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. – Any applications other than the standard applications intended. (4) The products and product specifications described in this book are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (6) Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS, thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. (7) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of our company. 20080805