EK423422-01

Product Specification PE423422 UltraCMOS® SPDT RF Switch 100–6000 MHz Product Description The PE423422 is a HaRP™ technology-enhanced reflective SPDT RF switch. It has received AEC-Q100 Grade 2 certification and meets the quality and performance standards that makes it suitable for use in harsh automotive environments. It is designed to cover a wide range of wireless applications from 100 MHz through 6 GHz such as automotive infotainment and traffic safety applications. No blocking capacitors are required if DC voltage is not present on the RF ports. Features Peregrine’s HaRP™ technology enhancements deliver high linearity and excellent harmonics performance. It is an innovative feature of the UltraCMOS® process, offering the performance of GaAs with the economy and integration of conventional CMOS.  High isolation The PE423422 is manufactured on Peregrine’s UltraCMOS® process, a patented variation of silicon-oninsulator (SOI) technology on a sapphire substrate, offering excellent RF performance.  AEC-Q100 Grade 2 certified  Supports operating temperature up to +105°C  Low insertion loss     0.25 dB @ 1000 MHz 0.40 dB @ 3000 MHz 0.65 dB @ 5000 MHz 0.90 dB @ 6000 MHz     41 dB @ 1000 MHz 28 dB @ 3000 MHz 20 dB @ 5000 MHz 16 dB @ 6000 MHz  Excellent linearity  IIP2 of 115 dBm  IIP3 of 73.5 dBm  High ESD tolerance  1kV HBM on all pins  200V MM on all pins  1kV CDM on all pins  Wide supply range of 2.3V to 5.5V Figure 1. Functional Diagram Figure 2. Package Type 12-lead 2x2 mm QFN DOC-02173 Document No. DOC-30514-2 | www.psemi.com ©2013-2014 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 13 PE423422 Product Specification Table 1. Electrical Specifications @ 25°C, VDD = 2.3V to 5.5V (ZS = ZL = 50Ω) Parameter Path Condition Min Operational frequency 100 Insertion loss 6000 MHz 100–1000 MHz 0.25 0.35 dB 1000–2000 MHz 0.30 0.40 dB 2000–3000 MHz 0.40 0.50 dB 3000–4000 MHz 0.50 0.70 dB 4000–5000 MHz 0.65 1 0.90 dB 5000–6000 MHz 0.90 1.251 dB 100–1000 MHz 39 41 dB 1000–2000 MHz 32 33 dB 2000–3000 MHz 26 28 dB 3000–4000 MHz 22 24 dB 4000–5000 MHz 18 20 dB 5000–6000 MHz 15 16 dB 100–1000 MHz 41 44 dB 1000–2000 MHz 33 35 dB 2000–3000 MHz 27 29 dB 3000–4000 MHz 22 24 dB 4000–5000 MHz 18 20 dB 5000–6000 MHz 15 17 dB 100–1000 MHz 28 dB 1000–2000 MHz 21 dB 2000–3000 MHz 20 dB 3000–4000 MHz 18 dB 4000–5000 MHz 1 dB 1 RFC–RFX Return loss RFC–RFX 2nd Harmonic, 2fo 16 5000–6000 MHz 13 dB +32 dBm output power, 850 / 900 MHz -99 dBc +32 dBm output power, 1800 / 1900 MHz -101 dBc +32 dBm output power, 850 / 900 MHz -93 dBc +32 dBm output power, 1800 / 1900 MHz -87 dBc Bands I, II, V, VIII +20 dBm CW @ TX freq at RFC, -15 dBm CW @ 2Tx-Rx at RFC, 50Ω -122 dBm RFC–RFX 100–6000 MHz 115 dBm RFC–RFX 100–6000 MHz 73.5 dBm RFC–RFX 100–6000 MHz 34 dBm 50% CTRL to 90% or 10% RF 2 RFC–RFX 3rd Harmonic, 3fo RFC–RFX IMD3 Input IP2 Input IP3 Notes: Unit RFX–RFX Isolation Switching time Max RFC–RFX Isolation Input 0.1 dB compression point Typ 2 4 μs 1. High frequency performance can be improved by external matching 2. The input 0.1dB compression point is a linearity figure of merit. Refer to Table 4 for the RF input power PMAX,CW (50Ω) ©2013-2014 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 13 Document No. DOC-30514-2 | UltraCMOS® RFIC Solutions PE423422 Product Specification Table 1A. Electrical Specifications @ -40°C to +105°C, VDD = 2.3V to 5.5V (ZS = ZL = 50Ω) Parameter Path Condition Min Operational frequency 100 Insertion loss 6000 MHz 100–1000 MHz 0.25 0.55 dB 1000–2000 MHz 0.30 0.65 dB 2000–3000 MHz 0.40 0.75 dB 3000–4000 MHz 0.50 0.85 dB 4000–5000 MHz 0.65 1.05 1 dB 5000–6000 MHz 0.90 1.451 dB 100–1000 MHz 38 41 dB 1000–2000 MHz 31 33 dB 2000–3000 MHz 25 28 dB 3000–4000 MHz 21 24 dB 4000–5000 MHz 17 20 dB 5000–6000 MHz 14 16 dB 100–1000 MHz 40 44 dB 1000–2000 MHz 32 35 dB 2000–3000 MHz 26 29 dB 3000–4000 MHz 21 24 dB 4000–5000 MHz 17 20 dB 5000–6000 MHz 14 17 dB 100–1000 MHz 28 dB 1000–2000 MHz 21 dB 2000–3000 MHz 20 dB 3000–4000 MHz 18 dB 4000–5000 MHz 1 dB 1 RFC–RFX Return loss RFC–RFX 2nd Harmonic, 2fo 16 5000–6000 MHz 13 dB +32 dBm output power, 850 / 900 MHz -99 dBc +32 dBm output power, 1800 / 1900 MHz -101 dBc +32 dBm output power, 850 / 900 MHz -93 dBc +32 dBm output power, 1800 / 1900 MHz -87 dBc Bands I, II, V, VIII +20 dBm CW @ TX freq at RFC, -15 dBm CW @ 2Tx-Rx at RFC, 50Ω -122 dBm RFC–RFX 100–6000 MHz 115 dBm RFC–RFX 100–6000 MHz 73.5 dBm RFC–RFX 100–6000 MHz 34 dBm 50% CTRL to 90% or 10% RF 2 RFC–RFX 3rd Harmonic, 3fo RFC–RFX IMD3 Input IP2 Input IP3 Notes: Unit RFX–RFX Isolation Switching time Max RFC–RFX Isolation Input 0.1 dB compression point Typ 2 5 μs 1. High frequency performance can be improved by external matching 2. The input 0.1dB compression point is a linearity figure of merit. Refer to Table 4 for the RF input power PMAX,CW (50Ω) Document No. DOC-30514-2 | www.psemi.com ©2013-2014 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 13 PE423422 Product Specification Figure 3. Pin Configuration (Top View) Table 3. Operating Ranges Symbol Min Typ Max Unit Supply voltage VDD 2.3 3.3 5.5 V Supply current IDD 120 200 µA Digital input high (V1, LS) VIH 1.2 1.5 3.3 V Digital input low (V1,LS) VIL 0 0 0.5 V Fig. 4 dBm +105 °C Parameter RF input power, CW (RFC-RFX)1 PMAX,CW Operating temperature range TOP -40 +25 Note 1: 100% duty cycle, all bands, 50Ω Table 4. Absolute Maximum Ratings Table 2. Pin Descriptions Parameter/Condition Supply voltage Min Max Unit VDD -0.3 5.5 V -0.3 3.3 V Fig. 4 dBm +150 °C VESD,HBM 1000 V VESD,MM 200 V VESD,CDM 1000 V Pin # Pin Name 1, 3, 4, 6, 7 GND Ground Digital input voltage (V1, LS) VI 2 RF21 RF port 2 RF input power, Max PMAX,ABS 5 1 RF common Storage temperature range 1 RF port 1 RFC Description Symbol 8 RF1 9 DGND 10 V1 Digital control logic input 1 11 LS Logic Select 12 VDD Supply voltage Pad GND Note 1: Digital ground ESD voltage MM, all pins 2 ESD voltage CDM, all pins Notes: 3 TST -65 1. Human Body Model (MIL_STD-883 Method 3015) 2. Machine Model (JEDEC JESD22-A115) 3. Charged Device Model (JEDEC JESD22-C101) Exposed pad: Ground for proper operation RF pins 2, 5 and 8 must be at 0V DC. The RF pins do not require DC blocking capacitors for proper operation if the 0V DC requirement is met ©2013-2014 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 13 ESD voltage HBM, all pins 1 Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. Document No. DOC-30514-2 | UltraCMOS® RFIC Solutions PE423422 Product Specification Electrostatic Discharge (ESD) Precautions Table 5. Truth Table When handling this UltraCMOS® device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS® devices are immune to latch-up. Path V1 LS RFC–RF2 1 1 RFC–RF1 0 1 RFC–RF1 1 0 RFC–RF2 0 0 Moisture Sensitivity Level The Moisture Sensitivity Level rating for the PE423422 in the 12-lead 2x2 mm QFN package is MSL1. Figure 4. Power De-rating Curve for 100–6000 MHz vs Ambient Temperature (50Ω) 35.0 34.5 34.0 33.5 Input Power (dBm) 33.0 32.5 32.0 31.5 31.0 30.5 30.0 29.5 Pmax,cw Pmax,abs 29.0 ‐40 ‐35 ‐30 ‐25 ‐20 ‐15 ‐10 ‐5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 Ambient Temperature (C) Document No. DOC-30514-2 | www.psemi.com ©2013-2014 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 13 PE423422 Product Specification Typical Performance Data @ 25°C and VDD = 3.3V unless otherwise specified Figure 5. Insertion Loss RFX Figure 6. Insertion Loss vs Temp (RFC–RF1) Figure 7. Insertion Loss vs VDD (RFC–RF1) Figure 8. Insertion Loss vs Temp (RFC–RF2) Figure 9. Insertion Loss vs VDD (RFC–RF2) ©2013-2014 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 13 Document No. DOC-30514-2 | UltraCMOS® RFIC Solutions PE423422 Product Specification Typical Performance Data @ 25°C and VDD = 3.3V unless otherwise specified Figure 10. RFC Port Return Loss vs Temp (RF1 Active) Figure 11. RFC Port Return Loss vs VDD (RF1 Active) Figure 12. RFC Port Return Loss vs Temp (RF2 Active) Figure 13. RFC Port Return Loss vs VDD (RF2 Active) Document No. DOC-30514-2 | www.psemi.com ©2013-2014 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 13 PE423422 Product Specification Typical Performance Data @ 25°C and VDD = 3.3V unless otherwise specified Figure 14. Active Port Return Loss vs Temp (RF1 Active) Figure 15. Active Port Return Loss vs VDD (RF1 Active) Figure 16. Active Port Return Loss vs Temp (RF2 Active) Figure 17. Active Port Return Loss vs VDD (RF2 Active) ©2013-2014 Peregrine Semiconductor Corp. All rights reserved. Page 8 of 13 Document No. DOC-30514-2 | UltraCMOS® RFIC Solutions PE423422 Product Specification Typical Performance Data @ 25°C and VDD = 3.3V unless otherwise specified Figure 18. Isolation vs Temp (RF1–RF2, RF1 Active) Figure 19. Isolation vs VDD (RF1–RF2, RF1 Active) Figure 20. Isolation vs Temp (RFC–RF2, RF1 Active) Figure 21. Isolation vs VDD (RFC–RF2, RF1 Active) Document No. DOC-30514-2 | www.psemi.com ©2013-2014 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 13 PE423422 Product Specification Evaluation Board Figure 22. Evaluation Board Layout The SPDT switch evaluation board was designed to ease customer evaluation of Peregrine’s PE423422. The RF common port is connected through a 50Ω transmission line via the top SMA connector, J2. RF1 and RF2 ports are connected through 50Ω transmission lines via SMA connectors J1 and J3, respectively. A through 50Ω transmission is available via SMA connectors J4 and J5. This transmission line can be used to estimate the loss of the PCB over the environmental conditions being evaluated. J8 provides DC and digital inputs to the device. The board is constructed of a four metal layer material with a total thickness of 62 mils. The top and bottom RF layers are Rogers RO4350 material with a 10 mil RF core. The middle layers provide ground for the transmission lines. The transmission lines were designed using a coplanar waveguide with ground plane model using a trace width of 22 mils, trace gaps of 7 mils, and metal thickness of 2.1 mils. PRT-29005 ©2013-2014 Peregrine Semiconductor Corp. All rights reserved. Page 10 of 13 Document No. DOC-30514-2 | UltraCMOS® RFIC Solutions PE423422 Product Specification Figure 23. Evaluation Board Schematic DOC-30527 Document No. DOC-30514-2 | www.psemi.com ©2013-2014 Peregrine Semiconductor Corp. All rights reserved. Page 11 of 13 PE423422 Product Specification Figure 24. Package Drawing 12-lead 2x2 mm QFN 0.25 (X12) 0.10 C A 2.00 (X2) 0.475 (X12) B 1.10±0.05 9 7 0.50 10 6 2.00 1.10±0.05 4 0.20±0.05 (X12) 0.10 C (X2) 0.50 1.10 2.40 12 1 3 1.00 0.275±0.05 (X12) 1.10 2.40 PIN #1 Identifier BOTTOM VIEW TOP VIEW RECOMMENDED LAND PATTERN DOC-01882 0.10 C 0.10 0.05 0.55±0.05 0.05 C C A B C ALL FEATURES SEATING PLANE 0.152 REF. SIDE VIEW 0.05 MAX C Figure 25. Top Marking Specifications PPZZ YWW Marking Spec Symbol Package Marking PP DU ZZ 00-99 Y 0-9 WW 01-53 Definition Part number marking for PE423422 Last two digits of lot code Last digit of year, starting from 2009 (0 for 2010, 1 for 2011, etc) Work week DOC-51207 ©2013-2014 Peregrine Semiconductor Corp. All rights reserved. Page 12 of 13 Document No. DOC-30514-2 | UltraCMOS® RFIC Solutions PE423422 Product Specification Figure 26. Tape and Reel Specifications Tape Feed Direction Pin 1 Nominal Tolerance Ao 2.20 ±0.10 Bo 2.20 ±0.10 Ko 0.75 ±0.10 F 3.50 ±0.05 P1 4.00 ±0.10 W 8.00 ±0.30 Top of Device Device Orientation in Tape Note: All dimensions in millimeters unless otherwise specified Table 6. Ordering Information Order Code Description Package Shipping Method PE423422A-Z PE423422 SPDT RF switch Green 12-lead 2x2 mm QFN 3000 units T/R EK423422-01 PE423422 Evaluation kit Evaluation kit 1/Box Sales Contact and Information For Sales and contact information please visit www.psemi.com. Advance Information: The product is in a formative or design stage. The datasheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification: The datasheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification: The datasheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer Notification Form). The information in this datasheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. Document No. DOC-30514-2 | www.psemi.com No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com ©2013-2014 Peregrine Semiconductor Corp. All rights reserved. Page 13 of 13