EK43205-01

Product Specification PE43205 UltraCMOS® RF Digital Attenuator 2-bit, 18 dB, 35–6000 MHz Product Description The PE43205 is a 50Ω, HaRP™ technology-enhanced fast switching 2-bit RF Digital Step Attenuator (DSA) designed for use in 3G/4G wireless infrastructure and other high performance RF applications. This DSA is a pin-compatible upgraded version of the PE43204 with a wider frequency and power supply range, and extended operating temperature range. Covering an 18 dB attenuation range in 6 dB and 12 dB steps, it maintains high RF performance and low power consumption from 35 MHz through 6 GHz. PE43205 is offered in a 12-lead 3x3 mm QFN package. In addition, no external blocking capacitors are required if 0 VDC is present on the RF ports. The PE43205 is manufactured on pSemi’s UltraCMOS® process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate. Features  Attenuation: 6 dB / 12 dB steps to 18 dB  Fast switching time of 29 ns  Low attenuation error  0.10 dB @ 2 GHz  0.15 dB @ 3 GHz  High linearity  +61 dBm IIP3 @ 1950 MHz     Wide supply range of 2.3V to 5.5V 1.8V control logic compatible 105°C operating temperature ESD performance  2 kV HBM on all pins  100V MM on all pins  1 kV CDM on all pins  Parallel control pSemi’s HaRP™ technology enhancements deliver high linearity and excellent harmonics performance. It is an innovative feature of the UltraCMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure 1. Functional Diagram Figure 2. Package Type 12-lead 3x3 mm QFN Switched Attenuator Array RF Input Parallel Control RF Output 2 Control Logic Interface DOC-01281 Document No. DOC-85387-2 │ www.psemi.com ©2017, 2019 pSemi Corp. All rights reserved. Page 1 of 11 PE43205 Product Specification Table 1. Electrical Specifications @ +25°C, VDD = 2.3V to 5.5V Parameter Condition Frequency range Min Typ 35 Max Unit 6000 MHz Attenuation range 6 dB and 12 dB steps 0–18 Insertion loss 35 MHz–2 GHz 2–3 GHz 3–4 GHz 4–5 GHz 5–6 GHz 0.50 0.60 0.70 0.85 1.05 0.60 0.70 0.80 1.10 1.30 dB dB dB dB dB Attenuation error 0 dB–18 dB attenuation settings 35 MHz–2 GHz >2–3 GHz >3–4 GHz >4–5 GHz >5–6 GHz 0.10 0.15 0.45 0.55 0.75 0.40 0.50 1.05 1.25 1.55 dB dB dB dB dB Return loss 35 MHz–2 GHz 2–3 GHz 3–4 GHz 4–5 GHz 5–6 GHz 17 14 11 10 9 dB dB dB dB dB Relative phase All states 35 MHz–2 GHz 2–3 GHz 3–4 GHz 4–5 GHz 5–6 GHz 9 12 17 22 24 deg deg deg deg deg Input 0.1dB compression point * 200 MHz–6 GHz 30 dBm IIP3 1950 MHz 61 dBm Switching time 50% DC CTRL to 90% or 10% RF 29 ns –0.45 –0.45 –0.15 –0.15 –0.30 dB Note: * Input 0.1 dB compression point is a linearity figure of merit. Refer to Table 3 for operating RF input power (50Ω). ©2017, 2019 pSemi Corp. All rights reserved. Page 2 of 11 Document No. DOC-85387-2 │ UltraCMOS® RFIC Solutions PE43205 Product Specification Table 1A. Electrical Specifications @ +105°C, VDD = 2.3V to 5.5V Parameter Condition Frequency range Min Typ 35 Max Unit 6000 MHz Attenuation range 6 dB and 12 dB steps 0–18 Insertion loss 35 MHz–2 GHz 2–3 GHz 3–4 GHz 4–5 GHz 5–6 GHz 0.60 0.65 0.80 0.95 1.15 0.70 0.80 0.90 1.20 1.45 dB dB dB dB dB Attenuation error 0 dB–18 dB attenuation settings 35 MHz–2 GHz >2–3 GHz >3–4 GHz >4–5 GHz >5–6 GHz –0.03 –0.10 –0.15 0.25 0.40 0.25 0.30 0.65 0.85 1.15 dB dB dB dB dB Return loss 35 MHz–2 GHz 2–3 GHz 3–4 GHz 4–5 GHz 5–6 GHz 18 15 11 10 9.5 dB dB dB dB dB Relative phase All states 35 MHz–2 GHz 2–3 GHz 3–4 GHz 4–5 GHz 5–6 GHz 9 13 17 23 25 deg deg deg deg deg Input 0.1dB compression point * 200 MHz–6 GHz 30 dBm IIP3 1950 MHz 63 dBm Switching time 50% DC CTRL to 90% or 10% RF 31 ns –0.35 –0.45 –0.45 –0.35 –0.45 dB Note: * Input 0.1 dB compression point is a linearity figure of merit. Refer to Table 3 for operating RF input power (50Ω). Document No. DOC-85387-2 │ www.psemi.com ©2017, 2019 pSemi Corp. All rights reserved. Page 3 of 11 PE43205 Product Specification RF1 2 NC 3 C2 11 10 9 Exposed Pad 8 7 NC 4 5 Table 3. Operating Ranges Symbol Min Supply voltage VDD 2.3 Supply current IDD Digital input high VIH Digital Input Low VIL Parameter GND RF2 NC 6 NC 1 12 NC GND C1 Pin 1 dot marking VDD Figure 3. Pin Configuration (Top View) Max Unit 5.5 V 200 μA 1.17 3.6 V –0.3 0.6 V Digital input leakage 10 μA RF input power, CW 35 MHz–4 GHz >4 GHz–6 GHz PMAX,CW See Fig. 4 +24 dBm dBm PMAX,PULSED See Fig. 4 +27 dBm dBm +105 °C RF input power, pulsed * 35 MHz–4 GHz >4 GHz–6 GHz Operating temperature range –40 +25 Description Table 4. Absolute Maximum Ratings Pin # Pin Name 1 GND 2 2 RF1 RF1 port Supply voltage 3 NC1 No connect 4 NC1 No connect 5 NC1 No connect 6 NC1 No connect 7 NC1 Ground Parameter/Condition Symbol Min Max Unit VDD –0.3 5.5 V Voltage on any digital input VI –0.3 3.6 V Storage temperature range TST –65 +150 °C Maximum input power PMAX,ABS +27.5 dBm No connect ESD voltage HBM1, on all pins VESD,HBM 2000 V ESD voltage MM2, on all pins VESD,MM 100 V ESD voltage CDM3, on all pins VESD,CDM 1000 V 8 RF2 RF2 port 9 GND Ground 10 C2 Attenuation control bit, 12 dB 11 C1 Attenuation control bit, 6 dB 12 VDD Supply voltage (nominal 3.3V) Notes: 1. Pins 3 through 7 may be tied to ground if desired, but they are not connected to ground internal to the package. 2. RF pins 2 and 8 must be at 0 VDC. The RF pins do not require DC blocking capacitors for proper operation if the 0 VDC requirement is met. ©2017, 2019 pSemi Corp. All rights reserved. Page 4 of 11 130 Note: * Pulsed, 5% duty cycle of 4620 µs period, 50Ω Table 2. Pin Descriptions 2 TOP Typ Notes: 1. Human Body Model (MIL-STD 883 Method 3015.7) 2. Machine Model (JEDEC JESD22-A115) 3. Charged Device Model (JEDEC JESD22-C101) Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. Document No. DOC-85387-2 │ UltraCMOS® RFIC Solutions PE43205 Product Specification Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up. Switching Frequency The PE43205 has a maximum 25 kHz switching rate. Switching rate is defined to be the speed at which the DSA can be toggled across attenuation states. Switching time is the time duration between the point the control signal reaches 50% of the final value and the point the output signal reaches within 10% or 90% of its target value. Table 5. Attenuation Word Truth Table C1 C2 Attenuation Setting RF1–RF2 L L Reference I.L. H L 6 dB L H 12 dB H H 18 dB Moisture Sensitivity Level The Moisture Sensitivity Level rating for the PE43205 in the 12-lead 3x3 mm QFN package is MSL1. Exposed Solder Pad Connection The exposed solder pad on the bottom of the package must be grounded for proper device operation. Spurious Performance The typical low-frequency spurious performance of the PE43205 is –135 dBm. Figure 4. Power De-Rating Curve for 35 MHz–4 GHz 29.0 27.0 Input Power (dBm) 25.0 23.0 Maximum Input Power 21.0 RF Input Power, Pulsed @ 25C Ambient 19.0 RF Input Power, Pulsed @ 105C Ambient RF Input Power, CW @ 25C Ambient 17.0 RF Input Power, CW @ 105C Ambient 15.0 35 350 Frequency (MHz) Document No. DOC-85387-2 │ www.psemi.com 3500 ©2017, 2019 pSemi Corp. All rights reserved. Page 5 of 11 PE43205 Product Specification Typical Performance Data @ +25°C and VDD = 3.3V, unless otherwise specified Figure 5. Attenuation vs. Attenuation Setting 1GHz 2 GHz 3 GHz 4 GHz 5 GHz Figure 6. Attenuation Error vs. Frequency 6dB 6 GHz 20 0.8 18 0.7 12dB 18dB 16 0.6 Attenuation Error (dB) Attenuation (dB) 14 12 10 8 6 0.5 0.4 0.3 0.2 4 0.1 2 0 0 0 6 12 18 Attenuation State (dB) 0 1 2 3 Frequency (GHz) 4 5 6 Figure 7. Insertion Loss vs. Temperature Figure 8. Input Return Loss vs. Attenuation State Figure 9. Output Return Loss vs. Attenuation State Figure 10. Input Return Loss vs. Temperature @ 12 dB State ©2017, 2019 pSemi Corp. All rights reserved. Page 6 of 11 Document No. DOC-85387-2 │ UltraCMOS® RFIC Solutions PE43205 Product Specification Typical Performance Data @ 25°C and VDD = 3.3V, unless otherwise specified Figure 11. Output Return Loss vs. Temperature @ 12 dB State Figure 12. Relative Phase vs. Frequency 6dB 12dB 18dB 30 Phase Error (Deg) 25 20 15 10 5 0 0 1 2 3 Frequency (GHz) 4 Document No. DOC-85387-2 │ www.psemi.com 5 6 ©2017, 2019 pSemi Corp. All rights reserved. Page 7 of 11 PE43205 Product Specification Evaluation Kit Figure 13. Evaluation Board Layout The 2-bit DSA evaluation kit board was designed to ease customer evaluation of pSemi’s PE43205. To evaluate the PE43205, apply 3.3V to the VDD header pin and Ground to the GND header pin. The DUT can be controlled two ways: 1. The mechanical switches in conjunction with the VCTL pin can be used. Apply desired control voltage to VCTL header pin. The top mechanical switch controls the 6 dB stage, the bottom mechanical switch controls the 12 dB stage. For each switch, the left position is the 0V condition, while the right position is the VCTRL condition. The middle position leaves the control pin floating. 2. The CTL1 and CTL2 pins on the header can be used. Each pin directly controls the 6 dB and 12 dB stage respectively. The VCTL pin on the header is left open. The mechanical switches may be left uninstalled or must be kept in the middle position. Note: To accurately measure the fast switching performance of the PE43205, C3 and C4 should be removed. PRT-53374 Power-up Control Settings The PE43205 will always power up into the state determined by the voltages on the two control pins. The DSA can be preset to any state within the 18 dB range by pre-setting the parallel control pins prior to power-up. There is a 10 μs delay between the time the DSA is powered-up to the time the desired state is set. If the control pins are left floating during power-up, the device will default to the minimum attenuation setting (insertion loss state). ©2017, 2019 pSemi Corp. All rights reserved. Page 8 of 11 Document No. DOC-85387-2 │ UltraCMOS® RFIC Solutions PE43205 Product Specification Figure 14. Evaluation Board Schematic Notes: 1. Use PCB part number PRT-53374. 2. CAUTION: Contains parts and assemblies susceptible to damage by electrostatic discharge (ESD). Document No. DOC-85387-2 │ www.psemi.com DOC-30927 ©2017, 2019 pSemi Corp. All rights reserved. Page 9 of 11 PE43205 Product Specification Figure 15. Package Drawing 12-lead 3x3 mm QFN 0.10 C 3.00 A (2X) B 9 7 0.50 (x8) 0.75 (x12) 10 6 1.15±0.05 3.00 1.20 3.40 12 4 0.23±0.05 (X12) 0.50 0.28 (x12) 1.15±0.05 0.55±0.05 (x12) 3 0.10 C (2X) 1 1.00 REF Pin #1 Corner 1.28 Pin #1 Identifier 3.40 TOP VIEW BOTTOM VIEW RECOMMENDED LAND PATTERN DOC-01924 0.10 C 0.10 0.05 0.75±0.05 0.05 C C A B C ALL FEATURES SEATING PLANE 0.203 0.05 C SIDE VIEW Note: Pin 1 identification tab is electrically connected to the exposed ground paddle. Figure 16. Top Marking Specifications = Pin 1 designator 43205 YYWW ZZZZZZ 43205 = Five digit part number YYWW = Date Code, last two digits of the year and work week ZZZZZZ = Maximum six characters of the assembly lot code DOC-51207 ©2017, 2019 pSemi Corp. All rights reserved. Page 10 of 11 Document No. DOC-85387-2 │ UltraCMOS® RFIC Solutions PE43205 Product Specification Figure 7. Tape and Reel Drawing Tape Feed Direction Pin 1 Top of Device Device Orientation in Tape Table 6. Ordering Information Ordering Code Description Package Shipping Method PE43205B-Z PE43205 Digital step attenuator Green 12-lead 3x3 mm QFN 3000 units/T&R EK43205-2 PE43205 Evaluation kit Evaluation kit 1/Box Sales Contact and Information For sales and contact information please visit www.psemi.com. Document No. DOC-85387-2 │ www.psemi.com ©2017, 2019 pSemi Corp. All rights reserved. Page 11 of 11