Product Specification
PE64904
UltraCMOS® Digitally Tunable Capacitor
(DTC) 100 - 3000 MHz
Product Description
The PE64904 is a DuNE™-enhanced Digitally Tunable
Capacitor (DTC) based on Peregrine’s UltraCMOS®
technology. DTC products provide a monolithically
integrated impedance tuning solution for demanding RF
applications.
Features
The PE64904 offers high RF power handling and
ruggedness, while meeting challenging harmonic and
linearity requirements.
This highly versatile product can be used in series or shunt
configurations to support a wide variety of tuning circuit
topologies.
The device is controlled through the widely supported
3-wire (SPI compatible) interface. All decoding and biasing
is integrated on-chip and no external bypassing or filtering
components are required.
Peregrine’s DuNE™ technology enables excellent linearity
and exceptional harmonic performance. DuNE devices
deliver performance superior to GaAs devices with the
economy and integration of conventional CMOS.
Figure 1. Functional Block Diagram
RF-
RF+
ESD
Serial
Interface
3-wire (SPI compatible) Serial Interface
with built-in bias voltage generation and
ESD protection
DuNE™-enhanced UltraCMOS® device
5-bit 32-state Digitally Tunable Capacitor
Series configuration C = 0.60 - 4.60 pF
(7.7:1 tuning ratio) in discrete 129 fF steps
Shunt configuration C = 1.14 - 5.10 pF
(4.6:1 tuning ratio) in discrete 129 fF steps
High RF Power Handling (up to 38 dBm,
30 Vpk RF) and High Linearity
Wide power supply range (2.3 to 3.6V)
and low current consumption
(typ. 140 μA at 2.6V)
Excellent 1.5 kV HBM ESD tolerance
on all pins
2 x 2 x 0.45 mm QFN package
Applications include:
Tunable Filter Networks
Tunable Antennas
RFID
Tunable Matching Networks
Phase Shifters
Wireless Communications
Figure 2. Package Type
10L 2 x 2 x 0.45 mm QFN package
ESD
CMOS Control
Driver and ESD
71-0066-01
DOC-87399-1
©2018 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 11
PE64904
Product Specification
Table 1. Electrical Specifications @ 25°C, VDD = 2.6V
Parameter
Operating Frequency Range
Configuration
Condition
Both
Min
Typ
100
Max
Units
3000
MHz
Minimum Capacitance
Series
Shunt
State = 00000, 100 MHz (RF+ to RF-)
State = 00000, 100 MHz (RF+ to Grounded RF-)
0.49
0.90
0.60
1.10
0.71
1.30
pF
Maximum Capacitance
Series
Shunt
State = 11111, 100 MHz (RF+ to RF-)
State = 11111, 100 MHz (RF+ to Grounded RF-)
3.78
4.19
4.60
5.10
5.45
6.00
pF
Parasitic Capacitance
Series
All States, 100 MHz (RF+ to GND, RF- to GND)
Tuning Ratio
Series
Shunt
100 MHz
100 MHz
7.7:1
4.6:1
5 bits (32 states), constant step size (100 MHz)
0.129
pF
1.40
1.33
Ω
Step Size
Both
0.5
Equivalent Series Resistance
Series
State = 00000
State = 11111
Quality Factor (Cmin)1
Shunt
100 MHz, with Ls removed
1 GHz, with Ls removed
2 GHz, with Ls removed
3 GHz, with Ls removed
10
35
32
25
Quality Factor (Cmax)1
Shunt
100 MHz, with Ls removed
1 GHz, with Ls removed
2 GHz, with Ls removed
3 GHz, with Ls removed
27
25
11
6
Self Resonant Frequency
Shunt
State 00000
State 11111
7.5
3.1
Harmonics (2fo)2
Harmonics (3fo)
2
pF
GHz
100 MHz - 3 GHz
-36
dBm
100 MHz - 3 GHz
-36
dBm
Series
Input Intercept Point (2nd Order)
Series
100 MHz - 3 GHz, +18 dBm per tone, 1 MHz Spacing
105
dBm
Input Intercept Point (3rd Order)
Series
100 MHz - 3 GHz, +18 dBm per tone, 1 MHz Spacing
65
dBm
Switching Time3, 4
Both
50% CTRL to 10/90% delta capacitance between any two
states
12
µs
Start-up Time3
Both
Time from VDD within specification to all performances within
specification
100
µs
Wake-up Time3, 4
Both
State change from standby mode to RF state to all performances within specification
100
µs
Notes: 1. Q for a Shunt DTC based on a Series RLC equivalent circuit.
Q = XC/R = (X-XL)/R, where X = XL+XC , XL = 2*pi*f*L, XC = -1/(2*pi*f*C), which is equal to removing the effect of parasitic inductance L S.
2. In series or shunt between 50 Ω ports. Pulsed RF input with 4620 µs period, 50% duty cycle, measured per 3GPP TS 45.005.
3. DC path to ground at RF+ and RF- must be provided to achieve specified performance.
4. State change activated on falling edge of SEN following data word.
©2018 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 11
DOC-87399-1
PE64904
Product Specification
Figure 3. Pin Configuration (Top View)
Table 4. Absolute Maximum Ratings
Pin 1
Symbol
GND
10
1
RF-
VDD
9
VI
RF+
VESD
RF-
2
8
RF+
DGND
3
7
SDA
VDD
4
6
SEN
5
Max
Units
Power supply voltage
-0.3
4.0
V
Voltage on any DC input
-0.3
4.0
V
1500
V
ESD Voltage (HBM, MIL_STD
883 Method 3015.7)
Electrostatic Discharge (ESD) Precautions
Table 2. Pin Descriptions
Pin Name
Min
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted
to the limits in the Operating Ranges table.
Operation between operating range maximum and
absolute maximum for extended periods may reduce
reliability.
SCL
Pin #
Parameter/Conditions
When handling this UltraCMOS® device, observe
the same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Description
1
1
RF-
Negative RF Port
2
RF-
Negative RF Port1
3
DGND
Ground
Power supply pin
4
VDD
5
SCL
Serial interface Clock input
6
SEN
Serial Interface Latch Enable Input
7
SDA
Serial interface Data input
8
RF+
Positive RF Port1
9
RF+
Positive RF Port1
10
GND
RF Ground
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS®
devices are immune to latch-up.
Note 1: Pins 1-2 and 8-9 must be tied together on PCB for optimal performance.
Moisture Sensitivity Level
Table 3. Operating Ranges
Parameter
Min
Typ
Max
2.3
2.6
3.6
V
IDD Power Supply Current (VDD = 2.6V)
140
200
µA
IDD Standby Current (VDD = 2.6V)
25
VDD Supply Voltage
Units
The Moisture Sensitivity Level rating for the
PE64904 in the 10-lead 2 x 2 x 0.45 mm QFN
package is MSL1.
µA
VIH Control Voltage High
1.2
1.8
3.6
V
VIL Control Voltage Low
0
0
0.57
V
+34
+32
dBm
dBm
30
30
30
Vpk
Vpk
Vpk
RF Input Power (50Ω)1
698 - 915 MHz
1710 -1910 MHz
Peak Operating RF Voltage2
VP to VM
VP to RFGND
VM to RFGND
TOP Operating Temperature Range
-40
+85
°C
TST Storage Temperature Range
-65
+150
°C
Notes: 1. Maximum Power Available from 50Ω Source. Pulsed RF input with
4620 µS period, 50% duty cycle, measured per 3GPP TS 45.005.
2. Node voltages defined per Equivalent Circuit Model Schematic
(Figure 18). When DTC is used as a part of reactive network, impedance
transformation may cause the internal RF voltages (VP, VM) to exceed Peak
Operating RF Voltage even with specified RF Input Power Levels. For
operation above about +20 dBm (100 mW), the complete RF circuit must
be simulated using actual input power and load conditions, and internal
node voltages (VP, VM in Figure 18) monitored to not exceed 30 Vpk.
DOC-87399-1
©2018 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 11
PE64904
Product Specification
Performance Plots @ 25°C and 2.6V unless otherwise specified
Figure 4. Measured Shunt C (@ 100 MHz) vs.
State (temperature)
Figure 5. Measured Shunt S11 (major states)
Measured Shunt C vs. State (Temperature)
5.5
5.0
Capacitance (pF)
10
C (pF) at +85C
C (pF) at +25C
C (pF) at -40C
Delta C (%) at +85C
Delta C (%) at -40C
9
8
4.5
7
4.0
6
3.5
5
3.0
4
2.5
3
2.0
2
1.5
1
1.0
0
0.5
-1
0.0
-2
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
Delta C (%), Relative to C at +25C
6.0
32
State
Figure 7. Measured Series S11/S22 (major states)
Figure 6. Measured Step Size vs State
(frequency)
1048
100 MHz
1000 MHz
917
2000 MHz
2500 MHz
786
655
Step Size (fF)
524
393
262
131
0
-131
-262
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
State
Figure 8. Measured Shunt C vs.
Frequency
(major states)
Measured Shunt C vs Frequency (major states)
Figure 9. Measured Series S21 vs. Frequency
(major states)
20.0
17.5
C0
C1
C2
C4
C8
C16
C31
15.0
Capacitance (pF)
12.5
10.0
7.5
5.0
2.5
0.0
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
Frequency (GHz)
©2018 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 11
DOC-87399-1
PE64904
Product Specification
Figure 10. Measured Shunt Q vs.
Frequency
(major states)
Measured Shunt Q vs Frequency (major states)
Figure 11. Measured Shunt Q (state 0) vs.
Frequency (temperature)
60
Measured Shunt Q (State 0) vs Frequency (Temperature)
60
50
Q (C0) at +85C
+85C
Q0
Q1
50
Q2
40
Q (C0) at -40C
+25C
Q4
35
Delta Q (%) at
at +85C
+85C
Q8
40
45
Q (C0) at +25C
-40C
50
40
Q16
30
Delta Q (%) at
at -40C
-40C
25
30
Q
Q
Q31
30
20
20
10
10
10
5
0
-5
0
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
0
0.00
3.00
Frequency [GHz]
-10
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
Frequency (GHz)
Figure 12. Measured Shunt Q (state 31) vs.
Frequency (temperature)
60
75
70
Q (C31) at +85C
65
50
60
Q (C0) at -40C
55
50
Q (C0) at +25C
40
45
Delta Q (%) at +85C
40
Q
35
30
Delta Q (%) at -40C
30
25
15
10
5
10
0
-5
-10
0
0.00
-15
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
Delta Q (%) Relative to 25C
20
20
3.00
Frequency (GHz)
DOC-87399-1
©2018 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 11
Delta Q (%) Relative to 25C
15
20
PE64904
Product Specification
Operation at Frequencies Below 100 MHz
The PE64904 may be operated below the
100 MHz specified minimum operating frequency.
The total capacitance and peak operating RF
voltage are de-rated down to 1 MHz. Figure 13
shows the total shunt capacitance from 1 MHz
through 100 MHz. As seen in Figure 14, the
maximum RF voltage that can be placed across
the RF terminals or across either RF terminal to
Ground is de-rated as a function of frequency.
Note: Table 1 performance specifications are not guaranteed below 100 MHz.
Figures 13, 14, and 15 reflect performance of a typical PE64904.
Figure 14. Voltage Derating vs. Frequency
(1 MHz - 100 MHz)
Figure 13. Measured Shunt C vs. Frequency
(major states, 1 MHz - 100 MHz)
20.0
17.5
15.0
30
25
Vmax RF (V)
12.5
Capacitance (pF)
35
C0
C1
C2
C4
C8
C16
C31
10.0
7.5
20
15
10
5.0
5
2.5
0.0
0
10
20
30
40
50
60
70
80
90
100
Frequency (MHz)
0
0
20
40
60
Frequency (MHz)
80
100
Figure 15. Measured Shunt Q vs. Frequency
(major states, 1 MHz - 100 MHz)
35
C0
C1
C2
C4
C8
C16
C31
30
Quality Factor
25
20
15
10
5
0
0
10
20
30
40
50
60
70
80
90
100
Frequency (MHz)
©2018 Peregrine Semiconductor Corp. All rights reserved.
Page 6 of 11
DOC-87399-1
PE64904
Product Specification
Serial Interface Operation and Sharing
More than 1 DTC can be controlled by one interface by
utilizing a dedicated enable (SEN) line for each DTC.
SDA, SCL, and VDD lines may be shared as shown in
Figure 17. Dedicated SEN lines act as a chip select such
that each DTC will only respond to serial transactions
intended for them. This makes each DTC change states
sequentially as they are programmed.
The PE64904 is controlled by a three wire SPIcompatible interface. As shown in Figure 16, the serial
master initiates the start of a telegram by driving the
SEN (Serial Enable) line high. Each bit of the 8-bit
telegram is clocked in on the rising edge of the SCL
(Serial Clock) line. SDA bits are clocked by most
significant bit (MSB) first, as shown in Table 5 and
Figure 16. Transactions on SDA (Serial Data) are
allowed on the falling edge of SCL. The DTC activates
the data on the falling edge of SEN. The DTC does not
count how many bits are clocked and only maintains
the last 8 bits it received.
Alternatively, a dedicated SDA line with common SEN
can be used. This allows all DTCs to change states
simultaneously, but requires all DTCs to be programmed
even if the state is not changed.
Figure 16. Serial Interface Timing Diagram (oscilloscope view)
tEPW
tESU
tDSU tDHD
tR
b5
b4
tF
1/fCLK
tEHD
SEN
SCL
SDA
DTC Data
b7
b0
b6
Dm-2
b6
0
0
MSB
(first in)
b5
STB
1
b2
b1
b0
Dm-1
Table 5. Register Map
b7
b3
Dm
Figure 17. Recommended Bus Sharing
b4
b3
b2
b1
b0
d4
d3
d2
d1
d0
Note 1: The DTC is active when low (set to 0) and in
low-current stand-by mode when high (set to 1)
DTC 1
RF+
VDD
LSB
(last in)
Table 6. Serial Interface Timing Characteristics
SDA
SCL
SEN1
SEN2
VDD
SDA
SCL
SEN
Symbol
fCLK
tR
tF
Parameter
Min
RF-
Max
Units
Serial Clock Frequency
26
MHz
SCL, SDA, SEN Rise Time
6.5
ns
SCL, SDA, SEN Fall Time
6.5
ns
DTC 2
RF+
VDD
SDA
SCL
tESU
SEN rising edge to SCL rising
edge
19.2
ns
tEHD
SCL rising edge to SEN falling
edge
19.2
ns
SEN
DGND
tDSU
SDA valid to SCL rising edge
13.2
ns
tDHD
SDA valid after SCL rising edge
13.2
ns
tEOW
SEN falling edge to SEN rising
edge
38.4
ns
DOC-87399-1
GND
DGND
VDD = 2.6V, -40°C < TA < +85°C, unless otherwise specified
GND
RF-
©2018 Peregrine Semiconductor Corp. All rights reserved.
Page 7 of 11
PE64904
Product Specification
Equivalent Circuit Model Description
The DTC Equivalent Circuit Model includes all
parasitic elements and is accurate in both Series
and Shunt configurations, reflecting physical circuit
behavior accurately and providing very close
correlation to measured data. It can easily be used
in circuit simulation programs. Most parameters are
state independent, and simple equations are
provided for the state dependent parameters.
The Tuning Core capacitance CS represents
capacitance between RF+ and RF- ports. It is
linearly proportional to state (0 to 31 in decimal) in
a discrete fashion. The Series Tuning Ratio is
defined as CSmax/CSmin.
CP represents the circuit and package parasitics
from RF ports to GND. In Shunt configuration the
total capacitance of the DTC is higher due to
parallel combination of CP and CS. In Series
configuration, CS and CP do not add in parallel and
the DTC appears as an impedance transformation
network.
Figure 18. Equivalent Circuit Model Schematic
LS
LS
RS
CS
VM
VP
RF+
RFCP
CP
RP2
RP2
RP1
RP1
RFGND
Table 8. Equivalent Circuit Model Parameters
Variable
Equation (state = 0, 1, 2…31)
Units
CS
0.129*state + 0.600
pF
RS
20/(state+20/(state+0.7)) + 0.7
Ω
RP1
7
Ω
RP2
10
kΩ
CP
0.5
pF
LS
0.27
nH
Table 9. Equivalent Circuit Data
State
Parasitic inductance due to circuit and package is
modeled as LS and causes the apparent
capacitance of the DTC to increase with frequency
until it reaches Self Resonant Frequency (SRF).
The value of SRF depends on state and is
approximately inversely proportional to the square
root of capacitance.
The overall dissipative losses of the DTC are
modeled by RS, RP1 and RP2 resistors. The
parameter RS represents the Equivalent Series
Resistance (ESR) of the tuning core and is
dependent on state. RP1 and RP2 represent losses
due to the parasitic and biasing networks, and are
state-independent.
Table 7. Maximum Operating RF Voltage
Condition
Limit
VP to VM
30 Vpk
VP to RFGND
30 Vpk
VM to RFGND
30 Vpk
©2018 Peregrine Semiconductor Corp. All rights reserved.
Page 8 of 11
Binary
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
DTC Core
Decimal
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Cs [pF]
0.60
0.73
0.86
0.99
1.12
1.25
1.37
1.50
1.63
1.76
1.89
2.02
2.15
2.28
2.41
2.54
2.66
2.79
2.92
3.05
3.18
3.31
3.44
3.57
3.70
3.83
3.95
4.08
4.21
4.34
4.47
4.60
Rs [Ω ]
1.40
2.27
2.83
3.08
3.12
3.05
2.93
2.78
2.64
2.51
2.39
2.27
2.17
2.08
2.00
1.93
1.86
1.80
1.75
1.70
1.65
1.61
1.57
1.54
1.51
1.48
1.45
1.42
1.40
1.37
1.35
1.33
DOC-87399-1
PE64904
Product Specification
Layout Recommendations
Evaluation Board
For optimal results, place a ground fill directly under
the DTC package on the PCB. Layout isolation is
desired between all control and RF lines. When
using the DTC in a shunt configuration, it is
important to make sure the RF-pin is solidly
grounded to a filled ground plane. Ground traces
should be as short as possible to minimize
inductance. A continuous ground plane is preferred
on the top layer of the PCB. When multiple DTCs
are used together, the physical distance between
them should be minimized and the connection
should be as wide as possible to minimize series
parasitic inductance.
The 101-0597 Evaluation Board (EVB) was designed
for accurate measurement of the DTC impedance
and loss. Two configurations are available: 1 Port
Shunt (J3) and 2 Port Series (J4, J5). Three
calibration standards are provided. The open (J2)
and short (J1) standards (104 ps delay) are used for
performing port extensions and accounting for
electrical length and transmission line loss. The Thru
(J9, J10) standard can be used to estimate PCB
transmission line losses for scalar de-embedding of
the 2 Port Series configuration (J4, J5).
Figure 19. Recommended Schematic of
Multiple DTCs
The board consists of a 4 layer stack with 2 outer
layers made of Rogers 4350B (εr = 3.48) and 2 inner
layers of FR4 (εr = 4.80). The total thickness of this
board is 62 mils (1.57 mm). The inner layers provide
a ground plane for the transmission lines. Each
transmission line is designed using a coplanar
waveguide with ground plane (CPWG) model using
a trace width of 32 mils (0.813 mm), gap of 15 mils
(0.381 mm), and a metal thickness of 1.4 mils
(0.051 mm).
Figure 21. Evaluation Board Layout
Figure 20. Recommended Layout of Multiple DTCs
101-0597
DOC-87399-1
©2018 Peregrine Semiconductor Corp. All rights reserved.
Page 9 of 11
PE64904
Product Specification
Figure 22. Package Drawing
10-lead 2 x 2 x 0.45 mm
19-2002
Figure 23. Marking Specifications
PPZZ
YWW
Marking Spec
Symbol
Package
Marking
PP
CG
ZZ
00-99
Y
0-9
WW
01-53
Definition
Part number marking for PE64904
Last two digits of lot code
Last digit of year, starting from 2009
(0 for 2010, 1 for 2011, etc)
Work week
17-0112
©2018 Peregrine Semiconductor Corp. All rights reserved.
Page 10 of 11
DOC-87399-1
PE64904
Product Specification
Figure 24. Tape and Reel Specifications
10-lead 2 x 2 x 0.45 mm
Tape Feed Direction
Pin 1
Top of
Device
Device Orientation in Tape
Table 9. Ordering Information
Order Code
Package
Description
Shipping Method
PE64904C-Z
10-lead QFN 2 x 2 x 0.45 mm
Package Part in Tape and Reel
3000 units/T&R
EK64904-13
Evaluation Kit
Evaluation Kit
1 Set/Box
Sales Contact and Information
For sales and contact information please visit www.psemi.com.
Advance Information: The product is in a formative or design stage. The datasheet contains
design target specifications for product development. Specifications and features may change in
any manner without notice. Preliminary Specification: The datasheet contains preliminary data.
Additional data may be added at a later date. Peregrine reserves the right to change
specifications at any time without notice in order to supply the best possible product.
Product Specification: The datasheet contains final data. In the event Peregrine decides to
change the specifications, Peregrine will notify customers of the intended changes by issuing a
CNF (Customer Notification Form).
The information in this document is believed to be reliable. However, Peregrine assumes no
liability for the use of this information. Use shall be entirely at the user’s own risk.
DOC-87399-1
©2018 Peregrine Semiconductor Corp. All rights reserved.
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