74ABT853

Philips Semiconductors Product specification 8-bit transceiver with 9-bit parity checker/ generator and flag latch (3-State) 74ABT853 FEATURES • Low static and dynamic power dissipation with high speed and high output drive The 74ABT853 is an octal transceiver with a parity generator/checker and is intended for bus–oriented applications. When Output Enable A (OEA) is High, it will place the A outputs in a high impedance state. Output Enable B (OEB) controls the B outputs in the same way. The parity generator creates an odd parity output (PARITY) when OEB is Low. When OEA is Low, the parity of the B port, including the PARITY input, is checked for odd parity. When an error is detected, the error data is sent to the input of a latch. The error data can then be passed, stored, cleared, or sampled depending on the ENABLE and CLEAR control signals. If both OEA and OEB are Low, data will flow from the A bus to the B bus and the part is forced into an error condition which creates an inverted PARITY output. This error condition can be used by the designer for system diagnostics. • Open-collector ERROR output • Output capability: +64mA/–32mA • Latch-up protection exceeds 500mA per Jedec Std 17 • ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model • Power-up 3-State • Live insertion/extraction permitted DESCRIPTION The 74ABT853 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. QUICK REFERENCE DATA SYMBOL tPLH tPHL tPLH tPHL CIN CI/O ICCZ PARAMETER Propagation delay An to Bn or Bn to An Propagation delay An to PARITY Input capacitance I/O capacitance Total supply current CONDITIONS Tamb = 25°C; GND = 0V CL = 50pF; VCC = 5V CL = 50pF; VCC = 5V VI = 0V or VCC Outputs disabled; VO = 0V or VCC Outputs disabled; VCC =5.5V TYPICAL 3.4 7.4 4 7 50 UNIT ns ns pF pF µA ORDERING INFORMATION PACKAGES 24-Pin Plastic DIP 24-Pin plastic SO 24-Pin Plastic SSOP Type II 24-Pin Plastic TSSOP Type I TEMPERATURE RANGE –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C OUTSIDE NORTH AMERICA 74ABT853 N 74ABT853 D 74ABT853 DB 74ABT853 PW NORTH AMERICA 74ABT853 N 74ABT853 D 74ABT853 DB 74ABT853PW DH DWG NUMBER SOT222-1 SOT137-1 SOT340-1 SOT355-1 PIN CONFIGURATION LOGIC SYMBOL OEA 1 24 V CC 23 B0 22 B1 2 3 4 5 6 7 8 9 21 B2 20 B3 19 B4 18 B5 17 B6 16 B7 15 PARITY 14 OEB 13 ENABLE TOP VIEW 23 22 21 20 19 18 17 16 14 1 11 13 A0 A1 A2 A3 A4 A5 A6 A7 OEB OEA CLEAR ENABLE B0 B1 B2 B3 B4 B5 B6 B7 PARITY ERROR 15 10 A0 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6 8 A7 9 ERROR 10 CLEAR 11 GND 12 SA00262 SA00263 1995 Sep 06 1 853-1672 15702 Philips Semiconductors Product specification 8-bit transceiver with 9-bit parity checker/ generator and flag latch (3-State) 74ABT853 PIN DESCRIPTION SYMBOL A0 – A7 B0 – B7 OEA OEB PARITY ERROR CLEAR ENABLE GND VCC PIN NUMBER 2, 3, 4, 5, 6, 7, 8, 9 23, 22, 21, 20, 19, 18, 17, 16 1 14 15 10 11 13 12 24 NAME AND FUNCTION A port 3–State inputs/outputs B port 3–State inputs/outputs Enables the A outputs when Low Enables the B outputs when Low Parity output/input Error output (open collector) Clears the error flag register when Low Enable input (active-Low) Ground (0V) Positive supply voltage FUNCTION TABLE INPUTS MODE A data to B bus and generate odd parity output B data to A bus and check for parity error1 A bus and B bus disabled2 OEB L H H L OEA H L H L An Σ OF HIGHS Odd Even (output) X Odd Even Bn + PARITY Σ OF HIGHS (output) X X (output) An (input) Bn Z (input) OUTPUTS Bn An (input) Z An PARITY L H (input) Z H L A data to B bus and generate inverted parity output NOTES: 1. Error checking is detailed in the Error Flag Function Table below. 2. When ENABLE is Low, ERROR is Low if the sum of A inputs is even or ERROR is High if the sum of A inputs is odd. ERROR FLAG FUNCTION TABLE INPUTS MODE Pass ENABLE L CLEAR L Bn + PARITY Σ OF HIGHS Odd Even Odd Even X X X INTERNAL NODE POINT ”P” H L H L X X X OUTPUT PRE–STATE ERRORn–1 X H X L X L H ERROR OUTPUT H L H L L H L H Sample Clear Store H L X Z = = = = L H H H L H High voltage level steady state Low voltage level steady state Don’t care High impedance ”off” state 1995 Sep 06 2 Philips Semiconductors Product specification 8-bit transceiver with 9-bit parity checker/ generator and flag latch (3-State) 74ABT853 LOGIC DIAGRAM 8 A0 – A7 8 B0 – B7 8 OEB PARITY OEA 8 8 MUX 9–bit Odd Parity Tree ”P” A } } B 9 Sel A/B ERROR ENABLE CLEAR SA00264 ABSOLUTE MAXIMUM RATINGS1, 2 SYMBOL VCC IIK VI IOK VOUT IOUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 VO < 0 output in Off or High state output in Low state VI < 0 CONDITIONS RATING –0.5 to +7.0 –18 –1.2 to +7.0 –50 –0.5 to +5.5 128 –65 to 150 UNIT V mA V mA V mA °C DC output diode current DC output voltage3 DC output current Storage temperature range NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1995 Sep 06 3 Philips Semiconductors Product specification 8-bit transceiver with 9-bit parity checker/ generator and flag latch (3-State) 74ABT853 RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER MIN VCC VI VIH VIL IOH IOL ∆t/∆v Tamb DC supply voltage Input voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature range 0 –40 4.5 0 2.0 0.8 –32 64 5 +85 LIMITS MAX 5.5 VCC V V V V mA mA ns/V °C UNIT DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25°C Min VIK Input clamp voltage VCC = 4.5V; IIK = –18mA VCC = 4.5V; IOH = –3mA; VI = VIL or VIH VOH High–level output voltage All outputs except ERROR VCC = 5.0V; IOH = –3mA; VI = VIL or VIH VCC = 4.5V; IOH = –32mA; VI = VIL or VIH VOL II IOFF IPU/PD IIH + IOZH IIL + IOZL ICEX IO ICCH ICCL ICCZ Quiescent supply current Low-level output voltage Input leakage current Control pins Data pins VCC = 4.5V; IOL = 64mA; VI = VIL or VIH VCC = 5.5V; VI = GND or 5.5V VCC = 5.5V; VI = GND or 5.5V VCC = 0.0V; VO or VI ≤ 4.5V VCC = 2.1V; VO = 0.5V; VI = GND or VCC; V OE = Don’t care VCC = 5.5V; VO = 2.7V; VI = VIL or VIH VCC = 5.5V; VO = 0.5V; VI = VIL or VIH VCC = 5.5V; VO = 5.5V; VI = GND or VCC VCC = 5.5V; VO = 2.5V VCC = 5.5V; Outputs High, VI = GND or VCC VCC = 5.5V; Outputs Low, VI = GND or VCC VCC = 5.5V; Outputs 3-State; VI = GND or VCC Outputs enabled, one input at 3.4V, other inputs at VCC or GND; VCC = 5.5V ∆ICC Additional supply current per input pin2 Outputs 3-State, one data input at 3.4V, other inputs at VCC or GND; VCC = 5.5V Outputs 3-State, one enable input at 3.4V, other inputs at VCC or GND; VCC = 5.5V –50 2.5 3.0 2.0 Typ –0.9 3.5 4.0 2.6 0.42 ±0.01 ±5 ±5.0 ±5.0 5.0 –5.0 5.0 –100 0.5 25 0.5 0.5 0.01 0.5 0.55 ±1.0 ±100 ±100 ±50 50 –50 50 –180 250 38 50 1.5 50 1.5 –50 Max –1.2 2.5 3.0 2.0 0.55 ±1.0 ±100 ±100 ±50 50 –50 50 –180 250 38 50 1.5 50 1.5 Tamb = –40°C to +85°C Min Max –1.2 V V V V V µA µA µA µA µA µA µA mA µA mA µA mA µA mA UNIT Power-off leakage current Power-up/down 3-State output current3 3-State output High current 3-State output Low current Output high leakage current Output current1 NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. This parameter is valid for any VCC between 0V and 2.1V, with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10%, a transition time of up to 100µsec is permitted. The ERROR output pin 10 is not included in this spec due to the open collector design. 1995 Sep 06 4 Philips Semiconductors Product specification 8-bit transceiver with 9-bit parity checker/ generator and flag latch (3-State) 74ABT853 AC CHARACTERISTICS GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER WAVEFORMS Min tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation delay An to Bn or Bn to An Propagation delay An to PARITY Propagation delay OEA to PARITY Propagation delay CLEAR to ERROR Propagation delay ENABLE to ERROR Propagation delay Bn or PARITY to ERROR Output enable time OEA to An or OEB to Bn, PARITY Output disable time OEA to An or OEB to Bn, PARITY 4 1, 4 1, 4 3 4 1, 4 2, 5 2, 5 1.2 1.0 2.1 2.5 1.8 2.3 1.0 1.8 1.8 2.0 3.0 1.0 2.1 3.1 3.2 Tamb = +25oC VCC = +5.0V Typ 3.4 2.6 7.4 7.4 6.6 6.7 3.6 3.8 4.5 7.9 9.0 3.2 4.1 5.1 5.6 Max 4.8 4.0 9.5 9.7 8.5 8.6 5.5 5.1 5.8 10.1 11.5 5.1 5.8 7.3 7.2 Tamb = –40 to +85oC VCC = +5.0V ±10% Min 1.2 1.0 2.1 2.5 1.8 2.3 1.0 1.8 1.8 2.0 3.0 1.0 2.1 3.1 3.2 Max 5.3 4.5 11.2 11.0 10.5 10.0 6.2 6.0 6.6 11.7 12.8 6.2 6.7 7.9 8.1 ns ns ns ns ns ns ns ns UNIT AC SETUP REQUIREMENTS GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER WAVEFORMS Tamb = VCC = +5.0V MIN ts(H) ts(L) th(H) th(L) ts(H) th(L) tw(L) tw(L) Setup time, High or Low Bn or PARITY to ENABLE Hold time, High or Low Bn or PARITY to ENABLE Setup time, High CLEAR to ENABLE Hold time, Low CLEAR to ENABLE Pulse width, Low CLEAR Pulse width, Low ENABLE 6 6 6 6 3 6 8.5 8.5 0.0 0.0 2.0 3.0 3.5 4.0 +25oC TYP 6.5 3.6 –3.4 –6.3 –1.6 1.8 1.0 2.5 Tamb = –40 to +85oC VCC = +5.0V ±10% MIN 8.5 8.5 0.0 0.0 2.0 3.0 3.5 4.0 ns ns ns ns ns ns UNIT 1995 Sep 06 5 Philips Semiconductors Product specification 8-bit transceiver with 9-bit parity checker/ generator and flag latch (3-State) 74ABT853 AC WAVEFORMS VM = 1.5V, VIN = GND to 3.0V INPUT VM tPHL VM tPLH INPUT VM VM tPLH OUTPUT VM VM OUTPUT VM tPHL SA00216 VM Waveform 1. Propagation Delay For Inverting Output SA00023 Waveform 4. Propagation Delay For Non-Inverting Output OEA, OEB VM tPZH VM tPHZ VOH –0.3V OUTPUT VM 0V OEA, OEB VM tPZL VM tPLZ SA00238 OUTPUT VM VOL +0.3V 0V Waveform 2. 3-State Output Enable Time to High Level and Output Disable Time from High Level SA00239 Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level tw(L) ERROR CLEAR, Bn, PARITY VM tPLH SA00265 ENABLE Waveform 3. CLEAR Pulse Width and CLEAR to ERROR Delay NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SA00266 Waveform 6. Data Setup and Hold Times and ENABLE Pulse Width 1995 Sep 06 6 ÉÉÉÉ É ÉÉÉÉÉÉÉÉÉÉ ÉÉÉ É ÉÉÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ VM VM VM VM ts(H) th(H) ts(L) th(L) tw(L) VM VM VM CLEAR VM VM Philips Semiconductors Product specification 8-bit transceiver with 9-bit parity checker/ generator and flag latch (3-State) 74ABT853 TYPICAL PROPAGATION DELAYS VERSUS LOAD FOR OPEN COLLECTOR OUTPUTS 18 16 14 12 10 8 6 4 tPHL 2 0 0 100 200 300 Load resistor (Ω) NOTE: When using Open-Collector parts, the value of the pull–up resistor greatly affects the value of the tPLH. For example, changing the specified pull-up resistor value from 500Ω to 100Ω will improve the tPLH over 300% with only a slight change in the tPHL. However, if the value of the pull-up resistor is changed, the user must make certain that the total IOL current through the resistor and the total IIL’s of the receivers does not exceed the IOL maximum specification. 400 500 600 Propagation delay (ns) tPLH SA00241 TEST CIRCUIT AND WAVEFORM VCC VX VIN PULSE GENERATOR RT D.U.T CL RL VOUT RX 90% NEGATIVE PULSE VM 10% tTHL (tF) tTLH (tR) 90% tW VM 10% 90% AMP (V) 0V tTLH (tR) tTHL (tF) 90% VM 10% tW 0V AMP (V) Test Circuit for 3-State Outputs POSITIVE PULSE 10% VM SWITCH POSITION TEST tPLZ tPZL All other SWITCH closed closed open LOAD VALUES OUTPUT ERROR All other RX VX 100Ω VCC 500Ω 7.0V VM = 1.5V Input Pulse Definition DEFINITIONS RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. INPUT PULSE REQUIREMENTS FAMILY Amplitude 74ABT 3.0V Rep. Rate 1MHz tW 500ns tR 2.5ns tF 2.5ns SA00242 1995 Sep 06 7