74LVC2G125DC

INTEGRATED CIRCUITS DATA SHEET 74LVC2G125 Dual bus buffer/line driver; 3-state Product specification Supersedes data of 2004 Jan 09 2004 Sep 22 Philips Semiconductors Product specification Dual bus buffer/line driver; 3-state FEATURES • Wide supply voltage range from 1.65 V to 5.5 V • 5 V tolerant input/output for interfacing with 5 V logic • High noise immunity • Complies with JEDEC standard: – JESD8-7 (1.65 V to 1.95 V) – JESD8-5 (2.3 V to 2.7 V) – JESD8B/JESD36 (2.7 V to 3.6 V). • ESD protection: – HBM EIA/JESD22-A114-B exceeds 2000 V – MM EIA/JESD22-A115-A exceeds 200 V. • ±24 mA output drive (VCC = 3.0 V) • CMOS low power consumption • Latch-up performance exceeds 250 mA • Direct interface with TTL levels • Inputs accept voltages up to 5 V • Multiple package options • Specified from −40 °C to +85 °C and −40 °C to +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C. SYMBOL tPHL/tPLH PARAMETER CONDITIONS VCC = 2.5 V; CL = 30 pF; RL = 500 Ω VCC = 2.7 V; CL = 50 pF; RL = 500 Ω VCC = 3.3 V; CL = 50 pF; RL = 500 Ω VCC = 5.0 V; CL = 50 pF; RL = 500 Ω CI CPD input capacitance power dissipation capacitance per buffer output enabled; notes 1 and 2 output disabled; notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; ∑(CL × VCC2 × fo) = sum of outputs. 2. The condition is VI = GND to VCC. DESCRIPTION 74LVC2G125 The 74LVC2G125 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74LVC2G125 provides a dual non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (pin nOE). A HIGH-level at pin nOE causes the output to assume a high-impedance OFF-state. Schmitt-trigger action at all inputs makes the circuit highly tolerant for slower input rise and fall times. TYPICAL 3.7 2.5 2.7 2.3 1.9 2 18 5 ns ns ns ns ns UNIT propagation delay inputs nA to output nY VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ pF pF pF 2004 Sep 22 2 Philips Semiconductors Product specification Dual bus buffer/line driver; 3-state FUNCTION TABLE See note 1. INPUT nOE L L H Note 1. H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. ORDERING INFORMATION PACKAGE TYPE NUMBER 74LVC2G125DP 74LVC2G125DC 74LVC2G125GM PINNING PIN 1 2 3 4 5 6 7 8 1A 2Y GND 2A 1Y 2OE VCC SYMBOL 1OE data input data output ground (0 V) data input data output output enable input (active LOW) supply voltage DESCRIPTION output enable input (active LOW) TEMPERATURE RANGE −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C PINS 8 8 8 PACKAGE TSSOP8 VSSOP8 XSON8 MATERIAL plastic plastic plastic nA L H X 74LVC2G125 OUTPUT nY L H Z CODE SOT505-2 SOT765-1 SOT833-1 MARKING V125 V25 V25 2004 Sep 22 3 Philips Semiconductors Product specification Dual bus buffer/line driver; 3-state 74LVC2G125 125 1OE 1OE 1A 2Y GND 1 2 3 4 001aab738 1 8 VCC 8 7 VCC 2OE 1Y 2A 2Y 3 6 1Y 1A 2 7 2OE 125 6 5 GND 4 5 2A 001aab739 Transparent top view Fig.1 Pin configuration TSSOP8 and VSSOP8. Fig.2 Pin configuration XSON8. handbook, halfpage 2 1 5 7 1A 1OE 2A 2OE 1Y 6 2Y 3 MNA941 Fig.3 Logic symbol. 2004 Sep 22 4 Philips Semiconductors Product specification Dual bus buffer/line driver; 3-state RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VI VO PARAMETER supply voltage input voltage output voltage VCC = 1.65 V to 5.5 V; enable mode VCC = 1.65 V to 5.5 V; disable mode VCC = 0 V; Power-down mode Tamb tr, tf operating ambient temperature input rise and fall times VCC = 1.65 V to 2.7 V VCC = 2.7 V to 5.5 V CONDITIONS 0 0 0 0 −40 0 0 MIN. 1.65 74LVC2G125 MAX. 5.5 5.5 VCC 5.5 5.5 +125 20 10 V V V V V UNIT °C ns/V ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK VI IOK VO PARAMETER supply voltage input diode current input voltage output diode current output voltage VI < 0 V note 1 VO > VCC or VO < 0 V enable mode; notes 1 and 2 disable mode; notes 1 and 2 IO ICC, IGND Tstg Ptot Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. output source or sink current VCC or GND current storage temperature power dissipation Tamb = −40 °C to +125 °C VO = 0 V to VCC CONDITIONS − −0.5 − −0.5 −0.5 − − −65 − MIN. −0.5 MAX. +6.5 −50 +6.5 ±50 +6.5 +6.5 ±50 ±100 +150 300 V mA V mA V V mA mA °C mW UNIT VCC + 0.5 V Power-down mode; notes 1 and 2 −0.5 2004 Sep 22 5 Philips Semiconductors Product specification Dual bus buffer/line driver; 3-state DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = −40 °C to +85 °C; note 1 VIH HIGH-level input voltage 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VIL LOW-level input voltage 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA IO = 4 mA IO = 8 mA IO = 12 mA IO = 24 mA IO = 32 mA VOH HIGH-level output voltage VI = VIH or VIL IO = −100 µA IO = −4 mA IO = −8 mA IO = −12 mA IO = −24 mA IO = −32 mA ILI IOZ Ioff ICC ∆ICC input leakage current VI = 5.5 V or GND 3-state output OFF-state VI = VIH or VIL; current VO = 5.5 V or GND power OFF leakage current VI or VO = 5.5 V 1.65 to 5.5 1.65 2.3 2.7 3.0 4.5 5.5 3.6 0 5.5 2.3 to 5.5 VCC − 0.1 1.2 1.9 2.2 2.3 3.8 − − − − − − − − − − − ±0.1 ±0.1 ±0.1 0.1 5 1.65 to 5.5 1.65 2.3 2.7 3.0 4.5 − − − − − − − − − − − − 0.65 × VCC 1.7 2.0 0.7 × VCC − − − − − − − − − − − − VCC (V) MIN. TYP. 74LVC2G125 MAX. UNIT − − − − 0.35 × VCC 0.7 0.8 0.3 × VCC 0.1 0.45 0.3 0.4 0.55 0.55 − − − − − − ±5 ±10 ±10 10 500 V V V V V V V V V V V V V V V V V V V V µA µA µA µA µA quiescent supply current VI = VCC or GND; IO = 0 A additional quiescent supply current per pin VI = VCC − 0.6 V; IO = 0 A 2004 Sep 22 6 Philips Semiconductors Product specification Dual bus buffer/line driver; 3-state 74LVC2G125 TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = −40 °C to +125 °C VIH HIGH-level input voltage 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VIL LOW-level input voltage 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA IO = 4 mA IO = 8 mA IO = 12 mA IO = 24 mA IO = 32 mA VOH HIGH-level output voltage VI = VIH or VIL IO = −100 µA IO = −4 mA IO = −8 mA IO = −12 mA IO = −24 mA IO = −32 mA ILI IOZ Ioff ICC ∆ICC Note 1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. input leakage current VI = 5.5 V or GND 3-state output OFF-state VI = VIH or VIL; current VO = 5.5 V or GND power OFF leakage current VI or VO = 5.5 V 1.65 to 5.5 1.65 2.3 2.7 3.0 4.5 5.5 3.6 0 5.5 2.3 to 5.5 VCC − 0.1 0.95 1.7 1.9 2.0 3.4 − − − − − − − − − − − − − − − − − − − − − − ±20 ±20 ±20 40 5000 V V V V V V µA µA µA µA µA 1.65 to 5.5 1.65 2.3 2.7 3.0 4.5 − − − − − − − − − − − − 0.1 0.70 0.45 0.60 0.80 0.80 V V V V V V 0.65 × VCC 1.7 2.0 0.7 × VCC − − − − − − − − − − − − − − − − 0.35 × VCC 0.7 0.8 0.3 × VCC V V V V V V V V VCC (V) MIN. TYP. MAX. UNIT quiescent supply current VI = VCC or GND; IO = 0 A additional quiescent supply current per pin VI = VCC − 0.6 V; IO = 0 A 2004 Sep 22 7 Philips Semiconductors Product specification Dual bus buffer/line driver; 3-state AC CHARACTERISTICS GND = 0 V. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb = −40 °C to +85 °C; note 1 tPHL/tPLH propagation delay nA to nY see Figs 4 and 6 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 tPZH/tPZL 3-state output enable time nOE to nY see Figs 5 and 6 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 tPHZ/tPLZ 3-state output disable time nOE to nY see Figs 5 and 6 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 Tamb = −40 °C to +125 °C tPHL/tPLH propagation delay nA to nY see Figs 4 and 6 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 tPZH/tPZL 3-state output enable time nOE to nY see Figs 5 and 6 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 tPHZ/tPLZ 3-state output disable time nOE to nY see Figs 5 and 6 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 Note 1. All typical values are measured at Tamb = 25 °C. 1.0 0.5 1.0 0.5 0.5 1.5 1.0 1.5 0.5 0.5 1.0 0.5 1.0 1.0 0.5 − − − − − − − − − − − − − − − 1.0 0.5 1.0 0.5 0.5 1.5 1.0 1.5 0.5 0.5 1.0 0.5 1.0 1.0 0.5 VCC (V) MIN. 74LVC2G125 TYP. MAX. UNIT 3.7 2.5 2.7 2.3 1.9 4.3 2.8 3.3 2.4 2.0 3.5 1.8 2.7 2.7 1.8 9.1 4.8 4.8 4.3 3.7 9.9 5.6 5.7 4.7 3.8 11.6 5.8 4.8 4.6 3.4 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 11.4 6.0 6.0 5.5 4.6 12.4 7.0 7.1 5.9 4.8 14.1 7.6 6.2 5.9 4.6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2004 Sep 22 8 Philips Semiconductors Product specification Dual bus buffer/line driver; 3-state AC WAVEFORMS 74LVC2G125 handbook, halfpage VI VM GND tPHL VOH tPLH nA input nY output VOL VM MNA230 INPUT VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V VM 0.5 × VCC 0.5 × VCC 1.5 V 1.5 V 0.5 × VCC VCC VCC 2.7 V 2.7 V VCC VI tr = tf ≤ 2.0 ns ≤ 2.0 ns ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns VOL and VOH are typical output voltage drop that occur with the output load. Fig.4 The input (nA) to output (nY) propagation delays and the output transition times. 2004 Sep 22 9 Philips Semiconductors Product specification Dual bus buffer/line driver; 3-state 74LVC2G125 handbook, full pagewidth VI nOE input GND tPLZ VCC output LOW-to-OFF OFF-to-LOW VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled VY VM VM VX tPZH tPZL VM outputs disabled outputs enabled MNA362 INPUT VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V VM 0.5 × VCC 0.5 × VCC 1.5 V 1.5 V 0.5 × VCC VCC VCC 2.7 V 2.7 V VCC VI tr = tf ≤ 2.0 ns ≤ 2.0 ns ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns VX = VOL + 0.3 V at VCC ≥ 2.7 V; VX = VOL + 0.15 V at VCC < 2.7 V; VY = VOH − 0.3 V at VCC ≥ 2.7 V; VY = VOH − 0.15 V at VCC < 2.7 V. VOL and VOH are typical output voltage drop that occur with the output load. Fig.5 3-state enable and disable times. 2004 Sep 22 10 Philips Semiconductors Product specification Dual bus buffer/line driver; 3-state 74LVC2G125 VEXT VCC PULSE GENERATOR VI D.U.T. RT CL RL VO RL mna616 VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V VI VCC VCC 2.7 V 2.7 V VCC CL 30 pF 30 pF 50 pF 50 pF 50 pF RL 1 kΩ 500 Ω 500 Ω 500 Ω 500 Ω VEXT tPLH/tPHL tPZH/tPHZ open open open open open GND GND GND GND GND tPZL/tPLZ 2 × VCC 2 × VCC 6V 6V 2 × VCC Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.6 Load circuitry for switching times. 2004 Sep 22 11 Philips Semiconductors Product specification Dual bus buffer/line driver; 3-state PACKAGE OUTLINES 74LVC2G125 TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 D E A X c y HE vMA Z 8 5 A pin 1 index A2 A1 (A3) Lp L θ 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.00 A2 0.95 0.75 A3 0.25 bp 0.38 0.22 c 0.18 0.08 D(1) 3.1 2.9 E(1) 3.1 2.9 e 0.65 HE 4.1 3.9 L 0.5 Lp 0.47 0.33 v 0.2 w 0.13 y 0.1 Z(1) 0.70 0.35 θ 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC --JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 2004 Sep 22 12 Philips Semiconductors Product specification Dual bus buffer/line driver; 3-state 74LVC2G125 VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 D E A X c y HE vMA Z 8 5 Q A pin 1 index A2 A1 (A3) θ Lp L 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.15 0.00 A2 0.85 0.60 A3 0.12 bp 0.27 0.17 c 0.23 0.08 D(1) 2.1 1.9 E(2) 2.4 2.2 e 0.5 HE 3.2 3.0 L 0.4 Lp 0.40 0.15 Q 0.21 0.19 v 0.2 w 0.13 y 0.1 Z(1) 0.4 0.1 θ 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC MO-187 JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 2004 Sep 22 13 Philips Semiconductors Product specification Dual bus buffer/line driver; 3-state 74LVC2G125 XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 0.95 x 1.95 x 0.5 mm SOT833-1 1 2 3 b 4 4× L (2) L1 e 8 e1 7 e1 6 e1 5 8× (2) A A1 D E terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A (1) max 0.5 A1 max 0.04 b 0.25 0.17 D 2.0 1.9 E 1.0 0.9 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT833-1 REFERENCES IEC --JEDEC MO-252 JEITA --EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 2004 Sep 22 14 Philips Semiconductors Product specification Dual bus buffer/line driver; 3-state DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION 74LVC2G125 This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). II Preliminary data Qualification III Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification  The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition  Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information  Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications  These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes  Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2004 Sep 22 15 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. © Koninklijke Philips Electronics N.V. 2004 SCA76 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R20/04/pp16 Date of release: 2004 Sep 22 Document order number: 9397 750 13777