80C52

INTEGRATED CIRCUITS 80C528/83C528 CMOS single-chip 8-bit microcontroller Product specification IC20 Data Handbook 1995 Feb 02 Philips Semiconductors Philips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C528/83C528 DESCRIPTION The 8XC528 single-chip 8-bit microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The 8XC528 has the same instruction set as the 80C51. Three versions of the derivative exist: ROM multi-source, two-priority-level, nested interrupt structure, two serial interfaces (UART and I2C-bus), and on-chip oscillator and timing circuits. In addition, the 8XC528 has two software selectable modes of power reduction — idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. FEATURES • 80C51 instruction set – 32k × 8 ROM (83C528) – ROMless (80C528) – 512 × 8 RAM – Memory addressing capability 64k ROM and 64k RAM – Three 16-bit counter/timers – On-chip watchdog timer with oscillator – Full duplex UART – I2C serial interface – Four 8-bit I/O ports • 83C528 — 32k bytes mask programmable • 80C528 — ROMless version of the 83C528 • 87C528 — 32k bytes EPROM (described in a separate data sheet) This device provides architectural enhancements that make it applicable in a variety of applications in consumer, telecom and general control systems, especially in those systems which need large ROM and RAM capacity on-chip. The 8XC528 contains a 32k × 8 ROM (83C528), a 512 × 8 RAM, four 8-bit I/O ports, two 16-bit timer/event counters (identical to the timers of the 80C51), a 16-bit timer (identical to the timer 2 of the 80C52), a watchdog timer with a separate oscillator, a • Power control modes: – Idle mode – Power-down mode – Warm start from power-down • CMOS and TTL compatible • Extended temperature ranges • ROM code protection • 7-source and 7-vector interrupt structure • Up to 3 external interrupt request inputs • Two programmable power reduction modes • Termination of Idle mode by any interrupt, • XTAL frequency range: 1.2 MHz to 16 MHz external or WDT (watchdog) reset (Idle and Power-down) with 2 priority levels PIN CONFIGURATIONS T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 SCL/P1.6 SDA/P1.7 RST 1 2 3 4 5 6 7 8 9 DUAL IN-LINE PACKAGE 40 VDD 39 P0.0/AD0 38 P0.1/AD1 37 P0.2/AD2 36 P0.3/AD3 35 P0.4/AD4 34 P0.5/AD5 33 P0.6/AD6 32 P0.7/AD7 31 EA 30 ALE 29 PSEN 28 P2.7/A15 27 P2.6/A14 26 P2.5/A13 25 P2.4/A12 24 P2.3/A11 23 P2.2/A10 22 P2.1/A9 21 P2.0/A8 T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 SCL/P1.6 SDA/P1.7 RST 1 2 3 4 5 6 7 8 9 SHRINK DUAL IN-LINE PACKAGE 42 VDD 41 P0.0/AD0 40 P0.1/AD1 7 39 P0.2/AD2 38 P0.3/AD3 37 P0.4/AD4 36 P0.5/AD5 35 P0.6/AD6 34 P0.7/AD7 33 EA 32 NC* 31 ALE 30 PSEN 29 P2.7/A15 28 P2.6/A14 27 P2.5/A13 26 P2.4/A12 25 P2.3/A11 24 P2.2/A10 23 P2.1/A9 22 P2.0/A8 12 22 11 1 QUAD FLAT PACK 23 33 44 34 18 28 17 LEADED CHIP CARRIER 29 39 6 1 40 RxD/P3.0 10 TxD/P3.1 11 INT0/P3.2 12 INT1/P3.3 13 T0/P3.4 14 T1/P3.5 15 WR/P3.6 16 RD/P3.7 17 XTAL2 18 XTAL1 19 VSS 20 RxD/P3.0 10 NC* 11 TxD/P3.1 12 INT0/P3.2 13 INT1/P3.3 14 T0/P3.4 15 T1/P3.5 16 WR/P3.6 17 RD/P3.7 18 XTAL2 19 XTAL1 20 VSS 21 * DO NOT CONNECT 1995 Feb 02 2 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C528/83C528 CERAMIC AND PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS 6 1 40 PLASTIC QUAD FLAT PACK PIN FUNCTIONS 44 34 7 39 1 33 PLCC PQFP 17 29 11 23 18 28 12 Function NC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE NC* EA P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function P1.5 P1.6/SCL P1.7/SDA RST P3.0/RxD NC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7RD XTAL2 XTAL1 VSS NC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 22 Function P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE NC* EA P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD NC* P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function NC* P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4 P1.5 P1.6/SCL P1.7/SDA RST P3.0/RxD NC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 * DO NOT CONNECT * DO NOT CONNECT LOGIC SYMBOL VDD XTAL1 PORT 0 ADDRESS AND DATA BUS VSS XTAL2 T2 T2EX RST EA PSEN SECONDARY FUNCTIONS ALE RxD TxD INT0 INT1 T0 T1 WR RD PORT 1 SCL SDA PORT 3 PORT 2 ADDRESS BUS 1995 Feb 02 3 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C528/83C528 ORDERING INFORMATION PHILIPS PART ORDER NUMBER PART MARKING ROMless P80C528FBP ROM P83C528FBP/xxx PHILIPS NORTH AMERICA PART ORDER NUMBER ROMless P80C528FBP N ROM P83C528FBP N Drawing Number SOT129-1 TEMPERATURE oC RANGE AND PACKAGE 0 to +70, Plastic Dual In-line Package FREQ MHz 16 P80C528FBA P83C528FBA/xxx P80C528FBA A P83C528FBA A SOT187-2 0 to +70, Plastic Leaded Chip Carrier 16 P80C528FBB P80C528FFP P83C528FBB/xxx P83C528FFP/xxx P80C528FBB B P80C528FFP N P83C528FBB B P83C528FFP N SOT307-2 SOT129-1 0 to +70, Plastic Quad Flat Pack –40 to +85, Plastic Dual In-line Package 16 16 P80C528FFA P83C528FFA/xxx P80C528FFA A P83C528FFA A SOT187-2 –40 to +85, Plastic Leaded Chip Carrier 16 P80C528FFB P80C528FHP P80C528FHA P80C528FHB P83C528FFB/xxx P83C528FHP/xxx P83C528FHA/xxx P83C528FHB/xxx P80C528FFB B P80C528FHP N P80C528FHA A P80C528FHB B P83C528FFB B P83C528FHP N P83C528FHA A P83C528FHB B SOT307-2 SOT129-1 SOT187-2 SOT307-2 –40 to +85, Plastic Quad Flat Pack –40 to +125, Plastic Dual In-line Package –40 to +125, Plastic Leaded Chip Carrier –40 to +125, Plastic Quad Flat Pack 16 16 16 16 P83C528FBR/xxx NOTE: 1. xxx denotes the ROM code number. SOT270-1 0 to +70, Plastic Shrink Dual In-Linr Package 16 1995 Feb 02 4 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C528/83C528 EPROM P87C528EBP N P87C528EBF FA P87C528EBA AA P87C528EBL KA P87C528EBB B P87C528EFP N P87C528EFF FA P87C528EFF FA P87C528EFL KA P87C528EFB B Drawing Number SOT129-1 0590B SOT187-2 1472A SOT307-2 SOT129-1 0590B SOT187-2 1472A SOT307-2 TEMPERATURE oC RANGE AND PACKAGE 0 to +70, Plastic Dual In-line Package 0 to +70, Ceramic Dual In-line Package w/Window 0 to +70, Plastic Leaded Chip Carrier 0 to +70, Ceramic Leaded Chip Carrier w/Window 0 to +70, Plastic Quad Flat Pack –40 to +85, Plastic Dual In-line Package –40 to +85, Ceramic Dual In-line Package w/Window –40 to +85, Plastic Leaded Chip Carrier –40 to +85, Ceramic Leaded Chip Carrier w/Window –40 to +85, Plastic Quad Flat Pack FREQ MHz 16 16 16 16 16 16 16 16 16 16 P87C528GBP N P87C528GBF FA P87C528GBA A P87C528GBL KA P87C528GFP N P87C528GFF FA P87C528GFA A P87C528GFL KA SOT129-1 0590B SOT187-2 1472A SOT129-1 0590B SOT187-2 1472A 0 to +70, Plastic Dual In-line Package 0 to +70, Ceramic Dual In-line Package w/Window 0 to +70, Plastic Leaded Chip Carrier 0 to +70, Ceramic Leaded Chip Carrier w/Window –40 to +85, Plastic Dual In-line Package –40 to +85, Ceramic Dual In-line Package w/Window –40 to +85, Plastic Leaded Chip Carrier –40 to +85, Ceramic Leaded Chip Carrier w/Window 20 20 20 20 20 20 20 20 1995 Feb 02 5 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C528/83C528 BLOCK DIAGRAM FREQUENCY REFERENCE XTAL2 XTAL1 COUNTERS T0 T1 T2 T2EX RST RAM OSCILLATOR AND TIMING PROGRAM MEMORY (32K x 8 ROM) DATA MEMORY (256 x 8) AUX–RAM DATA MEMORY (256 x 8) TWO 16-BIT TIMER/EVENT COUNTERS 16-BIT TIMER / EVENT COUNTER WATCHDOG TIMER CPU INTERNAL INTERRUPTS 64K-BYTE BUS EXPANSION CONTROL PROGRAMMABLE I/O PROGRAMMABLE SERIAL PORT FULL DUPLEX UART SYNCHRONOUS SHIFT BIT-LEVEL I2C INTERFACE INT0 INT1 EXTERNAL INTERRUPTS CONTROL PARALLEL PORTS, ADDRESS/DATA BUS AND I/O PINS SERIAL IN SERIAL OUT SDA SCL SHARED WITH PORT 3 1995 Feb 02 6 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C528/83C528 PIN DESCRIPTION PIN NO. MNEMONIC VSS VDD P0.0–0.7 DIP 20 40 39–32 SDIL 21 42 41–34 LCC 22 44 43–36 QFP 16 38 37–30 TYPE I I I/O NAME AND FUNCTION Ground: circuit ground potential. Power Supply: +5V power supply pin during normal operation, Idle mode and Power-down mode. Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7 which have open drain. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 1 can sink/source one TTL (4 LSTTL) inputs. T2 (P1.0): Timer/counter 2 external count input (following edge triggered). T2EX (P1.1): Timer/counter 2 trigger input. SCL (P1.6): I2C serial port clock line. SDA (P1.7): I2C serial port data line. Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the SC80C51 family, as listed below: RxD (P3.0): Serial input port TxD (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VDD. After a watchdog timer overflow, this pin is pulled high while the internal reset signal is active. Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. Program Store Enable: The read strobe to external program memory. When the device is executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. External Access Enable: EA must be externally held low during RESET to enable the device to fetch code from external program memory locations 0000H to 7FFFH. If EA is held high during RESET, the device executes from internal program memory unless the program counter contains an address greater than 7FFFH. EA is don’t care after RESET. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier. P1.0–P1.7 1–8 1–8 2–9 40–44 1–3 I/O 1 2 7 8 P2.0–P2.7 21–28 1 2 7 8 22–29 2 3 8 9 24–31 40 41 2 3 18–25 I I I/O I/O I/O P3.0–P3.7 10–17 10–18 (11=NC) 11, 13–19 5, 7–13 I/O 10 11 12 13 14 15 16 17 RST 9 10 12 13 14 15 16 17 18 9 11 13 14 15 16 17 18 19 10 5 7 8 9 10 11 12 13 4 I O I I I I O O I/O ALE 30 31 33 27 I/O PSEN 29 30 32 26 O EA 31 33 35 29 I XTAL1 XTAL2 19 18 20 19 21 20 15 14 I O 1995 Feb 02 7 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C528/83C528 Table 1. SYMBOL ACC* B* DPTR: DPH DPL IE*# IP*# 8XC524/8XC528 Special Function Registers DESCRIPTION Accumulator B register Data pointer (2 bytes): Data pointer high Data pointer low Interrupt enable Interrupt priority DIRECT ADDRESS E0H F0H 83H 82H AF A8H B8H EA BF – 87 AE ES1 BE PS1 86 AD6 96 SEL A6 A14 B6 WR – D6 AC AD ET2 BD PT2 85 AD5 95 – A5 A13 B5 T1 – D5 F0 AC ES0 BC PS0 84 AD4 94 – A4 A12 B4 T0 – D4 RS1 AB ET1 BB PT1 83 AD3 93 – A3 A11 B3 INT1 GF1 D3 RS0 AA EX1 BA PX1 82 AD2 92 – A2 A10 B2 INT0 GF0 D2 OV A9 ET0 B9 PT0 81 AD1 91 T2EX A1 A9 B1 TxD PD D1 F1 A8 EX0 B8 PX0 80 AD0 90 T2 A0 A8 B0 RxD IDL D0 P 00H 00H 00H xxxxxxxxB 9F 9E SM1 0 X X DE SCI SC0 8E TR1 CE EXF2 9D SM2 0 X X DD CLH CLH 8D TF0 CD RCLK 9C REN 0 X X DC BB X 8C TR0 CC TCLK 9B TB8 0 X X DB RBF X 8B IE1 CB EXEN2 9A RB8 0 X X DA WBF X 8A IT1 CA TR2 99 TI 0 X X D9 STR STR 89 IE0 C9 C/T2 98 RI 0 X X D8 ENS ENS 88 IT0 C8 CP/RL2 BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB E7 F7 E6 F6 E5 F5 E4 F4 E3 F3 E2 F2 E1 F1 LSB E0 F0 RESET VALUE 00H 00H 00H 00H 00H x0000000B P0* Port 0 80H AD7 97 FFH P1* Port 1 90H SDA A7 FFH P2* Port 2 A0H A15 B7 FFH P3* PCON Port 3 Power control B0H 87H RD SMOD D7 FFH 0xxx0000B PSW* RCAP2H# RCAP2L# SBUF SCON* S1BIT# S1INT# S1SCS*# SP TCON* T2CON*# TH0 TH1 TH2# TL0 TL1 TL2# T3# TMOD WDCON# Program status word Capture high Capture low Serial data buffer Serial controller Serial I2C data D0H CBH CAH 99H 98H D9H/RD WR DAH D8H/RD WR 81H CY SM0 SDI SD0 INT DF SDI SD0 8F 00H x0000000B 0xxxxxxxB 0xxxxxxxB xxxx0000B 00xxxx00B 07H Serial I2C interrupt Serial I2C control Stack pointer Timer control Timer 2 control Timer high 0 Timer high 1 Timer high 2 Timer low 0 Timer low 1 Timer low 2 Watchdog timer Timer mode Watchdog control 88H C8H 8CH 8DH CDH 8AH 8BH CCH FFH 89H A5H TF1 CF TF2 00H 00H 00H 00H 00H 00H 00H 00H 00H GATE C/T M1 M0 GATE C/T M1 M0 00H A5H * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. 1995 Feb 02 8 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C528/83C528 Table 2. Internal and External Program Memory Access with Security Bit Set INSTRUCTION ACCESS TO INTERNAL PROGRAM MEMORY YES NO ACCESS TO EXTERNAL PROGRAM MEMORY YES YES MOVC in internal program memory MOVC in external program memory ROM CODE PROTECTION By setting a mask programmable security bit, the ROM content in the 83C528 is protected, i.e., it cannot be read out by any test mode or by any instruction in the external program memory space. The MOVC instructions are the only ones which have access to program code in the internal or external program memory. The EA input is latched during RESET and is ‘don’t care’ after RESET (also if security bit is not set). This implementation prevents reading from internal program code by switching from external program memory to internal program memory during MOVC instruction or an instruction that handles immediate data. Table 2 lists the access to the internal and external program memory by the MOVC instructions when the security bit has been set to logical one. If the security bit has been set to a logical 0 there are no restrictions for the MOVC instructions. TIMER 2 Timer 2 is functionally equal to the Timer 2 of the 8052AH. Timer 2 is a 16-bit timer/counter. These 16 bits are formed by two special function registers TL2 and TH2. Another pair of special function register RCAP2L and RCAP2H form a 16-bit capture register or a 16-bit reload register. Like Timer 0 and 1, it can operate either as a timer or as an event counter. This is selected by bit C/T2N in the special function register T2CON. It has three operating modes: capture, autoload, and baud rate generator mode which are selected by bits in T2CON. program has to reload the watchdog timer within periods that are shorter than the programmed watchdog timer internal. This time interval is determined by an 8-bit value that has to be loaded in register T3 while at the same time the prescaler is cleared by hardware. Watchdog timer interval = [256 * (T3)] 2048 on * chip oscillator frequency BIT-LEVEL I2C INTERFACE This bit-level serial I/O interface supports the I2C-bus. P1.6/SCL and P1.7/SDA are the serial I/O pins. These two pins meet the I2C specification concerning the input levels and output drive capability. Consequently, these pins have an open drain output configuration. All the four modes of the I2C-bus are supported: – master transmitter – master receiver – slave transmitter – slave receiver The advantages of the bit-level I2C hardware compared with a full software I2C implementation are: – the hardware can generate the SCL pulse – Testing a single bit (RBF respectively, WBF) is sufficient as a check for error free transmission. The bit-level I2C hardware operates on serial bit level and performs the following functions: – filtering the incoming serial data and clock signals – recognizing the START condition – generating a serial interrupt request SI after reception of a START condition and the first falling edge of the serial clock – recognizing the STOP condition – recognizing a serial clock pulse on the SCL line – latching a serial bit on the SDA line (SDI) – stretching the SCL LOW period of the serial clock to suspend the transfer of the next serial data bit WATCHDOG TIMER T3 The watchdog timer consists of an 11-bit prescaler and an 8-bit timer formed by special function register T3. The prescaler is incremented by an on-chip oscillator with a fixed frequency of 1MHz. The maximum tolerance on this frequency is –50% and +100%. The 8-bit timer increments every 2048 cycles of the on-chip oscillator. When a timer overflow occurs, the microcontroller is reset and a reset output pulse of 16 × 2048 cycles of the on-chip oscillator is generated at pin RST. The internal RESET signal is not inhibited when the external RST pin is kept low by, for example, an external reset circuit. The RESET signal drives port 1, 2, 3 into the high state and port 0 into the high impedance state. The watchdog timer is controlled by one special function register WDCON with the direct address location A5H. WDCON can be read and written by software. A value of A5H in WDCON halts the on-chip oscillator and clears both the prescaler and timer T3. After the RESET signal, WDCON contains A5H. Every value other than A5H in WDCON enables the watchdog timer. When the watchdog timer is enabled, it runs independently of the XTAL-clock. Timer T3 can be read on the fly. Timer T3 can only be written if WDCON contains the value 5AH. A successful write operation to T3 will clear the prescaler and WDCON, leaving the watchdog enabled and preventing inadvertent changes of T3. To prevent an overflow of the watchdog timer, the user INTERNAL DATA MEMORY The internal data memory is divided into three physically separated segments: 256 bytes of RAM, 256 bytes of AUX-RAM, and a 128 bytes special function area. These can be addressed each in a different way. – RAM 0 to 127 can be addressed directly and indirectly as in the 80C51. Address pointers are R0 and R1 of the selected register bank. – RAM 128 to 255 can only be addressed indirectly as in the 80C51. Address pointers are R0 and R1 of the selected register bank. – AUX-RAM 0 to 255 is indirectly addressed in the same way as external data memory with the MOVX instructions. Address pointers are R0, R1 of the selected register bank and DPTR. An access to AUX-RAM 0 to 255 will not affect ports P0, P2, P3.6 and P3.7. An access to external data memory locations higher than 255 will be performed with the MOVX DPTR instructions in the same way as in the 8051 structure, so with P0 and P2 as data/address bus and P3.6 and P3.7 as write and read timing signals. Note that these external data memory cannot be accessed with R0 and R1 as address pointer. 1995 Feb 02 9 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C528/83C528 – setting Read Bit Finished (RBF) when the SCL clock pulse has finished and Write Bit Finished (WBF) if there is no arbitration loss detected (i.e., SDA = 0 while SDO = 1) – setting a serial clock Low-to-High detected (CLH) flag – setting a Bus Busy (BB) flag on a START condition and clearing this flag on a STOP condition – releasing the SCL line and clearing the CLH, RBF and WBF flags to resume transfer of the next serial data bit – generating an automatic clock if the single bit data register S1BIT is used in master mode. The following functions must be done in software: – handling the I2C START interrupts – converting serial to parallel data when receiving – converting parallel to serial data when transmitting – comparing the received slave address with its own – interpreting the acknowledge information – guarding the I2C status if RBF or WBF = 0. Additionally, if acting as master: – generating START and STOP conditions – handling bus arbitration – generating serial clock pulses if S1BIT is not used. Three SFRs control the bit-level I2C interface: S1INT, S1BIT and S1SCS. IP: Interrupt Priority Register This register is located at address B8H. Refer to Table 4. IP SFR (B8H) 7 – 6 PS1 5 PT2 4 PS 3 PT1 2 PX1 1 PT0 0 PX0 The interrupt vector locations and the interrupt priorities are: Source Vector 0003H 002BH 0053H 000BH 0013H 001BH 0023H Priority within Level Address IE0 TF2+EXF2 SI (I2C) TF0 IE1 TF1 R1+T1 Highest INTERRUPT SYSTEM The interrupt structure of the 8XC528 is the same as that used in the 80C51, but includes two additional interrupt sources: one for the third timer/counter, T2, and one for the I2C interface. The interrupt enable and interrupt priority registers are IE and IP. IE: Interrupt Enable Register This register is located at address A8H. Refer to Table 3. IE SFR (A8H) 7 EA 6 ES1 5 ET2 4 ES 3 ET1 2 EX1 1 ET0 0 EX0 Lowest Table 3. Description of IE Bits MNEMONIC EA BIT IE.7 FUNCTION General enable/disable control: 0 = NO interrupt is enabled. 1 = ANY individually enabled interrupt will be accepted. Enable bit-level I2C I/O interrupt Enable Timer 2 interrupt Enable Serial Port interrupt Enable Timer 1 interrupt Enable External interrupt 1 Enable Timer 0 interrupt Enable External interrupt 0 ES1 ET2 ES ET1 EX1 ET0 EX0 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0 Table 4. Description of IP Bits MNEMONIC – PS1 PT2 PS PT1 PX1 PT0 PX0 BIT IP.7 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 IP.0 FUNCTION Reserved. Bit-level I2C interrupt priority level Timer 2 interrupt priority level Serial Port interrupt priority level Timer 1 interrupt priority level External Interrupt 1 priority level Timer 0 interrupt priority level External Interrupt 0 priority level 1995 Feb 02 10 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C528/83C528 OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator, as shown in the Logic Symbol. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed. IDLE MODE In idle mode, the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. signal INT0 and INT1 must be kept low until the oscillator has restarted and stabilized. An instruction following the instruction that puts the device in the power-down mode will be executed. A reset generated by the watchdog timer terminates the power-down mode in the same way as an external RESET, and only the contents of the on-chip RAM are preserved. The control bits for the reduced power modes are in the special function register PCON. DESIGN CONSIDERATIONS At power-on, the voltage on VDD and RST must come up at the same time for a proper start-up. When the idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when idle is terminated by reset, the instruction following the one that invokes idle should not be one that writes to a port pin or to external memory. Table 5 shows the state of I/O ports during low current operating modes. RESET A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To insure a good power-up reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-up, the voltage on VDD and RST must come up at the same time for a proper start-up. POWER-DOWN MODE In the power-down mode, the oscillator is stopped and the instruction to invoke power-down is the last instruction executed. The power-down mode can be terminated by a RESET in the same way as in the 80C51 or in addition by one of two external interrupts, INT0 or INT1. A termination with an external interrupt does not affect the internal data memory and does not affect the special function registers. This makes it possible to exit power-down without changing the port output levels. To terminate the power-down mode with an external interrupt INT0 or INT1 must be switched to level-sensitive and must be enabled. The external interrupt input Table 5. Idle Idle Power-down Power-down External Pin Status During Idle and Power-Down Modes MODE PROGRAM MEMORY Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT 0 Data Float Data Float PORT 1 Data Data Data Data PORT 2 Data Address Data Data PORT 3 Data Data Data Data 1995 Feb 02 11 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C528/83C528 ABSOLUTE MAXIMUM RATINGS1, 2, 3 PARAMETER Operating temperature under bias Storage temperature range Voltage on any other pin to VSS Input, output current on any two pins Power dissipation (based on package heat transfer limitations, not device power consumption) RATING 0 to +70, or –40 to +85, or –40 to +125 –65 to +150 –0.5 to VDD +0.5 ±10 1.0 UNIT °C °C V mA W NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. DC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C (VDD = 5V ±20%), –40°C to +85°C (VDD = 5V ±20%), or –40°C to +125°C (VDD = 5V ±10%), VSS=0V TEST SYMBOL VIL PARAMETER Input low voltage, except EA, P1.6/SCL, P1.7/SDA Input low voltage to EA PART TYPE 0°C to 70°C –40°C to +85°C –40°C to +125°C 0°C to 70°C –40°C to +85°C –40°C to +125°C 0°C to 70°C –40°C to +85°C –40°C to +125°C 0°C to 70°C –40°C to +85°C –40°C to +125°C IOL = 1.6mA4 IOL = 3.2mA4 IOL = 3.0mA4 VDD = 5V ±10%, IOH = –60µA IOH = –25µA IOH = –10µA VDD = 5V ±10%, IOH = –800µA IOH = –300µA IOH = –80µA 0°C to 70°C –40°C to +85°C –40°C to +125°C 0°C to 70°C –40°C to +85°C –40°C to +125°C VIN = 0.45V 2.4 0.75VDD 0.9VDD 2.4 0.75VDD 0.9VDD –50 –75 –75 –650 –750 –750 CONDITIONS MIN –0.5 –0.5 –0.5 –0.5 –0.5 –0.5 –0.5 0.2VDD+0.9 0.2VDD+1.0 0.2VDD+1.0 0.7VDD 0.7VDD+0.1 0.7VDD+0.1 0.7VDD LIMITS MAX 0.2VDD–0.1 0.2VDD–0.15 0.2VDD–0.25 0.2VDD–0.3 0.2VDD–0.35 0.2VDD–0.45 0.3VDD VDD+0.5 VDD+0.5 VDD+0.5 VDD+0.5 VDD+0.5 VDD+0.5 6.0 0.45 0.45 0.4 UNIT V V V V V V V V V V V V V V V V V V V V V V V µA µA µA µA µA µA VIL1 VIL2 VIH Input low voltage to P1.6/SCL, P1.7/SDA3 Input high voltage, except XTAL1, RST, P1.6/SCL, P1.7/SDA Input high voltage, XTAL1, RST VIH1 VIH2 VOL VOL1 VOL2 VOH Input high voltage, P1.6/SCL, P1.7/SDA3 Output low voltage, ports 1, 2, 3, except P1.6/SCL, P1.7/SDA1 Output low voltage, port 0, ALE, PSEN1 Output low voltage, P1.6/SCL, P1.7/SDA Output high voltage, ports 1, 2, 3 VOH1 Output high voltage, Port 0 in external bus mode, ALE, PSEN, RST2 IIL Logical 0 input current, ports 1, 2, 3, except P1.6/SCL, P1.7/SDA Logical 1-to-0 transition current, ports 1, 2, 3, except P1.6/SCL, P1.7/SDA ITL See note 5 1995 Feb 02 12 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C528/83C528 DC ELECTRICAL CHARACTERISTICS (Continued) Tamb = 0°C to +70°C (VDD = 5V ±20%), –40°C to +85°C (VDD = 5V ±20%), or –40°C to +125°C (VDD = 5V ±10%), VSS=0V TEST SYMBOL IIL1 IIL2 IDD PARAMETER Input leakage current, port 0, EA Input leakage current, P1.6/SCL, P1.7/SDA Power supply current: Active mode Idle mode Power down mode Power down mode Internal reset pull-down resistor Capacitance of I/O buffer Freq.=1MHz Tamb = 25°C PART TYPE CONDITIONS 0.45