HEF4047BT

INTEGRATED CIRCUITS DATA SHEET TDA8922 2 × 25 W class-D power amplifier Objective specification 2003 Mar 20 Philips Semiconductors Objective specification 2 × 25 W class-D power amplifier CONTENTS 1 2 3 4 5 6 7 8 8.1 8.2 8.3 8.3.1 8.3.2 8.3.3 8.3.4 8.4 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 16.9 16.10 16.11 16.12 16.13 FEATURES APPLICATIONS GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION General Pulse width modulation frequency Protections Overtemperature Short-circuit across loudspeaker terminals and to supply lines Start-up safety test Supply voltage alarm Differential audio inputs LIMITING VALUES THERMAL CHARACTERISTICS QUALITY SPECIFICATION STATIC CHARACTERISTICS SWITCHING CHARACTERISTICS DYNAMIC AC CHARACTERISTICS (STEREO AND DUAL SE APPLICATION) DYNAMIC AC CHARACTERISTICS (MONO BTL APPLICATION) APPLICATION INFORMATION BTL application Pin MODE Output power estimation External clock Heatsink requirements Output current limiting Pumping effects Reference design PCB information for HSOP24 package Classification Bill of materials for reference design Curves measured in reference design Application schematics 17 18 18.1 18.2 18.2.1 18.2.2 18.3 18.3.1 18.3.2 18.3.3 18.4 19 20 21 PACKAGE OUTLINE SOLDERING TDA8922 Introduction Through-hole mount packages Soldering by dipping or by solder wave Manual soldering Surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of IC packages for wave, reflow and dipping soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS 2003 Mar 20 2 Philips Semiconductors Objective specification 2 × 25 W class-D power amplifier 1 FEATURES 2 APPLICATIONS TDA8922 • High efficiency (∼90%) • Operating supply voltage from ±12.5 to ±30 V • Very low quiescent current • Low distortion • Usable as a stereo Single-Ended (SE) amplifier or as a mono amplifier in Bridge-Tied Load (BTL) • Fixed gain of 30 dB in Single-Ended (SE) and 36 dB in Bridge-Tied Load (BTL) • High output power • Good ripple rejection • Internal switching frequency can be overruled by an external clock • No switch-on or switch-off plop noise • Short-circuit proof across load and to supply lines • Electrostatic discharge protection • Thermally protected. 4 QUICK REFERENCE DATA SYMBOL General; VP = ±20 V VP Iq(tot) η Po supply voltage total quiescent supply no load connected current efficiency PARAMETER • Television sets • Home-sound sets • Multimedia systems • All mains fed audio systems • Car audio (boosters). 3 GENERAL DESCRIPTION The TDA8922 is a high efficiency class-D audio power amplifier with very low dissipation. The typical output power is 2 × 25 W. The device is available in the HSOP24 power package with a small internal heatsink and in the DBS23P through-hole power package. Depending on the supply voltage and load conditions, a very small or even no external heatsink is required. The amplifier operates over a wide supply voltage range from ±12.5 to ±30 V and consumes a very low quiescent current. CONDITIONS MIN. ±12.5 − − 22 22 TYP. ±20 55 90 MAX. ±30 75 − − − − UNIT V mA % Po = 25 W; SE: RL = 2 × 8 Ω; fi = 1 kHz RL = 8 Ω; THD = 10%; VP = ±20 V; note 1 RL = 4 Ω; THD = 10%; VP = ±15 V; note 1 Stereo single-ended configuration output power 25 25 W W Mono bridge-tied load configuration Po Note 1. See Section 16.5. 5 ORDERING INFORMATION TYPE NUMBER TDA8922TH TDA8922J PACKAGE NAME HSOP24 DBS23P DESCRIPTION plastic, heatsink small outline package; 24 leads; low stand-off height plastic DIL-bent-SIL power package; 23 leads (straight lead length 3.2 mm) VERSION SOT566-3 SOT411-1 output power RL = 8 Ω; THD = 10%; VP = ±15 V; note 1 46 50 W 2003 Mar 20 3 Philips Semiconductors Objective specification 2 × 25 W class-D power amplifier 6 BLOCK DIAGRAM TDA8922 handbook, full pagewidth VDDA2 VDDA1 10 (4) STABI PROT 18 (12) 13 (7) RELEASE1 VDDP2 23 (16) VDDP1 14 (8) 15 (9) 3 (20) BOOT1 IN1− IN1+ 9 (3) 8 (2) INPUT STAGE PWM MODULATOR CONTROL AND ENABLE1 HANDSHAKE SWITCH1 DRIVER HIGH 16 (10) DRIVER LOW VSSP1 OUT1 SGND1 OSC MODE 11 (5) 7 (1) 6 (23) mute STABI OSCILLATOR MODE MANAGER TEMPERATURE SENSOR CURRENT PROTECTION TDA8922TH (TDA8922J) VDDP2 22 (15) BOOT2 SGND2 2 (19) mute ENABLE2 CONTROL SWITCH2 AND HANDSHAKE RELEASE2 DRIVER HIGH 21 (14) DRIVER LOW 17 (11) VSSP1 20 (13) VSSP2 MGU994 IN2 + IN2 − 5 (22) 4 (21) INPUT STAGE PWM MODULATOR OUT2 1 (18) VSSA2 12 (6) VSSA1 24 (17) VSSD 19 (-) HW (1) (1) Pin HW (TDA8922TH only) should be connected to pin VSSD in the application. Pin numbers in parenthesis refer to the TDA8922J. Fig.1 Block diagram. 2003 Mar 20 4 Philips Semiconductors Objective specification 2 × 25 W class-D power amplifier 7 PINNING PIN SYMBOL TDA8922TH VSSA2 SGND2 VDDA2 IN2− IN2+ MODE OSC IN1+ IN1− VDDA1 SGND1 VSSA1 PROT VDDP1 BOOT1 OUT1 VSSP1 STABI HW VSSP2 OUT2 BOOT2 VDDP2 VSSD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 TDA8922J 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 12 − 13 14 15 16 17 negative analog supply voltage for channel 2 signal ground for channel 2 positive analog supply voltage for channel 2 negative audio input for channel 2 positive audio input for channel 2 mode selection input: standby, mute or operating oscillator frequency adjustment or tracking input positive audio input for channel 1 negative audio input for channel 1 positive analog supply voltage for channel 1 signal ground for channel 1 negative analog supply voltage for channel 1 time constant capacitor for protection delay positive power supply voltage for channel 1 bootstrap capacitor for channel 1 PWM output from channel 1 negative power supply voltage for channel 1 decoupling of internal stabilizer for logic supply handle wafer; must be connected to pin VSSD negative power supply voltage for channel 2 PWM output from channel 2 bootstrap capacitor for channel 2 positive power supply voltage for channel 2 negative digital supply voltage DESCRIPTION TDA8922 2003 Mar 20 5 Philips Semiconductors Objective specification 2 × 25 W class-D power amplifier TDA8922 handbook, halfpage OSC IN1+ IN1− VDDA1 SGND1 VSSA1 handbook, halfpage 1 2 3 4 5 6 7 8 9 VSSD 24 VDDP2 23 BOOT2 22 OUT2 21 VSSP2 20 HW 19 1 2 3 4 5 6 VSSA2 SGND2 VDDA2 IN2 − IN2 + MODE OSC IN1+ IN1− PROT VDDP1 BOOT1 OUT1 10 VSSP1 11 STABI 12 VSSP2 13 OUT2 14 BOOT2 15 VDDP2 16 VSSD 17 VSSA2 18 SGND2 19 VDDA2 20 IN2 − 21 IN2 + 22 MODE 23 MGU996 TDA8922J TDA8922TH STABI 18 VSSP1 17 OUT1 16 BOOT1 15 VDDP1 14 PROT 13 MGU995 7 8 9 10 VDDA1 11 SGND1 12 VSSA1 Fig.2 Pin configuration TDA8922TH. Fig.3 Pin configuration TDA8922J. 2003 Mar 20 6 Philips Semiconductors Objective specification 2 × 25 W class-D power amplifier 8 8.1 FUNCTIONAL DESCRIPTION General TDA8922 The amplifier system can be switched in three operating modes with pin MODE: • Standby mode; with a very low supply current • Mute mode; the amplifiers are operational, but the audio signal at the output is suppressed • Operating mode; the amplifiers fully are operational with output signal. An example of a switching circuit for driving pin MODE is illustrated in Fig.4. For suppressing plop noise, the amplifier will remain automatically in the mute mode for approximately 150 ms before switching to the operating mode (see Fig.5). During this time, the coupling capacitors at the input are fully charged. The TDA8922 is a two channel audio power amplifier using class-D technology. A detailed application reference design is shown in Fig.10. Typical application schematics are shown in Figs 37 and 38. The audio input signal is converted into a digital Pulse Width Modulated (PWM) signal via an analog input stage and PWM modulator. To enable the output power transistors to be driven, this digital PWM signal is applied to a control and handshake block and driver circuits for both the high side and low side. In this way a level shift is performed from the low power digital PWM signal (at logic levels) to a high power PWM signal which switches between the main supply lines. A 2nd-order low-pass filter converts the PWM signal to an analog audio signal across the loudspeakers. The TDA8922 one-chip class-D amplifier contains high power D-MOS switches, drivers, timing and handshaking between the power switches and some control logic. For protection a temperature sensor and a maximum current detector are built-in. The two audio channels of the TDA8922 contain two PWMs, two analog feedback loops and two differential input stages. It also contains circuits common to both channels such as the oscillator, all reference sources, the mode functionality and a digital timing manager. The TDA8922 contains two independent amplifier channels with high output power, high efficiency (90%), low distortion and a low quiescent current. The amplifier channels can be connected in the following configurations: • Mono Bridge-Tied Load (BTL) amplifier • Stereo Single-Ended (SE) amplifiers. handbook, halfpage +5 V standby/ mute R MODE pin R SGND MBL463 mute/on Fig.4 Example of mode selection circuit. 2003 Mar 20 7 Philips Semiconductors Objective specification 2 × 25 W class-D power amplifier TDA8922 handbook, full pagewidth audio switching Vmode operating 4V 2V mute 0 V (SGND) standby 100 ms >50 ms time audio switching Vmode operating 4V 0 V (SGND) standby 100 ms 50 ms time MBL465 When switching from standby to mute, there is a delay of 100 ms before the output starts switching. The audio signal is available after Vmode has been set to operating, but not earlier than 150 ms after switching to mute. When switching from standby to operating, there is a first delay of 100 ms before the outputs starts switching. The audio signal is available after a second delay of 50 ms. Fig.5 Timing on mode selection input. 2003 Mar 20 8 Philips Semiconductors Objective specification 2 × 25 W class-D power amplifier 8.2 Pulse width modulation frequency 8.3.2 TDA8922 SHORT-CIRCUIT ACROSS LOUDSPEAKER TERMINALS AND TO SUPPLY LINES The output signal of the amplifier is a PWM signal with a carrier frequency of approximately 350 kHz. Using a 2nd-order LC demodulation filter in the application results in an analog audio signal across the loudspeaker. This switching frequency is fixed by an external resistor ROSC connected between pin OSC and VSSA. With the resistor value given in the schematic diagram of the reference design, the carrier frequency is typical 350 kHz. The carrier frequency can be calculated using the 9 × 10 following equation: f osc = ------------------ Hz R OSC If two or more class-D amplifiers are used in the same audio application, it is advisable to have all devices operating at the same switching frequency. This can be realized by connecting all OSC pins together and feed them from a external central oscillator. Using an external oscillator it is necessary to force pin OSC to a DC-level above SGND for switching from the internal to an external oscillator. In this case the internal oscillator is disabled and the PWM will be switched on the external frequency. The frequency range of the external oscillator must be in the range as specified in the switching characteristics; see Chapter 13. In an application circuit: • Internal oscillator: ROSC connected between pin OSC and VSSA • External oscillator: connect the oscillator signal between pins OSC and SGND; delete ROSC and COSC. 8.3 Protections 9 When the loudspeaker terminals are short-circuited or if one of the demodulated outputs of the amplifier is short-circuited to one of the supply lines, this will be detected by the current protection. If the output current exceeds the maximum output current of 4 A, then the power stage will shut down within less than 1 µs and the high current will be switched off. In this state the dissipation is very low. Every 100 ms the system tries to restart again. If there is still a short-circuit across the loudspeaker load or to one of the supply lines, the system is switched off again as soon as the maximum current is exceeded. The average dissipation will be low because of this low duty cycle. 8.3.3 START-UP SAFETY TEST During the start-up sequence, when pin MODE is switched from standby to mute, the conditions at the output terminals of the power stage are checked. In the event of a short-circuit at one of the output terminals to VDD or VSS the start-up procedure is interrupted and the systems waits for open-circuit outputs. Because the test is done before enabling the power stages, no large currents will flow in the event of a short-circuit. This system protects for short-circuits at both sides of the output filter to both supply lines. When there is a short-circuit from the power PWM output of the power stage to one of the supply lines (before the demodulation filter) it will also be detected by the start-up safety test. Practical use of this test feature can be found in detection of short-circuits on the printed-circuit board. Remark: This test is only operational prior to or during the start-up sequence, and not during normal operation. During normal operation the maximum current protection is used to detect short-circuits across the load and with respect to the supply lines. Temperature, supply voltage and short-circuit protections sensors are included on the chip. In the event that the maximum current or maximum temperature is exceeded the system will shut down. 8.3.1 OVERTEMPERATURE If the junction temperature Tj > 150 °C, then the power stage will shut down immediately. The power stage will start switching again if the temperature drops to approximately 130 °C, thus there is a hysteresis of approximately 20 °C. 2003 Mar 20 9 Philips Semiconductors Objective specification 2 × 25 W class-D power amplifier 8.3.4 SUPPLY VOLTAGE ALARM 8.4 Differential audio inputs TDA8922 If the supply voltage drops below ±12.5 V, the undervoltage protection circuit is activated and the system will shut down correctly. If the internal clock is used, this switch-off will be silent and without plop noise. When the supply voltage rises above the threshold level, the system is restarted again after 100 ms. If the supply voltage exceeds ±32 V the overvoltage protection circuit is activated and the power stages will shut down. They are re-enabled as soon as the supply voltage drops below the threshold level. An additional balance protection circuit compares the positive (VDD) and the negative (VSS) supply voltages and is triggered if the voltage difference between them exceeds a certain level. This level depends on the sum of both supply voltages. An expression for the unbalanced threshold level is as follows: Vth(unb) ≈ 0.15 × (VDD + VSS). Example: With a symmetrical supply of ±30 V, the protection circuit will be triggered if the unbalance exceeds approximately 9 V; see Section 16.7. For a high common mode rejection ratio and a maximum of flexibility in the application, the audio inputs are fully differential. By connecting the inputs anti-parallel the phase of one of the channels can be inverted, so that a load can be connected between the two output filters. In this case the system operates as a mono BTL amplifier and with the same loudspeaker impedance an approximately four times higher output power can be obtained. The input configuration for a mono BTL application is illustrated in Fig.6; for more information see Chapter 16. In the stereo single-ended configuration it is also recommended to connect the two differential inputs in anti-phase. This has advantages for the current handling of the power supply at low signal frequencies. handbook, full pagewidth IN1+ IN1− Vin IN2+ IN2− OUT1 SGND OUT2 power stage MBL466 Fig.6 Input configuration for mono BTL application. 2003 Mar 20 10 Philips Semiconductors Objective specification 2 × 25 W class-D power amplifier 9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VP VMODE Vsc IORM Tstg Tamb Tvj Notes 1. See Section 16.6. 10 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) TDA8922TH TDA8922J Rth(j-c) thermal resistance from junction to case TDA8922TH TDA8922J Note 1. See Section 16.5. 11 QUALITY SPECIFICATION note 1 1.3 1.3 PARAMETER thermal resistance from junction to ambient CONDITIONS in free air; note 1 35 35 VALUE supply voltage input voltage on pin MODE short-circuit voltage on output pins repetitive peak current in output pin storage temperature ambient temperature virtual junction temperature note 1 with respect to SGND PARAMETER CONDITIONS − − − − −55 −40 − MIN. TDA8922 MAX. ±30 5.5 ±30 4 +150 +85 150 V V V A UNIT °C °C °C UNIT K/W K/W K/W K/W In accordance with “General Quality Specification for Integrated Circuits: SNW-FQ-611D” if this device is used as an audio amplifier. 2003 Mar 20 11 Philips Semiconductors Objective specification 2 × 25 W class-D power amplifier 12 STATIC CHARACTERISTICS VP = ±25 V; Tamb = 25 °C; measured in Fig.10; unless otherwise specified. SYMBOL Supply VP Iq(tot) Istb VMODE IMODE Vstb Vmute Von VI VOO(SE) ∆VOO(SE) VOO(BTL) ∆VOO(BTL) Vo(stab) Tprot Thys Notes 1. The circuit is DC adjusted at VP = ±12.5 to ±30 V. 2. With respect to SGND (0 V). 3. The transition regions between standby, mute and operating mode contain hysteresis (see Fig.7). 4. With respect to VSSP1. supply voltage total quiescent supply current standby supply current note 1 no load connected ±12.5 − − note 2 VMODE = 5.5 V notes 2 and 3 notes 2 and 3 notes 2 and 3 0 − 0 2.2 4.2 − − − − − 11 ±20 55 100 − − − − − 0 − − − − 13 − 20 PARAMETER CONDITIONS MIN. TYP. TDA8922 MAX. ±30 75 500 UNIT V mA µA V µA V V V Mode select input; pin MODE input voltage input current input voltage for standby mode input voltage for mute mode input voltage for operating mode 5.5 1000 0.8 3.0 5.5 − 150 80 215 115 Audio inputs; pins IN1−, IN1+, IN2+ and IN2− DC input voltage note 2 V Amplifier outputs; pins OUT1 and OUT2 output offset voltage variation of output offset voltage output offset voltage variation of output offset voltage SE; operating and mute SE; operating ↔ mute BTL; operating and mute BTL; operating ↔ mute mute and operating; note 4 mV mV mV mV Stabilizer output; pin STABI stabilizer output voltage 15 − − V °C °C Temperature protection temperature protection activation hysteresis on temperature protection 150 − 2003 Mar 20 12 Philips Semiconductors Objective specification 2 × 25 W class-D power amplifier TDA8922 handbook, full pagewidth MBL467 STBY MUTE ON 0 0.8 2.2 3.0 4.2 5.5 VMODE (V) Fig.7 Behaviour of mode selection pin MODE. 13 SWITCHING CHARACTERISTICS VDD = ±25 V; Tamb = 25 °C; measured in Fig.10; unless otherwise specified. SYMBOL Internal oscillator fosc fosc(int) typical internal oscillator frequency internal oscillator frequency range ROSC = 30.0 kΩ note 1 290 210 317 − 344 600 kHz kHz PARAMETER CONDITIONS MIN. TYP. MAX. UNIT External oscillator or frequency tracking VOSC VOSC(trip) ftrack VP(OSC)(ext) voltage on pin OSC trip level for tracking on pin OSC frequency range for tracking minimum symmetrical supply voltage for external oscillator application SGND + 4.5 − 210 15 SGND + 5 SGND + 2.5 − − SGND + 6 − 600 − V V kHz V Note 1. Frequency set with ROSC according to the formula in Section 8.2. 2003 Mar 20 13 Philips Semiconductors Objective specification 2 × 25 W class-D power amplifier TDA8922 14 DYNAMIC AC CHARACTERISTICS (STEREO AND DUAL SE APPLICATION) VP = ±20 V; RL = 8 Ω; fi = 1 kHz; fosc = 310 kHz; RsL < 0.1 Ω (note 1); Tamb = 25 °C; measured in Fig.10; unless otherwise specified. SYMBOL Po PARAMETER output power CONDITIONS RL = 8 Ω; VP = ±20 V; note 2 THD = 0.5% THD = 10% RL = 8 Ω; VP = ±25 V; note 2 THD = 0.5% THD = 10% RL = 4 Ω; VP = ±15 V; note 2 THD = 0.5% THD = 10% THD total harmonic distortion Po = 1 W; note 3 fi = 1 kHz fi = 10 kHz Gv(cl) η SVRR closed loop voltage gain efficiency supply voltage ripple rejection Po = 25 W; fi = 1 kHz; note 4 operating; note 5 fi = 100 Hz fi = 1 kHz mute; fi = 100 Hz; note 5 standby; fi = 100 Hz; note 5 Zi Vn(o) input impedance noise output voltage operating Rs = 0 Ω; note 6 Rs = 10 kΩ; note 7 mute; note 8 αcs ∆Gv Vo(mute) CMRR Notes 1. RsL is the series resistance of inductor of low-pass LC filter in the application. 2. Output power is measured indirectly; based on RDSon measurement. 3. Total harmonic distortion is measured in a bandwidth of 22 Hz to 22 kHz. When distortion is measured using a lower order low-pass filter a significantly higher value is found, due to the switching frequency outside the audio band. Maximum limit is guaranteed but may not be 100% tested. 4. Output power measured across the loudspeaker load. 5. Vripple = Vripple(max) = 2 V (p-p); Rs = 0 Ω. 6. B = 22 Hz to 22 kHz; Rs = 0 Ω; maximum limit is guaranteed, but may not be 100% tested. 7. B = 22 Hz to 22 kHz; Rs = 10 kΩ. 2003 Mar 20 14 channel separation channel unbalance output signal in mute common mode rejection ratio note 10 Vi(CM) = 1 V (RMS) note 9 − − − − − − − 200 230 220 70 − − 75 400 − − − 1 400 − µV µV µV dB dB µV dB − 40 − − 45 55 50 55 80 68 − − − − − dB dB dB dB kΩ − − 29 85 0.02 0.15 30 90 0.05 − 31 − % % dB % 18 22 20 25 − − W W 29 36 33 40 − − W W 18 22 20 25 − − W W MIN. TYP. MAX. UNIT Philips Semiconductors Objective specification 2 × 25 W class-D power amplifier 8. B = 22 Hz to 22 kHz; independent of Rs. 9. Po = 1 W; Rs = 0 Ω; fi = 1 kHz. 10. Vi = Vi(max) = 1 V (RMS); maximum limit is guaranteed, but may not be 100% tested. TDA8922 15 DYNAMIC AC CHARACTERISTICS (MONO BTL APPLICATION) VP = ±15 V; RL = 8 Ω; fi = 1 kHz; fosc = 310 kHz; RsL < 0.1 Ω (note 1); Tamb = 25 °C; measured in Fig.10; unless otherwise specified. SYMBOL Po PARAMETER output power CONDITIONS RL = 8 Ω; VP = ±15 V; note 2 THD = 0.5% THD = 10% THD total harmonic distortion Po = 1 W; note 3 fi = 1 kHz fi = 10 kHz Gv(cl) η SVRR closed loop voltage gain efficiency supply voltage ripple rejection Po = 50 W; fi = 1 kHz; note 4 operating; note 5 fi = 100 Hz fi = 1 kHz mute; fi = 100 Hz; note 5 standby; fi = 100 Hz; note 5 Zi Vn(o) input impedance noise output voltage operating Rs = 0 Ω; note 6 Rs = 10 kΩ; note 7 mute; note 8 Vo(mute) CMRR Notes 1. RsL is the series resistance of inductor of low-pass LC filter in the application. 2. Output power is measured indirectly; based on RDSon measurement. 3. Total harmonic distortion is measured in a bandwidth of 22 Hz to 22 kHz. When distortion is measured using a low order low-pass filter a significant higher value will be found, due to the switching frequency outside the audio band. Maximum limit is guaranteed but may not be 100% tested. 4. Output power measured across the loudspeaker load. 5. Vripple = Vripple(max) = 2 V (p-p); Rs = 0 Ω. 6. B = 22 Hz to 22 kHz; Rs = 0 Ω; maximum limit is guaranteed, but may not be 100% tested. 7. B = 22 Hz to 22 kHz; Rs = 10 kΩ. 8. B = 22 Hz to 22 kHz; independent of Rs. 9. Vi = Vi(max) = 1 V (RMS); fi = 1 kHz; maximum limit is guaranteed, but may not be 100% tested. output signal in mute common mode rejection ratio note 9 Vi(CM) = 1 V (RMS) − − − − − 280 300 280 − 75 560 − − 500 − µV µV µV µV dB − 36 − − 22 49 44 49 80 34 − − − − − dB dB dB dB kΩ − − 35 85 0.015 0.02 36 90 0.05 − 37 − % % dB % 37 46 40 50 − − W W MIN. TYP. MAX. UNIT 2003 Mar 20 15 Philips Semiconductors Objective specification 2 × 25 W class-D power amplifier 16 APPLICATION INFORMATION 16.1 BTL application BTL: P o(1%) TDA8922 2 RL --------------------- × 2V P × ( 1 – t min × f osc ) R L + 1.2 = --------------------------------------------------------------------------------------------2 × RL When using the power amplifier in a mono BTL application (for more output power), the inputs of both channels must be connected in parallel and the phase of one of the inputs must be inverted (see Fig.6). In principle the loudspeaker can be connected between the outputs of the two single-ended demodulation filters. 16.2 Pin MODE Maximum current: 2V P × ( 1 – t min × f osc ) I o(peak) = -------------------------------------------------------- should not exceed 4 A. R L + 1.2 Legend: RL = load impedance fosc = oscillator frequency tmin = minimum pulse width (typical 190 ns) VP = single-sided supply voltage (so, if supply is ±30 V symmetrical, then VP = 30 V) Po(1%) = output power just at clipping Po(10%) = output power at THD = 10% Po(10%) = 1.25 × Po(1%). 16.4 External clock For correct operation the switching voltage at pin MODE should be debounced. If pin MODE is driven by a mechanical switch an appropriate debouncing low-pass filter should be used. If pin MODE is driven by an electronic circuit or microcontroller then it should remain at the mute voltage level for at least 100 ms before switching back to the standby voltage level. 16.3 Output power estimation The output power in several applications (SE and BTL) can be estimated using the following expressions: 2 RL --------------------- × V P × ( 1 – t min × f osc ) R L + 0.6 = ----------------------------------------------------------------------------------------2 × RL SE: P o(1%) The minimum required symmetrical supply voltage for external clock application is ±15 V (equally, the minimum asymmetrical supply voltage for applications with an external clock is 30 V). When using an external clock the following accuracy of the duty cycle of the external clock has to be taken into account: 47.5% < δ < 52.5%. A possible solution for an external clock oscillator circuit is illustrated in Fig.8. Maximum current: V P × ( 1 – t min × f osc ) I o(peak) = ---------------------------------------------------- should not exceed 4 A. R L + 0.6 handbook, full pagewidth VDDA 2 kΩ 0− 0+ 11 10 CTC 120 pF RTC 9.1 kΩ RCTC 2 1 ASTAB− 4 5 ASTAB+ 6 −TRIGGER VDD 360 kHz 320 kHz HOP 220 nF 5.6 V 14 HEF4047BT 7 VSS 3 4.3 V 13 8 +TRIGGER 9 MR 12 RETRIGGER CLOCK GND MBL468 Fig.8 External oscillator circuit. 2003 Mar 20 16 Philips Semiconductors Objective specification 2 × 25 W class-D power amplifier 16.5 Heatsink requirements handbook, halfpage TDA8922 In some applications it may be necessary to connect an external heatsink to the TDA8922. The determining factor is the 150 °C maximum junction temperature Tj(max) which cannot be exceeded. The expression below shows the relationship between the maximum allowable power dissipation and the total thermal resistance from junction to ambient: T j(max) – T amb R th(j-a) = ---------------------------------P diss 30 MBL469 Pdiss (W) (1) 20 (2) 10 Pdiss is determined by the efficiency (η) of the TDA8922. The efficiency measured in the TDA8922 as a function of output power is given in Fig.19. The power dissipation can be derived as function of output power (see Fig.18). The derating curves (given for several values of the Rth(j-a)) are illustrated in Fig.9. A maximum junction temperature Tj = 150 °C is taken into account. From Fig.9 the maximum allowable power dissipation for a given heatsink size can be derived or the required heatsink size can be determined at a required dissipation level. Example 1: Po = 2 × 25 W into 8 Ω Tj(max) = 150 °C Tamb = 60 °C Pdiss(tot) = 4.2 W (from Fig.18) The required Rth(j-a) = 21.4 K/W can be calculated. The Rth(j-a) of the TDA8922 in free air is 35 K/W; the Rth(j-c) of the TDA8922 is 1.3 K/W, thus a heatsink of 20.1 K/W is required for this example. In actual applications, other factors such as the average power dissipation with music source (as opposed to a continuous sine wave) will determine the size of the heatsink required. Example 2: Po = 2 × 25 W into 4 Ω Tj(max) = 150 °C Tamb = 60 °C Pdiss(tot) = 5.5 W (from Fig.18) The required Rth(j-a) = 16.4 K/W. The Rth(j-a) of the TDA8922 in free air is 35 K/W; the Rth(j-c) of the TDA8922 is 1.3 K/W, thus a heatsink of 15.1 K/W is required for this example. 16.6 (3) (4) (5) 0 0 20 40 60 100 80 Tamb (°C) (1) (2) (3) (4) (5) Rth(j-a) = 5 K/W. Rth(j-a) = 10 K/W. Rth(j-a) = 15 K/W. Rth(j-a) = 20 K/W. Rth(j-a) = 35 K/W. Fig.9 Derating curves for power dissipation as a function of maximum ambient temperature. Output current limiting To guarantee the robustness of the class-D amplifier the maximum output current which can be delivered by the output stage is limited. An overcurrent protection is included for each output power switch. When the current flowing through any of the power switches exceeds a defined internal threshold (e.g. in case of a short-circuit to the supply lines or a short-circuit across the load), the amplifier will shut down immediately and an internal timer will be started. After a fixed time (e.g. 100 ms) the amplifier is switched on again. If the requested output current is still too high the amplifier will switch-off again. Thus the amplifier will try to switch to the operating mode every 100 ms. The average dissipation will be low in this situation because of this low duty cycle. If the overcurrent condition is removed the amplifier will remain operating. Because the duty cycle is low the amplifier will be switched off for a relatively long period of time which will be noticed as a so-called audio-hole; an audible interruption in the output signal. 2003 Mar 20 17 Philips Semiconductors Objective specification 2 × 25 W class-D power amplifier To trigger the maximum current protection in the TDA8922, the required output current must exceed 4 A. This situation occurs in case of: • Short-circuits from any output terminal to the supply lines (VDD or VSS) • Short-circuit across the load or speaker impedances or a load impedance below the specified values of 4 and 8 Ω. Even if load impedances are connected to the amplifier outputs which have an impedance rating of 4 Ω, this impedance can be lower due to the frequency characteristic of the loudspeaker; practical loudspeaker impedances can be modelled as an RLC network which will have a specific frequency characteristic: the impedance at the output of the amplifier will vary with the input frequency. A high supply voltage in combination with a low impedance will result in large current requirements. Another factor which must be taken into account is the ripple current which will also flow through the output power switches. This ripple current depends on the inductor values which are used, supply voltage, oscillator frequency, duty factor and minimum pulse width. The maximum available output current to drive the load impedance can be calculated by subtracting the ripple current from the maximum repetitive peak current in the output pin, which is 4 A for the TDA8922. As a rule of thumb the following expressions can be used to determine the minimum allowed load impedance without generating audio holes: V P × ( 1 – t min × f osc ) Z L ≥ ---------------------------------------------------- – 0.6 for SE application. I ORM – I ripple 2V P × ( 1 – t min × f osc ) Z L ≥ -------------------------------------------------------- – 1.2 for BTL application. I ORM – I ripple Where: ZL = load impedance fosc = oscillator frequency tmin = minimum pulse width (typical 190 ns) VP = single-sided supply voltage (so, if the supply is ±30 V symmetrical, then VP = 30 V) IORM = maximum repetitive peak current in output pin; see also Chapter 9 Iripple = ripple current. See the application notes (tbf) for a more detailed description of the implications of output current limiting. 16.7 Pumping effects TDA8922 The TDA8922 class-D amplifier is supplied by a symmetrical voltage (e.g VDD = +25 V and VSS = −25 V). When the amplifier is used in a SE configuration, a so-called ‘pumping effect’ can occur. During one switching interval, energy is taken from one supply (e.g. VDD), while a part of that energy is delivered back to the other supply line (e.g. VSS) and visa versa. When the voltage supply source cannot sink energy, the voltage across the output capacitors of that voltage supply source will increase: the supply voltage is pumped to higher levels. The voltage increase caused by the pumping effect depends on: • Speaker impedance • Supply voltage • Audio signal frequency • Capacitor value present on supply lines • Source and sink currents of other channels. The pumping effect should not cause a malfunction of either the audio amplifier and/or the voltage supply source. For instance, this malfunction can be caused by triggering of the undervoltage or overvoltage protection or unbalance protection of the amplifier. See the application notes (tbf) for a more detailed description of the implications of output current limiting. 16.8 Reference design The reference design for a single-chip class-D audio amplifier using the TDA8922TH is illustrated in Fig.10. The Printed-Circuit Board (PCB) layout is shown in Fig.11. The Bill Of Materials (BOM) is given in Table 1. 16.9 PCB information for HSOP24 package The size of the PCB is 74.3 × 59.10 mm, dual sided 35 µm copper with 121 metallized through holes. The standard configuration has a symmetrical supply (typical ±20 V) with stereo SE outputs (typical 2 × 8 Ω). The PCB is also suitable for a mono BTL configuration (1 × 8 Ω) with symmetrical and asymmetrical supply. It is possible to use several different output filter inductors such as 16RHBP or EP13 types to evaluate the performance against the price or size. 16.10 Classification The application shows optimized signal and EMI performance. 2003 Mar 20 18 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... agewidth 2003 Mar 20 19 Philips Semiconductors 2 × 25 W class-D power amplifier VDD +25 V C6 100 nF R1(3) 10 kΩ R2(3) 9.1 kΩ L1 BEAD C1 470 µF L2 BEAD L3 BEAD C4 47 µF L4 BEAD C5 47 µF VDDA C2 470 µF C3 47 µF VSSP VDDP GND C7 100 nF VSS −25 V VDDA R3 39 kΩ on mute C8 220 nF off Z1 5.6 V R4 39 kΩ S1 VSSA VDDA VSSA C12 100 nF VSSA VDDP C13 100 nF VSSP C15 100 nF C10 100 nF C11 220 nF C9 220 nF R5 30 kΩ C14 220 nF R6 C16 5.6 kΩ 470 nF in 1 R7 5.6 kΩ C17 470 nF J1 J3 J2 (4) VDDA1 IN1+ C20 330 pF 10 8 VSSA1 12 7 OSC 6 MODE VDDP1 14 17 VSSP1 C24 560 pF BOOT1 C22 15 nF 16 OUT1 L5 27 µH L6 27 µH R11 4.7 Ω R13 22 Ω C29 220 nF C31 15 nF OUT2+ SGND R10 4.7 Ω C26 470 nF C28 220 nF R12 22 Ω C30 15 nF OUT1+ (2) SGND OUT1− SE 4 Ω 15 IN1− 9 SGND1 SGND J4(1) SGND2 11 TDA8922TH 2 21 IN2+ C21 330 pF 5 22 4 1 VSSA2 3 VDDA2 24 VSSD C32 220 nF C34 C35 C36 100 nF 220 nF 100 nF VSSA VDDA 18 STABI C33 47 pF C37 C38 C39 100 nF 220 nF 100 nF VDDP VSSP 13 PROT 19 HW 23 VDDP2 20 VSSP2 OUT2 C23 15 nF BOOT2 BTL 8 Ω C18 470 nF OUT2− SE 4 Ω R8 5.6 kΩ in 2 R9 C19 5.6 kΩ 470 nF IN2− C27 470 nF C25 560 pF MGU997 VSSP Objective specification Every decoupling to ground (plane) must be made as close as possible to the pin. To handle 20 Hz under all conditions in stereo SE mode, the external power supply needs to have a capacitance of at least 4700 µF per supply line; VP = ±27 V (max). (1) (2) (3) (4) BTL: remove In2, R8, R9, C18, C19, C21 and close J3 and J4. BTL: connect loudspeaker between OUT1+ and OUT2−. BTL: R1 and R2 are only required when an asymmetrical supply is used (VSS = 0 V). In case of hum, close J1 and J2. TDA8922 Fig.10 Single-chip class-D audio amplifier application diagram (reference design for SE and BTL). Philips Semiconductors Objective specification 2 × 25 W class-D power amplifier TDA8922 handbook, full pagewidth PCB version 4 C1 L6 C38 C3 U1 C2 C14 L5 C33 C5 C27 C26 L3 L1 L2 L4 1-2002 C35 C21 C8 C20 C11 J4 C4 C17 C16 C18 J3 Z1 C19 On − Out2 + − Out1+ S1 VDD GND VSS Off TDA8920/21/22/23/24TH state of D art In1 In2 Top silk screen Top copper C34 C25 R11 C23 C22 C37 C9 C36 C39 C32 C10 C15 R5 C13 C12 C24 R10 R3 R8 R4 R9 R7 R6 C7 R2 C6 R1 C30 R12 C28 R13 C29 C31 J2 J1 PHILIPS SEMICONDUCTORS Bottom silk screen Bottom copper MBL496 Fig.11 Printed-circuit board layout for the TDA8922TH. 2003 Mar 20 20 Philips Semiconductors Objective specification 2 × 25 W class-D power amplifier 16.11 Bill of materials for reference design Table 1 TDA8922 Single-chip class-D audio amplifier printed-circuit board (PCB version 4; 1-2002) for TDA8922TH (see Figs 10 and 11). REFERENCE U1 in1 and in2 out1 and out2 VDD, GND and VSS L6 and L5 L1, L2, L3 and L4 S1 Z1 C1 and C2 C3, C4 and C5 PART TDA8922TH cinch inputs output connector supply connector 27 µH BEAD PCB switch 5V6 470 µF; 35 V 47 µF; 63 V DESCRIPTION Philips Semiconductors B.V. Farnell 152-396 Augat 5KEV-02 Augat 5KEV-03 EP13 or 16RHBP Murata BL01RN1-A62 Knitter ATE1E M-O-M BZX 79C5V6 DO-35 Panasonic M series ECA1VM471 Panasonic NHG series ECA1JHG470 MKT EPCOS B32529-C474-K SMD 1206 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 1206 SMD 0805 SMD 0805 SMD 2512 SMD 1206 BOM ITEM QUANTITY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 2 2 1 2 4 1 1 2 3 6 9 10 2 4 2 1 2 1 1 1 4 2 2 2 2 1 1 C16, C17, C18, C19, C26 and 470 nF; 63 V C27 C8, C9, C11, C14, C28, C29, C32, C35 and C38 C6, C7, C10, C12, C13, C15, C34, C36, C37 and C39 C20 and C21 C22, C23, C30 and C31 C24, C25 C33 R4 and R3 R5 R1 R2 R6, R7, R8 and R9 R13 and R12 R10 and R11 J1 and J2 J3 and J4 heatsink printed-circuit board material 220 nF; 63 V 100 nF; 50 V 330 pF; 50 V 15 nF; 50 V 560 pF; 100 V 47 pF; 25V 39 kΩ; 0.1 W 30 kΩ; 0.1 W 10 kΩ; 0.1 W; optional 5.6 kΩ; 0.1 W 22 Ω; 1 W 4.7 Ω; 0.25 W 9.1 kΩ; 0.1 W; optional SMD 0805 solder dot jumpers for ground reference in case of hum (60 Hz noise) wire jumpers for BTL application 30 mm SK400; OK for maximum music dissipation; 1/8 Prated (2 × 75 W/8) in 2 × 4 Ω at Tamb = 70 °C 1.6 mm thick epoxy FR4 material, double sided 35 µm copper; clearances 300 µm; minimum copper track 400 µm 2003 Mar 20 21 Philips Semiconductors Objective specification 2 × 25 W class-D power amplifier 16.12 Curves measured in reference design The curves illustrated in Figs 20 and 21 are measured with a specified load impedance. Spread in ZL (e.g. due to the frequency characteristics of the loudspeaker) can trigger the maximum current protection circuit; see Section 16.6. TDA8922 The curves illustrated in Figs 30 and 31 show the effects of supply pumping when only one single-ended channel is driven with a low frequency signal; see Section 16.7. 102 handbook, halfpage THD + N (%) 10 MGX324 102 handbook, halfpage THD + N (%) 10 MGX327 1 1 10 −1 (1) 10 −1 (1) (2) 10 −2 (3) 10 −2 (2) 10 −3 10 −2 10 −1 1 10 Po (W) 102 10 −3 10 102 103 104 f i (Hz) 105 2 × 8 Ω SE; VP = ±20 V. (1) 10 kHz. (2) 1 kHz. (3) 100 Hz. 2 × 8 Ω SE; VP = ±20 V. (1) Po = 10 W. (2) Po = 1 W. Fig.12 THD + N as a function of output power. Fig.13 THD + N as a function of input frequency. 2003 Mar 20 22 Philips Semiconductors Objective specification 2 × 25 W class-D power amplifier TDA8922 102 handbook, halfpage THD + N (%) 10 MGX325 102 handbook, halfpage THD + N (%) 10 MGX328 1 1 10 −1 (1) 10 −1 (1) (2) 10 −2 (3) 10 −2 (2) 10 −3 10 −2 10 −1 1 10 Po (W) 102 10 −3 10 102 103 104 f i (Hz) 105 2 × 4 Ω SE; VP = ±15 V. (1) 10 kHz. (2) 1 kHz. (3) 100 Hz. 2 × 4 Ω SE; VP = ±15 V. (1) Po = 10 W. (2) Po = 1 W. Fig.14 THD + N as a function of output power. Fig.15 THD + N as a function of input frequency. 102 handbook, halfpage THD + N (%) 10 MGX326 102 handbook, halfpage THD + N (%) 10 MGX329 1 1 10 −1 (1) (2) 10 −1 (1) (2) 10 −2 (3) 10 −2 10 −3 10 −2 10 −1 1 10 Po (W) 102 10 −3 10 102 103 104 f i (Hz) 105 1 × 8 Ω BTL; VP = ±15 V. (1) 10 kHz. (2) 1 kHz. (3) 100 Hz. 1 × 8 Ω BTL; VP = ±15 V. (1) Po = 10 W. (2) Po = 1 W. Fig.16 THD + N as a function of output power. Fig.17 THD + N as a function of input frequency. 2003 Mar 20 23 Philips Semiconductors Objective specification 2 × 25 W class-D power amplifier TDA8922 handbook, halfpage 10 MGX332 Pdiss (W) handbook, halfpage 100 MGX333 η (1) (2) (3) (%) 8 80 6 (1) 60 (2) 4 (3) 40 2 20 0 10 −2 10 −1 1 10 Po (W) 102 0 0 20 40 60 80 100 Po (W) fi = 1 kHz. (1) 2 × 4 Ω SE, VP = ±15 V. (2) 2 × 8 Ω SE, VP = ±20 V. (3) 1 × 8 Ω BTL, VP = ±15 V. fi = 1 kHz. (1) 2 × 8 Ω SE, VP = ±20 V. (2) 2 × 4 Ω SE, VP = ±15 V. (3) 1 × 8 Ω BTL, VP = ±15 V. Fig.18 Power dissipation as a function of output power. Fig.19 Efficiency as a function of output power. MGX336 handbook, halfpage 100 handbook, halfpage 100 MGX337 Po (W) 80 (1) Po (W) 80 (1) 60 (3) 60 (2) (3) 40 (2) 40 20 20 0 10 15 20 25 30 35 VDD (V) 0 10 15 20 25 30 35 VDD (V) THD + N = 0.5%; fi = 1 kHz. (1) 1 × 8 Ω BTL. (2) 2 × 4 Ω SE. (3) 2 × 8 Ω SE. THD + N = 10%; fi = 1 kHz. (1) 1 × 8 Ω BTL. (2) 2 × 4 Ω SE. (3) 2 × 8 Ω SE. Fig.20 Output power as a function of supply voltage. Fig.21 Output power as a function of supply voltage. 2003 Mar 20 24 Philips Semiconductors Objective specification 2 × 25 W class-D power amplifier TDA8922 handbook, halfpage αcs 0 MGX330 handbook, halfpage αcs 0 MGX331 (dB) − 20 (dB) − 20 − 40 − 40 − 60 − 60 (1) − 80 (1) (2) − 80 (2) − 100 10 102 103 104 f i (Hz) 105 − 100 10 102 103 104 f i (Hz) 105 2 × 8 Ω SE; VP = ±20 V. (1) Po = 1 W. (2) Po = 10 W. 2 × 4 Ω SE; VP = ±15 V. (1) Po = 1 W. (2) Po = 10 W. Fig.22 Channel separation as a function of input frequency. Fig.23 Channel separation as a function of input frequency. handbook, halfpage 40 MGX340 handbook, halfpage 40 MGX341 G (dB) 35 (1) G (dB) 35 (1) (2) 30 (2) 30 (3) (3) 25 25 20 10 102 103 104 f i (Hz) 105 20 10 102 103 104 f i (Hz) 105 Vi = 100 mV; Rs = 5.6 kΩ; Ci = 330 pF. (1) 1 × 8 Ω BTL, VP = ±15 V. (2) 2 × 8 Ω SE, VP = ±20 V. (3) 2 × 4 Ω SE, VP = ±15 V. Vi = 100 mV; Rs = 0 kΩ. (1) 1 × 8 Ω BTL, VP = ±15 V. (2) 2 × 8 Ω SE, VP = ±20 V. (3) 2 × 4 Ω SE, VP = ±15 V. Fig.24 Gain as a function of input frequency. Fig.25 Gain as a function of input frequency. 2003 Mar 20 25 Philips Semiconductors Objective specification 2 × 25 W class-D power amplifier TDA8922 handbook, halfpage 100 MGX338 handbook, halfpage 320 MGX339 Iq (mA) 80 fclk (kHz) 310 60 40 300 20 0 0 5 10 15 20 25 30 VDD (V) 35 290 0 5 10 15 20 25 30 35 VDD (V) RL = ∞. RL = ∞. Fig.26 Quiescent current as a function of supply voltage. Fig.27 Clock frequency as a function of supply voltage. handbook, halfpage 0 MGX346 handbook, halfpage 0 MGX347 SVRR (dB) − 20 (1) SVRR) (dB) − 20 − 40 (2) (3) − 40 (1) − 60 − 60 (2) (3) − 80 − 80 − 100 10 102 103 104 f i (Hz) 105 − 100 0 1 2 3 4 5 Vripple(p-p) (V) VP = ±20 V; Vripple = 2 V (p-p) with respect to ground. (1) Both supply lines in phase. (2) Both supply lines in anti-phase. (3) One supply line rippled. VP = ±20 V; Vripple with respect to ground (in phase). (1) fripple = 1 kHz. (2) fripple = 100 Hz. (3) fripple = 10 Hz. Fig.28 SVRR as a function of input frequency. Fig.29 SVRR as a function of Vripple(p-p). 2003 Mar 20 26 Philips Semiconductors Objective specification 2 × 25 W class-D power amplifier TDA8922 handbook, halfpage 10 MGX334 Vripple(p-p) (V) 8 Vripple(p-p) (V) 8 handbook, halfpage 10 MGX335 6 (1) 6 4 4 (1) 2 (2) 2 (2) 0 10 −2 10 −1 1 10 Po (W) 102 0 10 102 103 f i (Hz) 104 3000 µF per supply line; fi = 10 Hz. (1) 1 × 4 Ω SE, VP = ±15 V. (2) 1 × 8 Ω SE, VP = ±20 V. 3000 µF per supply line. (1) Po = 10 W into 1 × 4 Ω SE, VP = ±15 V. (2) Po = 10 W into 1 × 8 Ω SE, VP = ±20 V. Fig.30 Supply voltage ripple as a function of output power. Fig.31 Supply voltage ripple as a function of input frequency. handbook, halfpage 10 MGX342 handbook, halfpage 150 MGX344 THD + N (%) 1 (1) Iq (mA) 120 90 10 −1 (2) 60 10 −2 (3) 30 10 −3 100 200 300 400 500 fclk (kHz) 600 0 100 200 300 400 500 fclk (kHz) 600 VP = ±20 V; Po = 1 W into 8 Ω. (1) 10 kHz. (2) 1 kHz. (3) 100 Hz. VP = ±20 V; RL = ∞. Fig.32 THD + N as a function of clock frequency. Fig.33 Quiescent current as a function of clock frequency. 2003 Mar 20 27 Philips Semiconductors Objective specification 2 × 25 W class-D power amplifier TDA8922 handbook, halfpage 1000 MGX345 handbook, halfpage 50 MGX343 Vres(rms) (mV) 800 Po (W) 40 600 30 400 20 200 10 0 100 200 300 400 500 fclk (kHz) 600 0 100 200 300 400 500 fclk (kHz) 600 VP = ±20 V; RL = 8 Ω. VP = ±20 V; RL = 8 Ω; fi = 1 kHz; THD + N = 10%. Fig.34 PWM residual voltage as a function of clock frequency. Fig.35 Output power as a function of clock frequency. handbook, halfpage 10 MGX348 handbook, halfpage Vo (V) 1 10 −1 120 S/N (dB) 100 MGX349 80 10 −2 60 10 −3 10 −4 10 −5 10 −6 40 (1) (2) 20 0 1 2 3 4 5 6 VMODE (V) 0 10 −2 10 −1 1 10 102 103 Po (W) Vi = 100 mV; fi = 1 kHz. VP = ±20 V; Rs = 5.6 kΩ.; filter: 20 kHz AES17 (1) 2 × 8 Ω SE. (2) 1 × 8 Ω BTL. Fig.36 Output voltage as a function of mode selection voltage. Fig.36 Signal-to-noise ratio as a function of output power. 2003 Mar 20 28 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2003 Mar 20 VDDA STABI PROT 18 RFB IN1− 9 Vin1 IN1+ 8 SGND1 11 COSC VSSA ROSC Vmode OSC 7 OSCILLATOR MODE 6 MODE MANAGER TEMPERATURE SENSOR CURRENT PROTECTION INPUT STAGE PWM MODULATOR RELEASE1 CONTROL AND ENABLE1 HANDSHAKE SWITCH1 DRIVER HIGH 16 DRIVER LOW VSSP1 OUT1 13 VDDA2 3 VDDA1 10 SGND mute STABI 16.13 Application schematics Philips Semiconductors handbook, full pagewidth 2 × 25 W class-D power amplifier VDDP VDDA +25 V VDDP2 23 VDDP1 14 15 BOOT1 29 TDA8922TH VDDP2 22 BOOT2 SGND 0V 21 SGND Vin2 SGND2 2 IN2 + 5 IN2 − 4 mute ENABLE2 CONTROL SWITCH2 AND HANDSHAKE RELEASE2 DRIVER HIGH OUT2 INPUT STAGE PWM MODULATOR DRIVER LOW 1 VSSA2 VSSA 12 VSSA1 RFB 24 VSSD VSSA 19 HW 17 VSSP1 20 VSSP2 −25 V VSSA Objective specification VSSP MGU998 TDA8922 Fig.37 Typical SE application schematic of TDA8922TH. This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2003 Mar 20 VDDA STABI PROT 12 RFB IN1− 3 Vin1 IN1+ 2 SGND1 5 COSC VSSA ROSC Vmode OSC 1 OSCILLATOR MODE 23 MODE MANAGER TEMPERATURE SENSOR CURRENT PROTECTION INPUT STAGE PWM MODULATOR RELEASE1 CONTROL AND ENABLE1 HANDSHAKE SWITCH1 DRIVER HIGH 10 DRIVER LOW VSSP1 OUT1 7 VDDA2 20 VDDA1 4 SGND mute STABI Philips Semiconductors handbook, full pagewidth 2 × 25 W class-D power amplifier VDDP VDDA +25 V VDDP2 16 VDDP1 8 9 BOOT1 30 TDA8922J VDDP2 15 BOOT2 SGND 0V 14 SGND Vin2 SGND2 19 IN2 + 22 IN2 − 21 mute ENABLE2 CONTROL SWITCH2 AND HANDSHAKE RELEASE2 DRIVER HIGH OUT2 INPUT STAGE PWM MODULATOR DRIVER LOW 18 VSSA2 VSSA 6 VSSA1 RFB 17 VSSD VSSA 11 VSSP1 13 VSSP2 −25 V VSSA Objective specification VSSP MGU999 TDA8922 Fig.38 Typical SE application schematic of TDA8922J. Philips Semiconductors Objective specification 2 × 25 W class-D power amplifier 17 PACKAGE OUTLINES HSOP24: plastic, heatsink small outline package; 24 leads; low stand-off height TDA8922 SOT566-3 E D x A X c y E2 HE vM A D1 D2 1 pin 1 index Q A2 E1 A4 Lp detail X 24 Z e bp 13 wM (A3) θ A 12 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A A2 max. 3.5 3.5 3.2 A3 0.35 A4(1) bp c D(2) D1 D2 1.1 0.9 E(2) 11.1 10.9 E1 6.2 5.8 E2 2.9 2.5 e 1 HE 14.5 13.9 Lp 1.1 0.8 Q 1.7 1.5 v w x y Z 2.7 2.2 θ 8° 0° +0.08 0.53 0.32 16.0 13.0 −0.04 0.40 0.23 15.8 12.6 0.25 0.25 0.03 0.07 Notes 1. Limits per individual lead. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT566-3 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-30 03-02-18 2003 Mar 20 31 Philips Semiconductors Objective specification 2 × 25 W class-D power amplifier TDA8922 DBS23P: plastic DIL-bent-SIL power package; 23 leads (straight lead length 3.2 mm) SOT411-1 non-concave x D Dh Eh view B: mounting base side A2 d β A5 A4 B j E2 E E1 L2 L1 L3 L 1 Z e e1 wM 23 Q m c e2 vM bp 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT A 2 mm A4 A5 bp c D (1) d D h E (1) e e1 e2 Eh E1 E2 j L L1 L2 L3 m Q v w x β Z (1) 12.2 4.6 1.15 1.65 0.75 0.55 30.4 28.0 12 2.54 1.27 5.08 11.8 4.3 0.85 1.35 0.60 0.35 29.9 27.5 6 10.15 6.2 1.85 3.6 9.85 5.8 1.65 2.8 14 10.7 2.4 1.43 2.1 4.3 0.6 0.25 0.03 45° 13 9.9 1.6 0.78 1.8 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT411-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 98-02-20 02-04-24 2003 Mar 20 32 Philips Semiconductors Objective specification 2 × 25 W class-D power amplifier 18 SOLDERING 18.1 Introduction 18.3.2 WAVE SOLDERING TDA8922 This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mount components are mixed on one printed-circuit board. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 18.2 18.2.1 Through-hole mount packages SOLDERING BY DIPPING OR BY SOLDER WAVE Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 18.3.3 MANUAL SOLDERING The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joints for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 18.2.2 MANUAL SOLDERING Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. 18.3 18.3.1 Surface mount packages REFLOW SOLDERING Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferably be kept: • below 220 °C for all the BGA packages and packages with a thickness 2.5mm and packages with a thickness