HEF4086BP

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4086B gates 4-wide 2-input AND-OR-invert gate Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification 4-wide 2-input AND-OR-invert gate DESCRIPTION The HEF4086B is a 4-wide 2-input AND-OR-invert (AOI) gate with two additional inputs (I8 or I9) which can be used as either expander or inhibit inputs by connecting them to any standard LOCMOS output. A HIGH on I8 or a LOW on I9 forces the output (O) LOW independent of the other eight inputs (I0 to I7). The output (O) is fully buffered for highest noise immunity and pattern insensitivity of output impedance. HEF4086B gates Fig.2 Pinning diagram. HEF4086BP(N): 14-lead DIL; plastic (SOT27-1) HEF4086BD(F): 14-lead DIL; ceramic (cerdip) (SOT73) HEF4086BT(D): 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America Fig.1 Functional diagram. PINNING I0 to I8 I9 O gate inputs gate input (active LOW) output (active LOW) FAMILY DATA, IDD LIMITS category GATES See Family Specifications January 1995 2 Philips Semiconductors Product specification 4-wide 2-input AND-OR-invert gate HEF4086B gates Fig.3 Logic diagram. LOGIC EQUATION O = I0 ⋅ I1 + I2 ⋅ I3 + I4 ⋅ I5 + I6 ⋅ I7 + I8 + I9 January 1995 3 Philips Semiconductors Product specification 4-wide 2-input AND-OR-invert gate AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Propagation delays I0 to I7 → O HIGH to LOW 5 10 15 5 LOW to HIGH I8 → O HIGH to LOW 10 15 5 10 15 5 LOW to HIGH I9 → O HIGH to LOW 10 15 5 10 15 5 LOW to HIGH Output transition times HIGH to LOW 10 15 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL tPLH tPHL tPLH tPHL tPLH tPHL 90 30 20 80 30 20 70 25 20 55 20 15 55 20 15 45 15 10 60 30 20 60 30 20 180 65 40 155 60 40 140 55 40 115 40 25 105 45 30 90 35 25 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL TYP. MAX. HEF4086B gates TYPICAL EXTRAPOLATION FORMULA 63 ns + (0,55 ns/pF) CL 19 ns + (0,23 ns/pF) CL 12 ns + (0,16 ns/pF) CL 53 ns + (0,55 ns/pF) CL 19 ns + (0,23 ns/pF) CL 12 ns + (0,16 ns/pF) CL 43 ns + (0,55 ns/pF) CL 14 ns + (0,23 ns/pF) CL 12 ns + (0,16 ns/pF) CL 28 ns + (0,55 ns/pF) CL 9 ns + (0,23 ns/pF) CL 7 ns + (0,16 ns/pF) CL 28 ns + (0,55 ns/pF) CL 9 ns + (0,23 ns/pF) CL 7 ns + (0,16 ns/pF) CL 18 ns + (0,55 ns/pF) CL 4 ns + (0,23 ns/pF) CL 2 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (µW) 525 fi + ∑ (foCL) × VDD2 2600 fi + ∑ (foCL) × VDD 7300 fi + ∑ (foCL) × VDD 2 2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 4 Philips Semiconductors Product specification 4-wide 2-input AND-OR-invert gate APPLICATION INFORMATION Figure 4 shows two HEF4086B ICs connected to obtain an 8-wide 2-input AOI function. The output (OA) of the first IC is fed directly into the I9B gate input of the second IC. Similarly, any NAND gate output can be fed directly into the I9 gate input to obtain a 5-wide AOI function. In addition, any AND gate output can be fed directly into the I8 gate input with the same result. HEF4086B gates Fig.4 Two HEF4086B ICs connected as an 8-wide 2-input AOI gate. Logic equation for Fig.4: O B = I 0A ⋅ I 1A + I 2A ⋅ I 3A + I 4A ⋅ I 5A + I 6A ⋅ I 7A + I 0B ⋅ I 1B + I 2B ⋅ I 3B + I 4B ⋅ I 5B + I 6B ⋅ I 7B January 1995 5