HEF4731BN

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4731B; HEF4731V LSI Quadruple 64-bit static shift register Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Quadruple 64-bit static shift register DESCRIPTION The HEF4731B and HEF4731V are quadruple 64-bit static shift registers each with separate serial data inputs (DA to DD), clock inputs (CPA to CPD) and data outputs (O63A to O63D) from the 64th register position. HEF4731B; HEF4731V LSI Recommended supply voltage range for HEF4731B is 3 to 15 V and for HEF4731V is 4,5 to 12,5 V. Data are shifted to the next stage on the negative-going transitions of the clock. Low impedance outputs are provided for direct interface to TTL. Fig.2 Pinning diagram. HEF4731BP; HEF4731VP(N): HEF4731BD; HEF4731VD(F): 14-lead DIL; plastic (SOT27-1) 14-lead DIL; ceramic (cerdip) (SOT73) ( ): Package Designator North America FAMILY DATA, IDD LIMITS category LSI Fig.1 Functional diagram. See Family Specifications January 1995 2 Philips Semiconductors Product specification Quadruple 64-bit static shift register HEF4731B; HEF4731V LSI Fig.3 Logic diagram (one of 64-bits shift register). The values given at VDD = 15 V in the following DC and AC characteristics, are not applicable to the HEF4731V, because of its reduced supply voltage range. DC CHARACTERISTICS VSS = 0 V; VI = VSS or VDD Tamb (°C) VDD V Output (source) current HIGH Output (sink) current LOW 5 5 10 15 4,75 10 15 0,4 0,5 1,5 IOL VOL V VOH V 2,5 4,6 9,5 13,5 −IOH SYMBOL −40 MIN. 3 1 3 10 2,3 6,0 20,0 MAX. + 25 MIN. 2,5 0,85 2,5 8,5 2,0 5,0 18,0 MAX. + 85 MIN. 2,0 0,65 2,0 6,5 1,6 4,0 14,0 MAX. mA mA mA mA mA mA mA AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (µW) 13 000 fi + ∑ (foCL) × VDD2 55 000 fi + ∑ (foCL) × VDD2 140 000 fi + ∑ (foCL) × VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 3 Philips Semiconductors Product specification Quadruple 64-bit static shift register AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Propagation delays CP → O63 HIGH to LOW 5 10 15 5 LOW to HIGH Transition times O63 HIGH to LOW 10 15 5 10 15 5 LOW to HIGH Minimum clock pulse width; HIGH Set-up time D → CP Hold time D → CP Maximum clock pulse frequency 10 15 5 10 15 5 10 15 5 10 15 5 10 15 fmax thold tsu tWCPH 200 75 50 25 15 15 50 30 20 2.25 6 9 tTLH tTHL tPLH tPHL 115 55 40 130 65 45 30 12 10 40 20 15 80 30 20 −5 −5 −5 20 10 5 6 16 25 230 ns 110 ns 80 ns 260 ns 130 ns 90 ns 60 ns 24 ns 20 ns 80 ns 40 ns 30 ns ns ns ns ns ns ns ns ns ns MHz MHz MHz SYMBOL MIN. TYP. MAX. HEF4731B; HEF4731V LSI TYPICAL EXTRAPOLATION FORMULA 132 ns + (0,26 ns/pF) CL 47 ns + (0,16 ns/pF) CL 34 ns + (0,11 ns/pF) CL 138 ns + (0,45 ns/pF) CL 56 ns + (0,19 ns/pF) CL 39 ns + (0,13 ns/pF) CL 10 ns + (0,40 ns/pF) CL 3 ns + (0,18 ns/pF) CL 3 ns + (0,13 ns/pF) CL 8 ns + (0,65 ns/pF) CL 5 ns + (0,30 ns/pF) CL 5 ns + (0,20 ns/pF) CL see also waveforms Fig.4 Note: the maximum power dissipation has to be observed Fig.4 Waveforms showing minimum clock pulse width, set-up and hold times for D to CP. Set-up and hold times are shown as positive values but may be specified as negative values. January 1995 4