HEF4755VP

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4755V LSI Transceiver for serial data communication Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Transceiver for serial data communication DESCRIPTION The HEF4755V transceiver is a circuit for serial data communication. It provides maximum transmission security and effectiveness. Therefore, in addition to the normal precautions, it contains a programmable digital bit-check, a programmable CRC (Cyclic Redundancy Check; Hamming distance 4 or 6) and format protection. The circuit has 8 possible operating modes: • synchronous – error checking only – receiving – transmitting – receiving with data out and transmitting the same message • asynchronous – error checking only – receiving – transmitting – receiving with data out and transmitting of a regenerated message. FEATURES • Transmission rate: SUPPLY VOLTAGE/CURRENT RATING VDD ISS −0,5 to +15 30 HEF4755V LSI RECOMMENDED OPERATING 4,75 to 12,6 − V mA FAMILY DATA, IDD LIMITS category LSI See Family Specification VDD 5V 7V 10 V SYNCHRONOUS 0,8 Mbaud 1,6 Mbaud 3,2 Mbaud ASYNCHRONOUS 31 kbaud 62 kbaud 125 kbaud • Inputs: standard LOCMOS • Outputs: TTL compatible (1 TTL load) • Operating ambient temperature range: −40 to + 85 °C • Transmit or receive a serial binary data stream • Start bit generation and recognition • Format protection and checking • Redundancy byte generation and checking • Digital bit check • Error recognition and error distinguishing • 8-bit parallel input/output transfer Fig.1 Pinning diagram. January 1995 2 Philips Semiconductors Product specification Transceiver for serial data communication HEF4755V LSI HEF4755VP(N): HEF4755VD(F): HEF4755VT(D): 28-lead DIL; plastic (SOT117-2) 28-lead DIL; ceramic (cerdip) (SOT135) 28-lead SO; plastic (SOT136-1) ( ): Package Designator North America PINNING 1 TST Test pin; during normal use connected to VSS. When TST is HIGH (VDD), internal check points are connected to the data bus. Input code for message length (see Table 1). 19 HD Hamming distance; determines the length of the redundancy byte: LOW = 7 bit (HD = 4) HIGH = 15 bit (HD = 6) Output message synchronization used in synchronous mode. Message output. Message input. Output data pulse; take-over pulse for data on the data bus. Output error; an active output means that at least 1 transmission error is recognized. Clock input; in synchronous mode equal to the transmission bit rate. Programming of the permissible time tolerance in bit distortion (see Table 3). Positive supply voltage; 4,5 V to 12,5 V (is the logic HIGH level). Ground (is the logic LOW level). 2 3 4 to 11 12 13 15 16 17 ML0 ML1 DIO0 to DIO7 RX TX AS R START 20 21 22 23 24 MOS MO MI DP ERR Bidirectional data bus. Mode input: receive; see Table 2 Mode input: transmit; see Table 2 Mode input: asynchronous; see Table 2 Reset; a positive signal resets all internal registers. Input start in transmitting mode; synchronization input (from MOS) in synchronous receiving mode. Output busy; active during receiving or transmitting a message. 25 26 27 28 14 CP TT1 TT0 VDD VSS 18 BUSY January 1995 3 Philips Semiconductors Product specification Transceiver for serial data communication Table 1 ML0 H L H L Table 2 RX L H L H Input code for message length ML1 H H L L MESSAGE LENGTH 6 data bytes 4 data bytes 2 data bytes variable length depends on format byte HEF4755V LSI Input code for input mode TX L L H H AS L L L L status register connected to the data bus for error recognition receiving in synchronous mode transmitting in synchronous mode receiving messages (without redundancy bit); data parallel out; calculating of redundancy byte; transmitting data with redundancy byte in synchronous mode only bit check in asynchronous mode; no data output on data bus receiving in asynchronous mode transmitting in asynchronous mode receiving and transmitting of a regenerated message in the asynchronous mode L H L H Table 3 TT1 L L H H Notes L L H H H H H H Permissible time tolerance in bit distortion TT0 L H L H PERMITTED DISTORTION (dt/T) 6/32 ≈ 19% 8/32 = 25% 10/32 ≈ 31% 12/32 ≈ 37% 1. H = HIGH state (the most positive voltage) 2. L = LOW state (the least positive voltage) January 1995 4 Philips Semiconductors Product specification Transceiver for serial data communication HEF4755V LSI (1) Only used in the asynchronous mode. Fig.2 Block diagram. Fig.3 Functional diagram. January 1995 5 Philips Semiconductors Product specification Transceiver for serial data communication FUNCTIONAL DESCRIPTION General The HEF4755V is used for protected-bit serial data communication. This protection makes it necessary to subdivide the serial data stream into data blocks called messages. Messages HEF4755V LSI In the synchronous mode the HEF4755V will transmit or receive a message as follows: The first bit of a transmitted message is the start-bit which cannot be mis interpreted. It instructs the receiver, that information transfer has started and it defines the time-window for the following bits. The start-bit is only necessary in the asynchronous mode and it is omitted in the synchronous mode. The first byte contains the number of data bytes that will follow. This byte is checked by the receiver and if a discrepancy is found, the receiver reports a code-error. This first byte is called ‘size’. The number of data bytes can also be fixed by wiring of the transmitter as well as the receiver. In this case the size byte is omitted. There is no protocol on the information of the data bytes, so the maximum number of informations per message is 256 ≈ 1017. The redundancy check byte secures the data bytes against transmission errors. This byte is calculated in The information is transmitted as follows: parallel to the data stream and it is send as last byte by the transmitter. The receiver calculates its own redundancy byte and compares it with the received one. If there is a discrepancy, the receiver reports a code error. Code protection Size The coding of the size byte is as follows: DIO0 = C DIO1 = B DIO2 = A DIO3 = P = C⊕B⊕A n = C ⋅ 22 + B ⋅ 21 + A ⋅ 20 With this, a hamming distance of 4 is obtained. January 1995 6 Philips Semiconductors Product specification Transceiver for serial data communication Redundancy byte The redundancy byte completes the data bytes with 15 (7) bits as a code word. If only one bit in the information has changed during the transmission, the two code words will differ by at least 6 (4) bit positions. So a change of up to 5 (3) bits will always be observed, even every odd number of false bits will be recognized. The HEF4755V has a programmable redundancy bit calculator which carries out this protection (the numbers given in parentheses are valid for the alternative possibility). If the transmission line carries extreme noise, this kind of message protection is less effective. In this case, the message is protected by checking bit-per-bit in a smaller time scale (see ‘bit protection’ below). Bit protection The HEF4755V checks every received bit within the time window defined by the start-bit. The programmed time tolerance (19%, 25%, 31% and 37%) determines that the bit protection circuit decides after 32 samples which bit is a true logic HIGH or LOW level, or an error. In the latter case, there are too many samples HIGH to obtain a LOW and, too many samples LOW to obtain a HIGH. Transmitting In the transmitting mode the HEF4755V uses the data pulse signal (DP, pin 23) to take 8 bits from the data bus. These parallel bits are shifted serially to the message output (MO). Receiving In the receiving mode the HEF4755V receives serial bits at the message input (MI). The circuit checks the message for transmission errors and, with every data pulse, 8 bits are transferred in parallel to the data bus. Every recognized error is stored and the error output is activated. The kind of error can be recognized by reading the status register over the data bus. HEF4755V LSI Asynchronous and synchronous mode If only one transmission line is available, then the receiver waits for the start-bit, synchronizes itself on the start bit and receives all the data bits of one message. This is called the asynchronous mode. By using 3 transmission lines, the circuit can go to the synchronous mode. In this case it is possible to transmit also the clock signal (CP) and message synchronization signal (MOS) in parallel with the data bits. The start bit and the bit check are omitted. In the synchronous mode the maximum transmission speed is 32 times the maximum speed in the asynchronous mode. In asynchronous receive mode a reset pulse is necessary between two messages. It is possible to derive this reset pulse from the busy signal by using hardware. The duration of the START-pulse at the transmitter must always be shorter than the message to be transferred. A good procedure for achieving this is to use the BUSY-signal to end the START-pulse. The recovery time between two messages must be at least two bit periods. During this time, the line must remain stable to prevent generation of an error. This must be ensured with external hardware/software. In the synchronous receive mode, the duration of the START-pulse at the transmitter must always be shorter than the message to be transferred. A good procedure for achieving this is to use the BUSY-signal to end the START-pulse. A continuous START-signal will cause malfunction. The recovery time between two messages must be at least one bit period. During this time, the message line must remain stable. A good way to achieve this is to use the trailing-edge of the BUSY-signal to generate a START-signal. In practice, if data is delivered to the transmitter fast enough, START can be BUSY. If the lines have different delays, the message line should have the longest delay. If it is not certain which line has the longest delay it is possible to phase-shift the clock signal of the receiver by inverting it. This is only possible with point-to-point lines. January 1995 7 Philips Semiconductors Product specification Transceiver for serial data communication DC CHARACTERISTICS VSS = 0 V; Tamb = −40 to + 85 °C; unless otherwise specified PARAMETER Outputs Output voltage LOW 4,75 to 12,6 4,75 Output voltage HIGH 4,75 to 12,6 4,75 Inputs/outputs VOL VOL VOH VOH − − VDD−1 VDD−1 − − − − − − 0,4 V 0,4 V V V VDD V SYMBOL MIN. TYP. MAX. UNIT HEF4755V LSI CONDITIONS IOL = 1,8 mA IOL = 2,3 mA Tamb = 25 °C −IOH = 1,1 mA −IOH = 1,4 mA Tamb = 25 °C As outputs Output voltage LOW 4,75 to 12,6 4,75 Output voltage HIGH 4,75 to 12,6 4,75 Output leakage current HIGH 12,6 12,6 LOW IOZH IOZH −IOZL −IOZL − − − − − − − − 20 µA 5 µA 20 µA 5 µA VOH = 12,6 V VOH = 12,6 V Tamb = 25 °C VOL = 0 V VOL = 0 V Tamb = 25 °C VOL VOL VOH VOH − − VDD−1 VDD−1 − − − − − − 0,4 V 0,4 V V V IOL = 1,8 mA IOL = 2,3 mA Tamb = 25 °C −IOH = 1,1 mA −IOH = 1,4 mA Tamb = 25 °C As inputs Input voltage LOW Input voltage HIGH 4,75 to 12,6 4,75 to 12,6 VIL VIH 0 0,7 VDD − − 0,3 VDD V VDD V January 1995 8 Philips Semiconductors Product specification Transceiver for serial data communication AC CHARACTERISTICS VSS = 0 V; Tamb = −40 to + 85 °C; unless otherwise specified PARAMETER Asynchronous mode Clock pulse width LOW HIGH START pulse width HIGH Set-up time Dn → CP Hold time CP → Dn Reset (R) pulse width HIGH Synchronous mode Clock pulse width LOW HIGH Set-up time START → CP Hold time CP → START Set-up time Dn → CP Hold time CP → Dn Reset (R) pulse width HIGH Note 1. Measured between output voltage levels of 0,8 V and 2 V. 5 10 5 10 5 10 5 10 5 10 5 10 5 10 tWCPL tWCPH tsu thold tsu thold tWRH 625 150 625 150 0,6 0,15 300 75 600 150 0 0 1 0,25 ns ns ns ns µs µs ns ns ns ns ns ns µs µs 5 10 5 10 5 10 5 10 5 10 5 10 tWCPL tWCPH tWSH tsu thold tWRH 500 125 500 125 0,9 0,22 1,4 0,35 0 0 1 0,25 ns ns ns ns µs µs µs µs µs µs µs µs VDD V SYMBOL MIN. TYP. MAX. UNIT HEF4755V LSI CONDITIONS AS at VDD AS at VSS January 1995 9 Philips Semiconductors Product specification Transceiver for serial data communication HEF4755V LSI Fig.6 Waveforms showing the clock, data and start timing. January 1995 10 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... January 1995 11 Fig.7 Function/timing diagram when using the HEF4755V in the asynchronous mode where the byte number per message is variable and the hamming distance is 4. Philips Semiconductors Transceiver for serial data communication HEF4755V LSI Product specification This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... January 1995 12 Fig.8 Function/timing diagram when using the HEF4755V in the asynchronous mode where the byte number per message is variable and the hamming distance is 4. Philips Semiconductors Transceiver for serial data communication HEF4755V LSI Product specification