IRF840

Philips Semiconductors Product specification PowerMOS transistor Avalanche energy rated FEATURES • Repetitive Avalanche Rated • Fast switching • High thermal cycling performance • Low thermal resistance g IRF840 SYMBOL d QUICK REFERENCE DATA VDSS = 500 V ID = 8.5 A RDS(ON) ≤ 0.85 Ω s GENERAL DESCRIPTION N-channel, enhancement mode field-effect power transistor, intended for use in off-line switched mode power supplies, T.V. and computer monitor power supplies, d.c. to d.c. converters, motor control circuits and general purpose switching applications. The IRF840 is supplied in the SOT78 (TO220AB) conventional leaded package. PINNING PIN 1 2 3 tab gate drain source drain DESCRIPTION SOT78 (TO220AB) tab 1 23 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Pulsed drain current Total dissipation Operating junction and storage temperature range CONDITIONS Tj = 25 ˚C to 150˚C Tj = 25 ˚C to 150˚C; RGS = 20 kΩ Tmb = 25 ˚C; VGS = 10 V Tmb = 100 ˚C; VGS = 10 V Tmb = 25 ˚C Tmb = 25 ˚C MIN. - 55 MAX. 500 500 ± 30 8.5 5.4 34 147 150 UNIT V V V A A A W ˚C AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS Non-repetitive avalanche energy CONDITIONS MIN. MAX. 531 UNIT mJ Unclamped inductive load, IAS = 7.4 A; tp = 0.22 ms; Tj prior to avalanche = 25˚C; VDD ≤ 50 V; RGS = 50 Ω; VGS = 10 V; refer to fig:17 Repetitive avalanche energy1 IAR = 8.5 A; tp = 2.5 µs; Tj prior to avalanche = 25˚C; RGS = 50 Ω; VGS = 10 V; refer to fig:18 Repetitive and non-repetitive avalanche current EAR IAS, IAR - 13 8.5 mJ A 1 pulse width and repetition rate limited by Tj max. March 1999 1 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Avalanche energy rated THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS MIN. in free air - IRF840 TYP. MAX. UNIT 60 0.85 K/W K/W ELECTRICAL CHARACTERISTICS Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER Drain-source breakdown voltage ∆V(BR)DSS / Drain-source breakdown ∆Tj voltage temperature coefficient RDS(ON) Drain-source on resistance VGS(TO) Gate threshold voltage gfs Forward transconductance IDSS Drain-source leakage current V(BR)DSS IGSS Qg(tot) Qgs Qgd td(on) tr td(off) tf Ld Ld Ls Ciss Coss Crss CONDITIONS VGS = 0 V; ID = 0.25 mA VDS = VGS; ID = 0.25 mA MIN. 500 2.0 3.5 TYP. MAX. UNIT 0.1 0.6 3.0 6 1 40 10 55 5.5 30 18 37 80 36 3.5 4.5 7.5 960 140 80 0.85 4.0 25 250 200 80 7 45 V %/K Ω V S µA µA nA nC nC nC ns ns ns ns nH nH nH pF pF pF VGS = 10 V; ID = 4.8 A VDS = VGS; ID = 0.25 mA VDS = 30 V; ID = 4.8 A VDS = 500 V; VGS = 0 V VDS = 400 V; VGS = 0 V; Tj = 125 ˚C Gate-source leakage current VGS = ±30 V; VDS = 0 V Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance ID = 8.5 A; VDD = 400 V; VGS = 10 V VDD = 250 V; RD = 30 Ω; RG = 9.1 Ω Measured from tab to centre of die Measured from drain lead to centre of die Measured from source lead to source bond pad VGS = 0 V; VDS = 25 V; f = 1 MHz SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS Tmb = 25˚C Tmb = 25˚C IS = 8.5 A; VGS = 0 V IS = 8.5 A; VGS = 0 V; dI/dt = 100 A/µs MIN. TYP. MAX. UNIT 440 6.4 8.5 34 1.2 A A V ns µC March 1999 2 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Avalanche energy rated IRF840 120 110 100 90 80 70 60 50 40 30 20 10 0 PD% Normalised Power Derating 1 Zth j-mb, Transient thermal impedance (K/W) D = 0.5 0.2 PHP6N60 0.1 0.1 0.05 0.02 0.01 single pulse P D tp D= tp T t T 0 20 40 60 80 100 Tmb / C 120 140 0.001 1us 10us 1ms 100us 10ms tp, pulse width (s) 100ms 1s Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) ID% Normalised Current Derating Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T PHP8N50 10 V 7V 6.5 V 6V 5.5 V 10 5V 5 0 VGS = 4.5 V 120 110 100 90 80 70 60 50 40 30 20 10 0 30 25 20 15 ID, Drain current (Amps) Tj = 25 C 0 20 40 60 80 Tmb / C 100 120 140 0 5 10 15 20 25 VDS, Drain-Source voltage (Volts) 30 Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 10 V ID / A S/ ID Fig.5. Typical output characteristics. ID = f(VDS); parameter VGS PHP8N50 Tj = 25 C 100 BUK457-500B 2 RDS(on), Drain-Source on resistance (Ohms) 4.5 V 5V 5.5 V VGS = 6 V 10 S RD (O N) = VD tp = 10 us 100 us 1.5 6.5 V 7V 1 10 V 1 ms 1 DC 10 ms 100 ms 0.5 0.1 1 10 100 VDS / V 1000 0 0 5 10 15 ID, Drain current (Amps) 20 25 Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp Fig.6. Typical on-state resistance. RDS(ON) = f(ID); parameter VGS March 1999 3 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Avalanche energy rated IRF840 25 ID, Drain current (Amps) VDS > ID x RDS(on)max PHP8N50 4 VGS(TO) / V max. 20 3 typ. 15 min. 2 10 1 5 Tj = 150 C 0 0 Tj = 25 C 0 2 4 6 VGS, Gate-Source voltage (Volts) 8 10 -60 -40 -20 0 20 40 60 Tj / C 80 100 120 140 Fig.7. Typical transfer characteristics. ID = f(VGS); parameter Tj gfs, Transconductance (S) VDS > ID x RDS(on)max Tj = 25 C 8 150 C 6 PHP8N50 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 0.25 mA; VDS = VGS ID / A SUB-THRESHOLD CONDUCTION 10 1E-01 1E-02 1E-03 2% typ 98 % 4 1E-04 2 1E-05 0 1E-06 0 5 10 15 ID, Drain current (A) 20 25 0 1 2 VGS / V 3 4 Fig.8. Typical transconductance. gfs = f(ID); parameter Tj a Normalised RDS(ON) = f(Tj) Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS PHP8N50 10000 Junction capacitances (pF) 2 Ciss 1000 1 100 Coss Crss 0 -60 -40 -20 0 20 40 60 Tj / C 80 100 120 140 10 1 10 100 VDS, Drain-Source voltage (Volts) 1000 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 4.25 A; VGS = 10 V Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz March 1999 4 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Avalanche energy rated IRF840 20 IF, Source-Drain diode current (Amps) VGS = 0 V PHP8N50 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Gate-source voltage, VGS (V) ID = 8.5A Tj = 25 C 100V VDD = 400 V 200V PHP8N50E 15 10 150 C 5 Tj = 25 C 0 20 40 Gate charge, QG (nC) 60 80 0 0 0.2 0.4 0.6 0.8 1 VSDS, Source-Drain voltage (Volts) 1.2 1.4 Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); parameter VDS Switching times (ns) VDD = 250 V VGS = 10 V RD = 30 Ohms Tj = 25 C PHP8N50 10 Fig.16. Source-Drain diode characteristic. IF = f(VSDS); parameter Tj 1000 Non-repetitive Avalanche current, IAS (A) 25 C Tj prior to avalanche = 125 C 100 td(off) 1 VDS tf tr td(on) 10 0 10 20 30 40 RG, Gate resistance (Ohms) 50 60 tp ID PHP8N50E 1E-05 1E-04 Avalanche time, tp (s) 1E-03 1E-02 0.1 1E-06 Fig.14. Typical switching times; td(on), tr, td(off), tf = f(RG) Fig.17. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tp); unclamped inductive load 1.15 1.1 1.05 Normalised Drain-source breakdown voltage V(BR)DSS @ Tj V(BR)DSS @ 25 C 10 Maximum Repetitive Avalanche Current, IAR (A) Tj prior to avalanche = 25 C 1 1 0.95 0.9 0.85 -100 125 C 0.1 PHP8N50E 0.01 1E-06 -50 0 50 Tj, Junction temperature (C) 100 150 1E-05 1E-04 Avalanche time, tp (s) 1E-03 1E-02 Fig.15. Normalised drain-source breakdown voltage; V(BR)DSS/V(BR)DSS 25 ˚C = f(Tj) Fig.18. Maximum permissible repetitive avalanche current (IAR) versus avalanche time (tp) March 1999 5 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Avalanche energy rated MECHANICAL DATA Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220 SOT78 IRF840 E P A A1 q D1 D L2(1) L1 Q L b1 1 2 3 b c e e 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 4.5 4.1 A1 1.39 1.27 b 0.9 0.7 b1 1.3 1.0 c 0.7 0.4 D 15.8 15.2 D1 6.4 5.9 E 10.3 9.7 e 2.54 L 15.0 13.5 L1 3.30 2.79 L2 max. 3.0 (1) P 3.8 3.6 q 3.0 2.7 Q 2.6 2.2 Note 1. Terminals in this zone are not tinned. OUTLINE VERSION SOT78 REFERENCES IEC JEDEC TO-220 EIAJ EUROPEAN PROJECTION ISSUE DATE 97-06-11 Fig.19. SOT78 (TO220AB); pin 2 connected to mounting base (Net mass:2g) Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to mounting instructions for SOT78 (TO220AB) package. 3. Epoxy meets UL94 V0 at 1/8". March 1999 6 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Avalanche energy rated DEFINITIONS Data sheet status Objective specification Product specification Limiting values IRF840 This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. © Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. March 1999 7 Rev 1.000