PCA9544A

INTEGRATED CIRCUITS PCA9544A 4-channel I2C multiplexer with interrupt logic Product data sheet Supersedes data of 2004 Jul 28 2004 Sep 29 Philips Semiconductors Philips Semiconductors Product data sheet 4-channel I2C multiplexer with interrupt logic PCA9544A DESCRIPTION The PCA9544A is a 1-of-4 bi-directional translating multiplexer, controlled via the I2C-bus. The SCL/SDA upstream pair fans out to four SCx/SDx downstream pairs, or channels. Only one SCx/SDx channel is selected at a time, determined by the contents of the programmable control register. Four interrupt inputs, INT0 to INT3, one for each of the SCx/SDx downstream pairs, are provided. One interrupt output, INT, which acts as an AND of the four interrupt inputs, is provided. FEATURES A power-on reset function puts the registers in their default state and initializes the I2C state machine with no channels selected. The pass gates of the multiplexer are constructed such that the VDD pin can be used to limit the maximum high voltage which will be passed by the PCA9544A. This allows the use of different bus voltages on each SCx/SDx pair, so that 1.8 V, 2.5 V or 3.3 V parts can communicate with 5 V parts without any additional protection. External pull-up resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5 V tolerant. • 1-of-4 bi-directional translating multiplexer • I2C interface logic; compatible with SMBus • 4 Active-LOW Interrupt Inputs • Active-LOW Interrupt Output • 3 address pins allowing up to 8 devices on the I2C-bus • Channel selection via I2C-bus • Power-up with all multiplexer channels deselected • Low RdsON switches • Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses • No glitch on power-up • Supports hot insertion • Low stand-by current • Operating power supply voltage range of 2.3 V to 5.5 V • 5 V tolerant Inputs • 0 to 400 kHz clock frequency • ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V per JESD22-C101 • Latchup testing is done to JESDEC Standard JESD78 which exceeds 100 mA • Three packages offered: SO20, TSSOP20, and HVQFN20 ORDERING INFORMATION PACKAGES 20-Pin Plastic SO 20-Pin Plastic TSSOP 20-Pin Plastic HVQFN TEMPERATURE RANGE –40 °C to +85 °C –40 °C to +85 °C –40 °C to +85 °C ORDER CODE PCA9544AD PCA9544APW PCA9544ABS TOPSIDE MARK PCA9544AD PA9544A 9544A DRAWING NUMBER SOT163-1 SOT360-1 SOT662-1 Standard packing quantities and other packaging data are available at www.standardproducts.philips.com/packaging. I2C is a trademark of Philips Semiconductors Corporation. 2004 Sep 29 2 Philips Semiconductors Product data sheet 4-channel I2C multiplexer with interrupt logic PCA9544A PIN CONFIGURATION — SO, TSSOP A0 1 A1 2 A2 3 INT0 4 SD0 5 SC0 6 INT1 7 SD1 8 SC1 9 VSS 10 20 VDD 19 SDA 18 SCL 17 INT 16 SC3 15 SD3 14 INT3 13 SC2 PIN CONFIGURATION — HVQFN A1 20 A0 VDD SDA SCL 19 18 17 16 15 INT 14 SC3 13 SD3 12 INT3 11 SC2 10 6 7 8 9 A2 INT0 SD0 SC0 INT1 1 2 3 4 5 12 SD2 11 INT2 SD1 SC1 VSS INT2 SD2 SW00373 TOP VIEW su01666 Figure 1. Pin configuration — SO, TSSOP Figure 2. Pin configuration — HVQFN PIN DESCRIPTION SO, TSSOP PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 HVQFN PIN NUMBER 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 SYMBOL A0 A1 A2 INT0 SD0 SC0 INT1 SD1 SC1 VSS INT2 SD2 SC2 INT3 SD3 SC3 INT SCL SDA VDD Address input 0 Address input 1 Address input 2 Active-LOW interrupt input 0 Serial data 0 Serial clock 0 Active-LOW interrupt input 1 Serial data 1 Serial clock 1 Supply ground Active-LOW interrupt input 2 Serial data 2 Serial clock 2 Active-LOW interrupt input 3 Serial data 3 Serial clock 3 Active-LOW interrupt output Serial clock line Serial data line Supply voltage FUNCTION 2004 Sep 29 3 Philips Semiconductors Product data sheet 4-channel I2C multiplexer with interrupt logic PCA9544A BLOCK DIAGRAM PCA9544A SC0 SC1 SC2 SC3 SD0 SD1 SD2 SD3 SWITCH CONTROL LOGIC VSS VDD POWER-ON RESET SCL INPUT FILTER I2C-BUS CONTROL A0 A1 A2 SDA INT[0–3] INT LOGIC INT SW02267 Figure 3. Block diagram 2004 Sep 29 4 Philips Semiconductors Product data sheet 4-channel I2C multiplexer with interrupt logic PCA9544A DEVICE ADDRESSING Following a START condition the bus master must output the address of the slave it is accessing. The address of the PCA9544A is shown in Figure 4. To conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW. INTERRUPT HANDLING The PCA9544A provides 4 interrupt inputs, one for each channel and one open drain interrupt output. When an interrupt is generated by any device, it will be detected by the PCA9544A and the interrupt output will be driven LOW. The channel need not be active for detection of the interrupt. A bit is also set in the control byte. Bits 4 – 7 of the control byte correspond to channels 0 – 3 of the PCA9544A, respectively. Therefore, if an interrupt is generated by any device connected to channel 2, the state of the interrupt inputs is loaded into the control register when a read is accomplished. Likewise, an interrupt on any device connected to channel 0 would cause bit 4 of the control register to be set on the read. The master can then address the PCA9544A and read the contents of the control byte to determine which channel contains the device generating the interrupt. The master can then reconfigure the PCA9544A to select this channel, and locate the device generating the interrupt and clear it. The interrupt clears when the device originating the interrupt clears. It should be noted that more than one device can be providing an interrupt on a channel, so it is up to the master to ensure that all devices on a channel are interrogated for an interrupt. The interrupt inputs may be used as general purpose inputs if the interrupt function is not required. If unused, interrupt input(s) must be connected to VDD through a pull-up resistor. Table 2. Control Register Read — Interrupt INT3 INT2 INT1 INT0 0 D3 B2 B1 B0 1 1 1 0 A2 A1 A0 R/W FIXED HARDWARE SELECTABLE SW00862 Figure 4. Slave address The last bit of the slave address defines the operation to be performed. When set to logic 1, a read is selected while a logic 0 selects a write operation. CONTROL REGISTER Following the successful acknowledgement of the slave address, the bus master will send a byte to the PCA9544A which will be stored in the Control Register. If multiple bytes are received by the PCA9544A, it will save the last byte received. This register can be written and read via the I2C-bus. INTERRUPT BITS (READ ONLY) 7 6 5 4 3 X CHANNEL SELECTION BITS (READ/WRITE) 2 B2 1 B1 0 B0 COMMAND No interrupt on channel 0 Interrupt on channel 0 No interrupt on channel 1 Interrupt on channel 1 No interrupt on channel 2 Interrupt on channel 2 No interrupt on channel 3 Interrupt on channel 3 INT3 INT2 INT1 INT0 ENABLE BIT SW00386 X X X 1 X X X X Figure 5. Control register 0 CONTROL REGISTER DEFINITION A SCx/SDx downstream pair, or channel, is selected by the contents of the control register. This register is written after the PCA9544A has been addressed. The 3 LSBs of the control byte are used to determine which channel is to be selected. When a channel is selected, it will become active after a stop condition has been placed on the I2C-bus. This ensures that all SCx/SDx lines will be in a HIGH state when the channel is made active, so that no false conditions are generated at the time of connection. Table 1. Control Register; Write — Channel Selection/ Read — Channel Status INT3 INT2 INT1 INT0 D3 B2 B1 B0 COMMAND X X 1 0 X X X X X X 1 0 X 1 X X X X X X X X X X X X X X X X X 0 X X X X X 0 X X X X X 0 X X X X X 0 X X X X X 0 0 1 1 1 1 0 X 0 0 1 1 0 X 0 1 0 1 0 No channel selected Channel 0 enabled Channel 1 enabled Channel 2 enabled Channel 3 enabled No channel selected; power-up default state NOTE: Several interrupts can be active at the same time. Ex: INT3 = 0, INT2 = 1, INT1 = 1, INT0 = 0, means that there is no interrupt on channels 0 and 3, and there is interrupt on channels 1 and 2. POWER-ON RESET When power is applied to VDD, an internal Power On Reset holds the PCA9544A in a reset condition until VDD has reached VPOR. At this point, the reset condition is released and the PCA9544A registers and I2C state machine are initialized to their default states, all zeroes causing all the channels to be deselected. Thereafter, VDD must be lowered below 0.2 V to reset the device. 2004 Sep 29 5 Philips Semiconductors Product data sheet 4-channel I2C multiplexer with interrupt logic PCA9544A VOLTAGE TRANSLATION The pass gate transistors of the PCA9544A are constructed such that the VDD voltage can be used to limit the maximum voltage that will be passed from one I2C-bus to another. Vpass vs. VDD 5.0 4.5 MAXIMUM 4.0 TYPICAL 3.5 Vpass 3.0 2.5 2.0 1.5 1.0 2.0 2.5 3.0 3.5 4.0 VDD 4.5 5.0 5.5 MINIMUM Figure 6 shows the voltage characteristics of the pass gate transistors (note that the graph was generated using the data specified in the DC Characteristics section of this datasheet). In order for the PCA9544A to act as a voltage translator, the Vpass voltage should be equal to, or lower than the lowest bus voltage. For example, if the main bus was running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then Vpass should be equal to or below 2.7 V to effectively clamp the downstream bus voltages. Looking at Figure 6, we see that Vpass (max.) will be at 2.7 V when the PCA9544A supply voltage is 3.5 V or lower so the PCA9544A supply voltage could be set to 3.3 V. Pull-up resistors can then be used to bring the bus voltages to their appropriate levels (see Figure 13). More Information can be found in Application Note AN262 PCA954X family of I 2C/SMBus multiplexers and switches. SW00820 Figure 6. Vpass voltage 2004 Sep 29 6 Philips Semiconductors Product data sheet 4-channel I2C multiplexer with interrupt logic PCA9544A CHARACTERISTICS OF THE I2C-BUS The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. Start and stop conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P) (see Figure 8). Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 7). System configuration A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 9). SDA SCL data line stable; data valid change of data allowed SW00363 Figure 7. Bit transfer SDA SDA SCL S START condition P STOP condition SCL SW00365 Figure 8. Definition of start and stop conditions SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C MULTIPLEXER SLAVE SW00366 Figure 9. System configuration 2004 Sep 29 7 Philips Semiconductors Product data sheet 4-channel I2C multiplexer with interrupt logic PCA9544A Acknowledge The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition. DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition 1 2 8 9 clock pulse for acknowledgement SW00368 Figure 10. Acknowledgement on the I2C-bus SLAVE ADDRESS CONTROL REGISTER SDA S 1 1 1 0 A2 A1 A0 0 R/W A X X X X X B2 B1 B0 A P start condition acknowledge from slave acknowledge from slave SW00802 Figure 11. WRITE control register SLAVE ADDRESS CONTROL REGISTER last byte SDA S 1 1 1 0 A2 A1 A0 1 R/W A INT3 INT2 INT1 INT0 X acknowledge from slave B2 B1 B0 NA P stop condition start condition no acknowledge from master SW00378 Figure 12. READ control register 2004 Sep 29 8 Philips Semiconductors Product data sheet 4-channel I2C multiplexer with interrupt logic PCA9544A TYPICAL APPLICATION VDD = 2.7 – 5.5 V VDD = 3.3 V V = 2.7 – 5.5 V SEE NOTE (1) SDA SCL SDA SCL INT SD0 CHANNEL 0 SC0 INT0 V = 2.7 – 5.5 V SEE NOTE (1) I2C/SMBus MASTER SD1 CHANNEL 1 SC1 INT1 V = 2.7 – 5.5 V SEE NOTE (1) SD1 CHANNEL 2 SC1 INT2 V = 2.7 – 5.5 V SEE NOTE (1) SD1 A2 SC1 A1 NOTE: 1. If the device generating the Interrupt has an open-drain output structure or can be tri-stated, a pull-up resistor is required. If the device generating the Interrupt has a totem-pole output structure and cannot be tri-stated, a pull-up resistor is not required. The Interrupt inputs should not be left floating. A0 VSS INT3 CHANNEL 3 PCA9544A SW02268 Figure 13. Typical application 2004 Sep 29 9 Philips Semiconductors Product data sheet 4-channel I2C multiplexer with interrupt logic PCA9544A ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134).Voltages are referenced to GND (ground = 0 V). SYMBOL VDD VI II IO IDD ISS Ptot Tstg Tamb PARAMETER DC supply voltage DC input voltage DC input current DC output current Supply current Supply current total power dissipation Storage temperature range Operating ambient temperature CONDITIONS RATING –0.5 to +7.0 –0.5 to +7.0 ±20 ±25 ±100 ±100 400 –60 to +150 –40 to +85 UNIT V V mA mA mA mA mW °C °C NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 2004 Sep 29 10 Philips Semiconductors Product data sheet 4-channel I2C multiplexer with interrupt logic PCA9544A DC CHARACTERISTICS SYMBOL Supply VDD IDD Istb VPOR Supply voltage Supply current Standby current VDD = 2.3 V to 3.6 V; VSS = 0 V; Tamb = –40 °C to +85 °C; unless otherwise specified. (See page 12 for VDD = 3.6 V to 5.5 V) LIMITS PARAMETER TEST CONDITIONS CONDITIONS MIN TYP MAX UNIT 2.3 Operating mode; VDD = 3.6 V; no load; VI = VDD or VSS; fSCL = 100 kHz Standby mode; VDD = 3.6 V; no load; VI = VDD or VSS; fSCL = 0 kHz no load; VI = VDD or VSS — — — — 10 0.1 1.5 3.6 30 1 2.1 V µA µA V Power-on reset voltage (Note 1) Input SCL; input/output SDA VIL VIH IO OL IL Ci VIL VIH ILI Ci Pass Gate RO ON Switch resistance Switch resistance VCC = 3.0 V to 3.6 V, VO = 0.4 V, IO = 15 mA VCC = 2.3 V to 2.7 V, VO = 0.4V, IO = 10 mA Vswin = VDD = 3.3 V; Iswout = –100 µA VPass Switch output voltage Switch output voltage Vswin = VDD = 3.0 V to 3.6 V; Iswout = –100 µA Vswin = VDD = 2.5 V; Iswout = –100 µA Vswin = VDD = 2.3 V to 2.7 V; Iswout = –100 µA IL Cio INT Output IOL IOH LOW-level output current HIGH-level output current VOL = 0.4 V 3 — 7 — — +10 mA µA Leakage current Input/output capacitance VI = VDD or VSS VI = VSS 5 7 — 1.6 — 1.1 –1 — 11 16 1.9 — 1.5 — — 3 30 55 — 2.8 — 2.0 +1 5 µA pF V Ω LOW-level input voltage HIGH-level input voltage LOW-level output current level output current Leakage current Input capacitance VOL = 0.4 V VOL = 0.6 V VI = VDD or VSS VI = VSS –0.5 0.7VDD 3 6 –1 — — — 7 10 — 10 0.3VDD 6 — — +1 13 mA µA pF V V Select inputs A0 to A2 / INT0 to INT3 LOW–level input voltage HIGH-level input voltage Input leakage current Input capacitance VI = VDD or VSS VI = VSS –0.5 0.7VDD –1 — — — — 1.6 +0.3VDD VDD + 0.5 +1 3 V V µA pF NOTES: 1. VDD must be lowered to 0.2 V in order to reset part. 2. For operation between published voltage ranges, refer to worst case parameter in both ranges. 2004 Sep 29 11 Philips Semiconductors Product data sheet 4-channel I2C multiplexer with interrupt logic PCA9544A DC CHARACTERISTICS SYMBOL Supply VDD IDD Istb VPOR VIL VIH IO OL IL Ci VIL VIH ILI Ci Pass Gate RON VPass IL Cio INT Output IOL IOH Supply voltage Supply current VDD = 4.5 V to 5.5 V; VSS = 0 V; Tamb = –40 °C to +85 °C; unless otherwise specified. (See page 11 for VDD = 2.3 V to 3.6 V) LIMITS PARAMETER TEST CONDITIONS CONDITIONS MIN TYP MAX UNIT 4.5 Operating mode; VDD = 5.5 V; no load; VI = VDD or VSS; fSCL = 100 kHz Standby mode; VDD = 5.5 V; no load; VI = VDD or VSS; fSCL = 0 kHz no load; VI = VDD or VSS — — 25 5.5 100 V µA µA V Standby current Power-on reset voltage — — 0.3 1.7 1 2.1 Input SCL; input/output SDA LOW-level input voltage HIGH-level input voltage LOW-level output current level output current Leakage current Input capacitance VOL = 0.4 V VOL = 0.6 V VI = VDD or VSS VI = VSS –0.5 0.7VDD 3 6 –1 — — — — — — 12 0.3VDD 6 — — +1 13 V V mA mA µA pF Select inputs A0 to A2 / INT0 to INT3 LOW-level input voltage HIGH-level input voltage Input leakage current Input capacitance pin at VDD or VSS VI = VSS VCC = 4.5 V to 5.5 V, VO = 0.4 V, IO = 15 mA Vswin = VDD = 5.0 V; Iswout = –100 µA Vswin = VDD = 4.5 V to 5.5 V; Iswout = –100 µA VI = VDD or VSS VI = VSS VOL = 0.4 V –0.5 0.7VDD –1 — — — — 2 +0.3VDD VDD + 0.5 +1 5 V V µA pF Ω V V µA pF Switch resistance Switch output voltage Switch output voltage Leakage current Input/output capacitance 4 — 2.6 –1 — 9 3.6 – — 3 24 — 4.5 +1 5 LOW-level output current HIGH-level output current 3 — — — — +10 mA µA NOTES: 1. VDD must be lowered to 0.2 V in order to reset part. 2. For operation between published voltage ranges, refer to worst case parameter in both ranges. 2004 Sep 29 12 Philips Semiconductors Product data sheet 4-channel I2C multiplexer with interrupt logic PCA9544A AC CHARACTERISTICS SYMBOL tpd fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tSU;STO tHD;DAT tSU;DAT tR tF Cb tSP tVD:DATL tVD:DATH tVD:ACK INT tiv tir Lpwr Hpwr INTn to INT active valid time4 INTn to INT inactive delay time4 LOW level pulse width rejection of INTn inputs4 HIGH level pulse width rejection of INTn inputs4 — — 10 500 4 2 — — — — 1 500 4 2 — — µs µs ns ns PARAMETER Propagation delay from SDA to SDn or SCL to SCn SCL clock frequency Bus free time between a STOP and START condition Hold time (repeated) START condition After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Set-up time for STOP condition Data hold time Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Capacitive load for each bus line Pulse width of spikes which must be suppressed by the input filter Data valid (HL)4 Data valid (LH)4 Data valid Acknowledge STANDARD-MODE I2C-bus MIN — 0 4.7 4.0 4.7 4.0 4.7 4.0 02 250 — — — — — — — MAX 0.31 100 — — — — — — 3.45 — 1000 300 400 50 1 0.6 1 FAST-MODE I2C-bus MIN — 0 1.3 0.6 1.3 0.6 0.6 0.6 02 100 20 + 0.1Cb3 20 + 0.1Cb3 — — — — — MAX 0.31 400 — — — — — — 0.9 — 300 300 400 50 1 0.6 1 ns kHz µs µs µs µs µs µs µs ns ns µs µs ns µs µs µs UNIT NOTES: 1. Pass gate propagation delay is calculated from the 20 Ω typical RON and and the 15 pF load capacitance. 2. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. 3. Cb = total capacitance of one bus line in pF. 4. Measurements taken with 1 kΩ pull-up resistor and 50 pF load. SDA tBUF tLOW tR tF tHD;STA tSP SCL tHD;STA P S tHD;DAT tHIGH tSU;DAT Sr tSU;STA tSU;STO P SU00645 Figure 14. Definition of timing on the I2C-bus 2004 Sep 29 13 Philips Semiconductors Product data sheet 4-channel I2C multiplexer with interrupt logic PCA9544A SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 2004 Sep 29 14 Philips Semiconductors Product data sheet 4-channel I2C multiplexer with interrupt logic PCA9544A TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 2004 Sep 29 15 Philips Semiconductors Product data sheet 4-channel I2C multiplexer with interrupt logic PCA9544A HVQFN20: plastic thermal enhanced very thin quad flat package; no leads; 20 terminals; body 5 x 5 x 0.85 mm SOT662-1 2004 Sep 29 16 Philips Semiconductors Product data sheet 4-channel I2C multiplexer with interrupt logic PCA9544A REVISION HISTORY Rev _2 Date 2004929 Description Product data sheet (9397 750 13931). Supersedes data of 2004 Jul 28 (9397 750 13301). • Table 1. Modifications: “Control Register; Write — Channel Selection / Read — Channel Status” on page 5: add ‘no channel selected; power-up default state’ row to bottom of table • DC characteristics table (VDD = 2.3 V to 3.6 V) on page 11: – Supply change IDD Typ. from 20 µA to 10 µA change IDD Max. from 50 µA to 30 µA – Input SCL; input/output SDA change IOL Typ. (VOL = 0.4 V) from “–” to 7 mA change IOL Typ. (VOL = 0.6 V) from “–” to 10 mA change Ci Typ. from 12 pF to 10 pF – Select inputs A0 to A2 / INT0 to INT3 change Test conditions for ILI from “pin at VDD or VSS” to “VI = VDD or VSS” – INT output change IOL Typ. from “–” to 7 mA change IOH Max. from +100 µA to +10 µA – Add Note 2. • DC characteristics table (VDD = 4.5 V to 5.5 V) on page 12: – change description from “VDD = 3.6 V to 5.5 V” to “VDD = 4.5 V to 5.5 V” – Supply change VDD Min. from 3.6 V to 4.5 V change IDD Typ. from 65 µA to 25 µA – Input SCL; input/output SDA remove parameters IIL and IIH add parameter IL – Select inputs A0 to A2 / INT0 to INT3; change ILI Max. from +50 µA to +1 µA – Pass Gate change IL Min. from –10 µA to –1 µA change IL Max. from +100 µA to +1 µA – INT output; change IOH Max from +100 µA to +10 µA – Add Note 2. • AC characteristics table on page 13: – add reference to (new) Note 4 at parameters tVD:DATL and tVD:DATH – INT Add reference to (new) Note 4 in all 4 parameter descriptions Lpwr and Hpwr: change “or” to “of” – Add Note 4. _1 20040728 Objective data sheet (9397 750 13301). 2004 Sep 29 17 Philips Semiconductors Product data sheet 4-channel I2C multiplexer with interrupt logic PCA9544A Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011. Data sheet status Level I Data sheet status [1] Objective data sheet Product status [2] [3] Development Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). II Preliminary data sheet Qualification III Product data sheet Production [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 © Koninklijke Philips Electronics N.V. 2004 All rights reserved. Printed in U.S.A. Date of release: 09-04 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. Document number: 9397 750 13931 Philips Semiconductors 2004 Sep 29 18