PAS109B

PAS109B PAS109BC QQVGA COLOR CMOS IMAGE SENSOR PAS109BB QQVGA MONO CMOS IMAGE SENSOR General Description The PAS109B is a color and monochrome digital CMOS image sensor with resolution of 164(H) x 124(V). The PAS109B outputs 8, 4 , 2 or 1-bit digital raw data or 8-bit formatted data per pixel. The PAS109B performs automatic gain control, automatic exposure control and automatic de-flicker. The PAS109B can also be programmed via I2CTM serial control bus. By programming the internal register settings, it performs on-chip frame rate adjustment, exposure control, offset correction DAC, programmable gain control as well as output formatting. By proprietary technology, FPN, smear and blooming are drastically reduced. The PAS109 is available in color or monochrome in 32-pin LCC or 32-pin chip-with-lens package. Features 164x124 pixels, 1/11” Lens Automatic/Manual exposure-gain control On chip 10-bit ADC On chip PGA On chip 9-bit DAC User selectable output data formats: • • 8-bit formatted data 8/4/2/1-bit raw data Output tri-state through /CSB pin or register AE report Horizontal mirror output Flash light application allowable Automatic de-flicker External oscillator I2C Interface Wide operating supply range: 2.4 – 3.6V Low power dissipation: 16mW @ 60fps Low power down dissipation: 200µW Key Specification Wide operating supply range Power Supply 2.4V ~ 3.6V Array Elements Optical Format Pixel Size System Clock Max. Pixel Rate FPN Sensitivity PGA Gain Frame Rate Scan Mode S/N ratio Package 164 x 124 1/11 ” 7.25µ 7.25 7.25µ 7.25 7.25µm x 7.25µm Up to 48MHz 1.5MHz < 0.2% of saturation 2.0V/Lux-sec 16X (24dB) 60fps Progressive >40dB 32-pin LCC or 32-pin LCC chip with lens All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 1 V1.1, Mar. 2002 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw PixArt Imaging Inc. PAS109B CMOS Image Sensor IC 1. Pin Assignment Pin# Name Power Supply 28 VDDD 27 GNDD 3 VDDA 2 GNDA 19 VDDQ 18 GNDQ 1 GNDE Data Interface 17 D0 16 D1 15 D2 12 D3 11 D4 10 D5 9 D6 8 D7 22 PXCK 23 HSYNC 24 VSYNC Analog pin 6 VRT 4 VCM 5 VRB 7 VDDY1 I2C 25 SCL 26 SDA Type P P P P P P P O O O O O O O O O O O I/O I/O I/O BYPASS I I/O I I BIAS Description Digital VDD Digital Ground Analog VDD Analog Ground Digital VDD Digital Ground Ground Pixel data output, LSB Pixel data output Pixel data output Pixel data output Pixel data output Pixel data output Pixel data output Pixel data output, MSB Pixel clock output Horizontal Synchronization clock Vertical Synchronization clock ADC reference voltage, top level Common mode voltage reference ADC reference voltage, bottom level Reference voltage I2C interface clock I2C interface bi-direction data Chip select bar, active low System clock input pin Fixed bias input voltage Not connected Not connected Not connected Not connected Not connected Misc. Pins 30 20 14 13 21 29 31 32 CSB SYSCLK VLRST NC NC NC NC NC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 2 V1.1, Mar. 2002 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw PixArt Imaging Inc. PAS109B CMOS Image Sensor IC 2. Block Diagram DAC 9-bit Voltage Reference 10- Bit ADC b0..b9 Imager (164x124) Column & Row drive CDS + ReadOut PGA Gain code Edge detect Data packing Data companding D0..D7 Ex posure Time AEC/AGC Decision Interface control HSYNC VSYNC Timing Control Clock Gen. PXCK CS Control register I2C SCL SDA Block Diagram Fig 2.1 – Block diagram of PAS109 As the block diagram of PAS109 is shown in Figure 1. By pulling the CSB pin to low, the 164x124 sensor starts to produce a signal according to the amount of the light integrated in pixels. An entire raw data is then fed to a CDS readout array to reduce FPN noise and reset noise. A differential signal is then read out serially and fed to a programmable gain amplifier (PGA) followed by a 10-bit A/D converter. Voltage reference block generates all necessary voltage and current for sensor array and analog circuit. All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 3 V1.1, Mar. 2002 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw PixArt Imaging Inc. PAS109B CMOS Image Sensor IC 3. Pixel Array And Pixel Color Pattern 3.1. Pixel array and pixel color pattern The output image format of PAS109B is QQVGA (164x124 pixel array). To provide the co-processor with the extra information it needs for interpolation at the edges of the pixel array, an border of 2 pixels on all 4 sides of the array are available. Fig 3.1. illustrates the pixel array and pixel color pattern. Dummy row GRGR BGBG GRGR GRGR BGBG GRGR Row 125 Row 124 Array: 164(H) x 124(V) 124 rows BGBG GRGR BGBG Dummy row Dummy row Dummy row Dark line Dark line Dummy row 164 columns 1 column BGBG GRGR BGBG Row 3 Row 2 Row 0 Row 1 1column Fig 3.1. Pixel array and pixel color pattern Note: 1. 2. 3. Pixel color pattern does not apply to monochrome sensor. Pixel read-out proceeds from left to right, and from bottom row to top row. Pixel array not drawn to scale. All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 4 V1.1, Mar. 2002 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw PixArt Imaging Inc. PAS109B CMOS Image Sensor IC 4 Output timing: line time = Hs +4+2+160+2+4 = 194 pixclks Hsync=22 PXCK Hsync BBB PXCLK BBBB 2+160+2 raw data BBBB BBBB 2+160+2 raw data Fig. 4.1 Inter-line timing Vsync. Vsync Frame time (=126 lines) Black Black Valid frame data (124 lines) Black Hsync. Hsync Fig. 4.2 Inter-frame timing (frame time=126 lines) Vsync Hsync Black Hsync Black Frame time (>126 lines) Black Valid frame data (124 lines) Fig. 4.3 Inter-frame timing(frame time>126 lines) All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 5 V1.1, Mar. 2002 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw PixArt Imaging Inc. PAS109B CMOS Image Sensor IC 5. I2C Bus PAS109B supports I2C-bus transfer protocol and is acting as slave device. The 7 bits unique slave address is 1000000 and supports receiving / transmitting speed up to 400kHz. 5.1 I2C bus overview Only two wires SDA (serial data) and SCL (serial clock) carry information between the devices connected to the I2C bus. Normally both SDA and SCL lines are open collector structure and pull high by external pull-up resistors. Only the master can initiates a transfer (start), generates clock signals, and terminates a transfer (stop). Start and stop condition: A high to low transition of the SDA line while SCL is high defines a start condition. A low to high transition of the SDA line while SCL is high defines a stop condition. Please refer to Fig 5.1. Valid data: The data on the SDA line must be stable during the high period of the SCL clock. Within each byte, MSB is always transferred first. Read/write control bit is the LSB of the first byte. Please refer to Fig 5.2. Both the master and slave can transmit and receive data from the bus. Acknowledge: The receiving device should pull down the SDA line during high period of the SCL clock line when a complete byte was transferred by transmitter. In the case of a master received data from a slave, the master does not generate an acknowledgment on the last byte to indicate the end of a master read cycle. SDA SCL S Start Condition P Stop Condition Fig 5.1 Start and Stop Conditions All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 6 V1.1, Mar. 2002 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw PixArt Imaging Inc. PAS109B CMOS Image Sensor IC SDA DATA STABLE DATA CHANGE ALLOWED SCL Fig 5.2 5.2 Data Transfer Format 5.2.1 Master transmits data to slave (write cycle) S : Start A : Acknowledge by slave P : Stop Valid Data RW : The LSB of 1ST byte to decide whether current cycle is read or write cycle. RW=1 read cycle, RW=0 write cycle. SUBADDRESS : The address values of PAS109B internal control registers (Please refer to PAS109B register description) 1ST BYTE 2ND BYTE n BYTEs + A S SLAVE ID (7 BIT) RW A SUBADDRESS (8 BIT) A DATA A DATA A P MSB LSB=0 During write cycle, the master generates start condition and then places the 1st byte data that are combined slave address (7 bits) with a read/write control bit to SDA line. After slave(PAS109B) issues acknowledgment, the master places 2nd byte (sub-address) data on SDA line. Again follow the PAS109B acknowledgment, the master places the 8 bits data on SDA line and transmit to PAS109B control register (address was assigned by 2nd byte). After PAS109B issue acknowledgment, the master can generate a stop condition to end of this write cycle. In the condition of multi-byte write, the PAS109B sub-address is automatically increment after each DATA byte transferred. The data and A cycles is repeat until last byte write. Every control registers value inside PAS109B can be programming via this way. (Please refer to Fig 5.3.) 7 V1.1, Mar. 2002 All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw PixArt Imaging Inc. PAS109B CMOS Image Sensor IC 5.2.2 Slave transmits data to master (read cycle) The sub-address was taken from previous write cycle The sub-address is automatically increment after each byte read Am : Acknowledge by master Note there is no acknowledgment from master after last byte read 1ST BYTE SLAVE ADDRESS (7 BITS) 2ND BYTE n BYTE S RW A DATA (8 BIT) Am DATA Am DATA 1 P NO ACK IN LAST BYTE During read cycle, the master generates start condition and then place the 1st byte data that are combined slave address (7 bits) with a read/write control bit to SDA line. After issue acknowledgment, 8 bits DATA was also placed on SDA line by PAS109B. The 8 bit data was read from PAS109B internal control register that address was assigned by previous write cycle. Follow the master acknowledgment, the PAS109B place the next 8 bits data (address is increment automatically) on SDA line and then transmit to master serially. The DATA and Am cycles is repeat until the last byte read. After last byte read, Am is no longer generated by master but instead by keep SDA line high. The slave (PAS109B) must releases SDA line to master to generate STOP condition. (Please refer to Fig 5.3.) SDA SCL 1-7 S Start Condition Address R/W ACK from Receiver Data ACK from Receiver Data 8 9 1-7 8 9 1-7 8 9 P Stop ACK from Condition Receiver Fig 5.3 Data Transfer Format All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 8 V1.1, Mar. 2002 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw PixArt Imaging Inc. PAS109B CMOS Image Sensor IC 5.3 I2C Bus Timing SDA SDA tf tLOW SCL S tHD;STA tHD;DAT tSU;STA Sr tSU;STO P S tr tSU;DAT tf tHD;STA tSP tr tBUF tHIGH Fig 5.4 I2C Bus Timing 5.4 I2C Bus Timing Specification PARAMETER SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated. Low period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time. For I2C-bus device Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Bus free time between a STOP and START Capacitive load for each bus line Noise margin at LOW level for each connected device (including hysteresis) Noise margin at HIGH level for each connected device (including hysteresis) Note: It depends on the "high" period time of SCL. STANDARD-MODE SYMBOL MIN. MAX. UNIT fscl tHD:STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO tBUF Cb VnL VnH 10 4.0 4.7 0.75 4.7 0 250 30 30 4.0 4.7 1 0.1 VDD 0.2 VDD 400 3.45 N.D. N.D. 15 - kHz us us us us us ns ns(note1) ns(note1) us us pF V V All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 9 V1.1, Mar. 2002 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw PixArt Imaging Inc. PAS109B CMOS Image Sensor IC 6. Specifications Absolute Maximum Ratings Symbol Vdd Vin Vout Topt1 Topt2 DC supply voltage DC input voltage DC output voltage Operating temperature (chip functional) Operating temperature (guaranteed performance) Parameter Min -0.5 0.5 -0.5 -10 0 Max 3.8 Vdd+0.5 Vdd+0.5 70 40 Unit V V V ℃ ℃ DC Electrical Characteristics (VDD=3.0V±20%, Ta=10°C~40°C ) Symbol Type :PWR VDD IDD Analog and digital operating voltage Operating Current 2.4 3.0 8 100 2.0 0 TBD Vdd-0.2 0.2 VDD 0.8 10 3.6 V mA uA V V pF uA V V Parameter Min. Typ. Max. Unit Istby Standby current Type :IN & I/O Reset and SYSCLK VIH VIL Cin Ilkg VOH VOL Input voltage HIGH Input voltage LOW Input capacitor Input leakage current Output voltage HIGH Output voltage LOW Type : OUT & I/O for PXD0:7, PXCK, H/VSYNC & SDA, load 10pf, 1.2kΩ, 3.0volts AC Operating Condition Symbol SYSCLK PXCK Parameter Master clock frequency Pixel clock output frequency Min. 4.5 Typ. Max. 48 1.5 Unit MHz MHz Sensor Characteristics Parameter Photo response non-uniformity Saturation output voltage Dark output voltage Dark signal non-uniformity Sensitivity ( Red channel ) Sensitivity ( Green channel ) Sensitivity ( Blue channel ) Symbol PRNU Vsat. Vdark DSNU R G B Min. Typ. 1.18 1.35 35 2.52 2.0 2.0 1.35 Max. Unit % V mV/sec % V/Lux-sec V/Lux-sec V/Lux-sec 10 V1.1, Mar. 2002 Note All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw PixArt Imaging Inc. PAS109B CMOS Image Sensor IC 7. Package Information 7.1. 32-pin LCC 7.1.1. Pin Connection Diagram GNDE GNDA VDDA 3 CSB NC NC 29 30 31 32 NC 1 2 4 VCM VDDD GNDD SDA SCL VSYNC HSYNC PXCK NC 28 5 VRB VRT VDDY1 D7 D6 D5 D4 D3 27 26 25 24 6 7 8 9 10 23 22 21 20 19 18 17 16 15 14 13 11 12 SYSCLK VLRST VDDQ GNDQ -- Bottom View -- NC D1 D0 D2 All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 11 V1.1, Mar. 2002 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw PixArt Imaging Inc. PAS109B CMOS Image Sensor IC 7.1.2. Package Outline All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 12 V1.1, Mar. 2002 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw PixArt Imaging Inc. PAS109B CMOS Image Sensor IC 7.2. 32-pin LCC chip with lens package 7.2.1. Pin Connection Diagram All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 13 V1.1, Mar. 2002 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw PixArt Imaging Inc. PAS109B CMOS Image Sensor IC 7.2.2. Lens Specification & Package Outline Lens specification: EFL BFL F no. Diagonal Field of View Distortion IR filter cutoff 1.7mm 1.65mm 2.2 52° -3% 648nm+10nm Note: Customized lens is available upon request. Package Outline: All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 14 V1.1, Mar. 2002 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw PixArt Imaging Inc. PAS109B CMOS Image Sensor IC 8. Ordering Information Part Number PAS109BCB-32 PAS109BBB-32 PAS109BCL-32 PAS109BBL-32 Color/Monochrome Color Monochrome Color Monochrome Package 32-pin LCC (plastic) 32-pin LCC (plastic) 32-pin LCC chip with lens 32-pin LCC chip with lens All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 15 V1.1, Mar. 2002 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw