LV7844DV-125.0M-T500

LV78D Series 3.3 V LVDS Clock Oscillators January 2008 This device is obsolete, January 2008 This is replaced by the LV98xxDV device For new designs use the LV93xxDV device • Pletronics’ LV78D Series is a quartz crystal controlled precision square wave generator with an LVDS output. • FR4 base with a mechanical metal cover. • Solder pad compatible with many 9x14mm plastic J lead packages. • Has internal bypass capacitor on the Vcc lead • Tape and Reel or cut tape packaging is available. • 80 to 250 MHz • 9.04mm x 8.91mm (S package) • Enable/Disable Function on pad 2 (see LV76D for E/D on pad 1) • Disable function includes low standby power mode • 3rd Overtone Crystals used • Low Jitter • 5x7 mm LCC ceramic oscillator inside Pletronics Inc. certifies this device is in accordance with the RoHS 5/6 (2002/95/EC) and WEEE (2002/96/EC) directives. Pletronics Inc. guarantees the device does not contain the following: Cadmium, Hexavalent Chromium, Lead, Mercury, PBB’s, PBDE’s Weight of the Device: 0.4 grams Moisture Sensitivity Level: 1 As defined in J-STD-020C Second Level Interconnect code: e4 Absolute Maximum Ratings: Parameter VCC Supply Voltage Vi Vo Input Voltage Output Voltage Unit -0.5V to +5.0V -0.5V to VCC + 0.5V -0.5V to VCC + 0.5V Thermal Characteristics The maximum die or junction temperature is 155oC The thermal resistance junction to board is 60 to 100oC/Watt depending on the solder pads, ground plane and construction of the PCB. Product information is current as of publication date. The product conforms to specifications per the terms of the Pletronics standard warranty. Production processsing does not necessarily include testing of all parameters. Copyright © 2006, 2007, 2008 Pletronics Inc. LV78D Series 3.3 V LVDS Clock Oscillators January 2008 Part Number: LV78 45 D E V -125.0M -XX Packaging code or blank T250 = 250 per Tape and Reel T500 = 500 per Tape and Reel T1K = 1000 per Tape and Reel Frequency in MHz Supply Voltage VCC V = 3.3V _ 10% + Optional Enhanced OTR Blank = Temp. range -10 to +70oC E = Temp. range -40 to +85oC Series Model Frequency Stability 45 = + 50 ppm _ 44 = + 25 ppm _ 20 = + 20 ppm _ Series Model Marking Legend: PLE = Pletronics FF.FFF M = Frequency in MHz YYWW or YWW or YMD = Date of Manufacture (year and week, or year-month-day) All other marking is internal factory codes Specifications such as frequency stability, supply voltage and operating temperature range, etc. are not identified from the marking. External packaging labels and packing list will correctly identify the ordered Pletronics part number. Codes for Date Code YMD Code Year Code Month Code Day Code Day Code Day 1 1 D 13 T 25 6 2006 A JAN 2 2 E 14 U 26 7 2007 B FEB 3 3 F 15 V 27 8 2008 C MAR 4 4 G 16 W 28 9 2009 D APR E MAY 5 5 H 17 X 29 0 2010 F JUN 6 6 J 18 Y 30 1 2011 G JUL 7 7 K 19 Z 31 H AUG 8 8 L 20 2 2012 J SEP 9 9 M 21 K OCT A 10 N 22 L NOV B 11 P 23 M DEC C 12 R 24 Part Marking: PLE LV78D FF.FFF M C YMDXX or LV78DX FF.FFF M PLE XX C YYWWXX www.pletronics.com 425-776-1880 2 LV78D Series 3.3 V LVDS Clock Oscillators January 2008 Electrical Specification for 3.30V _10% over the specified temperature range + Item Frequency Range Frequency Accuracy “45" “44" “20" Output Waveform Output High Level Output Low Level Differential Output (VOD) Output Offset Voltage (VOS) Differential Output Error (dVOS) Output Symmetry Output TRISE and TFALL Jitter -0.90 247 1.125 -45 300 Vcc Supply Current Enable/Disable Internal Pull-up V disable V enable Output leakage VOUT = VCC VOUT = 0V Enable Disable time Start up time Operating Temperature Range 50 2.0 -10 -10 -10 -40 Storage Temperature Range Standby Current ICC -55 Min 80 -50 -25 -20 Max 250 +50 +25 +20 LVDS 1.60 -454 1.375 50 55 700 0.15 2.8 66 0.8 +10 +10 10 10 5 +70 +85 +125 3 mA Kohm Volts Volts uA uA nS nS mS o Unit MHz ppm Condition For all supply voltages, load changes, aging for 1 year, shock, vibration and temperatures Volts Volts mVolts Volts mVolts % pS pS RMS See load circuit See load circuit See load circuit See load circuit See load circuit R1 = 50 ohms R1 = 50 ohms R1 = 50 ohms R1 = 50 ohms R1 = 50 ohms Referenced to 50% of amplitude or crossing point Vth is 20% and 80% of waveform Measured from 12KHz to 20MHz from Fnominal Measured from 10Hz to 1MHz from Fnominal Includes current of properly terminated device To Vcc (equivalent resistance) Referenced to Ground Referenced to Ground Pad 1 low, device disabled Time for output to reach a logic state Time for output to reach a high Z state Measured from the time Vcc = 3.0V Standard Temperature Range Extended Temperature Range “E” Option C C C o o uA Pad 1 low, device disabled Specifications with Pad 1 E/D open circuit Typical Phase-Noise Response www.pletronics.com 425-776-1880 3 LV78D Series 3.3 V LVDS Clock Oscillators January 2008 0 -20 -40 dBc/Hz -60 -80 -100 -120 -140 -160 10 1,000 100,000 10,000,000 Frequency (Hz) Load Circuit Test Waveform Symmetry Vhigh 80% 50% 20% Vlow Trise Tfall Out Out* Showing Out Measurement only www.pletronics.com 425-776-1880 4 LV78D Series 3.3 V LVDS Clock Oscillators January 2008 Reliability: Environmental Compliance Parameter Mechanical Shock Vibration Solderability Thermal Shock Condition MIL-STD-883 Method 2002, Condition B MIL-STD-883 Method 2007, Condition A MIL-STD-883 Method 2003 MIL-STD-883 Method 1011, Condition A ESD Rating Model Human Body Model Charged Device Model Minimum Voltage 1500 1000 Conditions MIL-STD-883 Method 3115 JESD 22-C101 Package Labeling Label is 1" x 2.6" (25.4mm x 66.7mm) Font is Courier New Bar code is 39-Full ASCII Label is 1" x 2.6" (25.4mm x 66.7mm) Font is Arial Layout and application information Recommend connecting Pad 1 and Pad 2 together to permit the design to accept Enable/Disable on both input pads (see LV76D for E/D on pad 1) For Optimum Jitter Performance, Pletronics recommends: • a ground plane under the device • no large transient signals (both current and voltage) should be routed under the device • do not layout near a large magnetic field such as a high frequency switching power supply • do not place near piezoelectric buzzers or mechanical fans. www.pletronics.com 425-776-1880 5 LV78D Series 3.3 V LVDS Clock Oscillators January 2008 Mechanical: Inches A B C D1 E1 Cover: Centered on the base 304 Stainless Steel 0.010 inch (0.25mm) Electroless Nickel Plated 1 µinch (25 µm) typical Label: White Kapton with Black Letters –or-Blue Epoxy heat cure ink covering top with laser marked lettering F1 FR4 PCB Base: Solder masked All via holes tented on bottom Copper Clad 670 µinch (17 µm) Nickel plated 118 µinch (3 µm) Gold plated 0.8 µinch (0.02 µm) Typical thicknesses Pin 3 Ground plane is typical Not to scale G1 H I1 J1 K1 L1 1 mm 8.91 +0.07 _ 9.04 +0.13 _ 2.62 +0.13 _ 8.23 8.03 1.27 1.02 1.50 0.51 1.02 2.54 0.66 0.351 +0.003 _ 0.356 +0.005 _ 0.103 +0.005 _ 0.324 0.316 0.050 0.040 0.059 0.020 0.040 0.100 0.026 typical • • • The package is not hermetically sealed (the crystal unit inside is hermetically sealed). The sides are intentionally left open to permit cleaning material to freely flow in the package, thus minimizing the accumulation of contaminants during cleaning processes. The internal part of the package must be thoroughly dry before operating. Pad 1 2 Function No connect Output Enable/Disable Ground (GND) Output Output* Supply Voltage (VCC) Note There is no internal connection to this pad When this pad is not connected the oscillator shall operate. When this pad is