PL611S-17-XXXUIR

( Preliminary) PL611s-17 1 .8V-3.3V PicoPLL TM K Hz to MHz Programmable Clock F EATURES • A dvanced Programmable PLL design for lowfrequency (kHz) input applications. • I nput Frequency: 10kHz to 200MHz • O TP selectable AC/DC Input Coupling. • A ccepts > 0.1V reference signal input voltage • Very low Jitter and Phase Noise • O utput Frequency: o < 65MHz @ 1.8V operation o < 90MHz @ 2.5V operation o < 125MHz @ 3.3V operation • Disabled outputs programmable as HiZ or Active Low. • O ffered in Tiny G REEN /RoHS compliant packages o 6 -pin DFN (2.0mmx1.3mmx0.6mm) o 6 -pin SC70 (2.3mmx2.25mmx1.0mm) o 6 -pin SOT23 (3.0mmx3.0mmx1.35mm) • S ingle 1.8V, 2.5V, or 3.3V ± 10% power supply • O perating temperature range from -40 ° C to 85 ° C DESCRIPTION T he PL611s-17 is a low-cost general purpose frequency synthesizer and a member of PhaseLink’s PicoPLL TM F actory Programmable ‘Quick Turn Clock (QTC)’ family. Designed to fit in a small SOT23, SC70, or DFN package for high performance, low power applications, the PL611s-17 accepts a low frequency (>10KHz) Reference input and generates up to 125MHz outputs with the best phase noise, jitter performance, and power consumption for handheld devices and notebook applications. In addition, one programmable I/O pin can be configured as Output Enable (OE), Frequency switching (FSEL), Power Down (PDB) input, or CLK1 (F OUT , F REF , F REF /2) output. Cascading the PL611s17 with other PicoPLL ICs can result in producing all required system clocks with specific savings in board space, power consumption, and cost. P ACKAGE PIN CONFIGURATION OE, PDB, FSEL, CLK1 VDD FIN LF 1 2 3 6 5 4 CLK0 GND GND CLK0 LF SOT23 23SOT23-6L (3.0mmx3.0mmx1.35mm) mmx3 mmx1 35mm) mm 3 2 PL611s-17 1 6 5 4 FIN OE, PDB, FSEL, CLK1 VDD PL611s-17 PL611s-17 PL611s-17 PL611s-17 FIN OE, PDB, FSEL, CLK1 VDD 1 2 3 6 5 4 LF GND CLK0 DFNDFN-6L (2.0mmx1.3mmx0.6mm) mmx1 mmx0 mm) B LOCK DIAGRAM Ref. R-Counter (7-bit) M-Counter (16-bit) PL611s-17 PL611s-17 PL611s-17 PL611s-17 SC70 70SC70-6L (2.3mmx2.25mmx1.0mm) mmx2 25mmx1 mm) mmx FIN Phase Detector Charge Pump FVCO = FRef * (M/R) VCO Programmable Function FOut = FVCO P-Counter (4-bit) /2*P CLK0 Programming Logic OE, PDB, FSEL, CLK1 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 01/04/07 Page 1 ( Preliminary) PL611s-17 1 .8V-3.3V PicoPLL TM K Hz to MHz Programmable Clock K EY PROGRAMMING PARAMETERS CLK Output Frequency FOUT = FREF * (M / R) /(2*P) Where M=16 bit R= 7 bit P= 4 bit CLK0 = FOUT, FREF or FREF / (2*P) CLK1 = FREF, FREF/2, CLK0 or CLK0/2 Output Drive Strength Three optional drive strengths to choose from: • Low: 4mA • Std: 8mA (default) • High: 16mA Programmable Input/Output One output pin can be configured as: • • • • • OE - input FSEL - input PDB - input CLK1 – output HiZ or Active Low disabled state PACKAGE PIN ASSIGNMENT N ame V DD SOT Pin# 1 P in # SC70 Pin# 2 DFN Pin# 3 Type P VDD connection. Description This programmable I/O pin can be configured as Output Enable (OE) input, Power Down (PDB) input, Frequency Selector (FSEL) or CLK1 clock output. This pin has an internal 10M pull up resistor (OE, PDB & FSEL Only). O E, PDB, FSEL, CLK1 2 1 2 I/O T he OE and PDB features can be programmed to allow the output to float (Hi Z), or to operate in the ‘Active low’ mode. S tate 0 1 ( default) OE D isable CLK Normal mode PDB Power Down Mode Normal mode FSEL Frequency ‘2’ Frequency ‘1’ F IN LF G ND C LK0 3 4 5 6 3 4 5 6 1 6 5 4 I I P O Reference input pin. Loop Filter input pin. GND connection Programmable Clock Output 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 01/04/07 Page 2 ( Preliminary) PL611s-17 1 .8V-3.3V PicoPLL TM K Hz to MHz Programmable Clock F UNCTIONAL DESCRIPTION P L611s-17 is a highly featured, very flexible, advanced programmable PLL design for high performance, lowpower, small form-factor applications. The PL611s-17 accepts a reference clock input of 10kHz to 200MHz and is capable of producing two outputs up to 125MHz. This flexible design allows the PL611s-17 to deliver any PLL generated frequency, F REF ( Ref Clk) frequency or F REF / (2*P) to CLK0 and/or CLK1. Some of the design features of the PL611s-17 are mentioned below: P LL Programming T he PLL in the PL611s-17 is fully programmable. The PLL is equipped with an 7-bit input frequency divider (R-Counter), and an 16-bit VCO frequency feedback loop divider (M-Counter). The output of the PLL is transferred to a 4-bit post VCO divider (PCounter). The output frequency is determined by the following formula [FOUT = FREF * (M / R) / (2 * P) ]. C lock Output (CLK0) C LK0 is the main clock output. The PL611s-17 can also be programmed to provide a second clock output, CLK1, on the programmable I/O pin (see OE/PDB/FSEL/CLK1 pin description below). The output of CLK0 can be configured as the PLL output (F VCO /(2*P)), F REF ( Ref Clk Frequency) output, or F REF /(2*P) output. The output drive level can be programmed to Low Drive (4mA), Standard Drive (8mA) or High Drive (16mA). The maximum output frequency is 125MHz. Clock Output (CLK1) T he CLK1 feature allows the PL611s-17 to have an additional clock output. This output can be programmed to one of the following: FREF - Reference ( Ref Clk ) Frequency FREF / 2 CLK0 CLK0 / 2 Power-Down Control (PDB) T he Power Down (PDB) feature allows the user to put the PL611s-17 into “Sleep Mode”. When activated (logic ‘0’), PDB ‘Disables the PLL, the oscillator circuitry, counters, and all other active circuitry. In Power Down mode the IC consumes 10kHz and produce a clock output in the MHz range, as shown in the diagram ‘1’, below. Also, to save costs in consumer product system designs and for greater area optimization, it is possible to use the XOUT of the RTC crystal (32.768KHz) as the reference input to the PL611s-17, as shown in diagram ‘2’, below. XIN C1 REFIN OE, PDB FSEL, CLK1 1.8~3.3V XIN 32.768 KHz ASIC 1 2 3 6 5 4 D iagram ‘1’ N ote: An AC Coupling Cap may be required if RTC Clock amplitude is too small. G UIDELINES FOR EXTERNAL COMPONENT SELECTION F or the optimum performance, an accurate external loop filter capacitor must be selected. A general guideline for selecting this component based on the input frequency is shown in the table below. I nput Frequency 3MHz ~ 200MHz 300KHz ~ 10MHz 30KHz ~ 1.0MHz 10KHz ~ 100KHz Capacitor Value 1.0nF 1.0nF 4.7nF 47nF T he optimal way to choose the value is using the following formula: C (nF) = 0.8 + M/280 W here C = Loop Filter Capacitor value (in nF) M = M counter value. Provided by PhaseLink with device samples. Notes: * F ind the closest commercially available value. Values in the E12 range with 5% tolerance are acceptable. * With possible M-counter values between 1 and 65536, the capacitor value is expected in the range 820pF thru 220nF. 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 01/04/07 Page 4 PL611s-17 PL611s-17 PL611s-17 PL611s-17 LF LFGND MHZ CLK (Any Frequency) C2 XOUT XOUT REFIN OE, PDB FSEL, CLK1 1.8~3.3V 1 2 3 6 5 4 D iagram ‘2’ PL611s-17 LF LFGND MHZ CLK (Any Frequency) ( Preliminary) PL611s-17 1 .8V-3.3V PicoPLL TM K Hz to MHz Programmable Clock E LECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS P ARAMETERS S upply Voltage Range I nput Voltage Range O utput Voltage Range S oldering Temperature (Green package) D ata Retention @ 85 ° C S torage Temperature A mbient Operating Temperature* TS 10 - 65 -40 150 85 SYMBOL V DD VI VO MIN. - 0.5 - 0.5 - 0.5 MAX. 7 V DD +0.5 V DD +0.5 260 UNITS V V V °C Year °C °C Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only. AC SPECIFICATIONS PARAMETERS @ V DD = 3.3V I nput (FIN) Frequency @ V DD = 2.5V @ V DD = 1.8V I nput (FIN) Signal Amplitude I nput (FIN) Signal Amplitude Internally AC/DC coupled (High Frequency) Internally AC/DC coupled (Low Frequency) 3.3V < 50MHz, 2.5V < 40MHz, 1.8V < 15MHz @ VDD = 3.3V O utput Frequency @ VDD = 2.5V @ VDD = 1.8V S ettling Time O utput Enable Time O utput Rise Time O utput Fall Time D uty Cycle P eriod Jitter, Pk-to-Pk* (measured from 10,000 samples) At power-up (after VDD i ncreases over 1.62V) O E Function; Ta=25º C, 15pF Load PDB Function; Ta=25º C, 15pF Load 15pF Load, 10/90% VDD, High Drive, 3.3V 15pF Load, 90/10% VDD, High Drive, 3.3V VDD / 2 With capacitive decoupling between VDD a nd GND. 45 1.2 1.2 50 70 0.9 0.1 10KHz CONDITIONS MIN. TYP. MAX. 200 166 133 VDD VDD 125 90 65 2 10 2 1.7 1.7 55 UNITS MHz V pp V pp MHz ms ns ms ns ns % ps * N ote: Jitter performance depends on the programming parameters. 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 01/04/07 Page 5 ( Preliminary) PL611s-17 1 .8V-3.3V PicoPLL TM K Hz to MHz Programmable Clock D C SPECIFICATIONS PARAMETERS S upply Current, Dynamic, with Loaded CMOS Outputs S upply Current, Dynamic, with Loaded CMOS Outputs S upply Current, Dynamic with Loaded CMOS Outputs O perating Voltage O utput Low Voltage O utput High Voltage O utput Current, Low Drive O utput Current, Standard Drive O utput Current, High Drive SYMBOL I DD I DD I DD V DD V OL V OH I OSD I OSD I OHD CONDITIONS @ VDD = 3.3V,30MHz, load=15pF @ VDD = 2.5V,30MHz, load=15pF @ VDD = 1.8V,30MHz, load=5pF MIN. TYP. 6.0 3.9 2.1* MAX. UNITS mA mA mA 1 .62 I OL = + 4mA Standard Drive I OH = - 4mA Standard Drive V OL = 0 .4V, V OH = 2 .4V V OL = 0 .4V, V OH = 2 .4V V OL = 0 .4V, V OH = 2 .4V V DD – 0 .4 4 8 16 3.63 0.4 V V V mA mA mA 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 01/04/07 Page 6 ( Preliminary) PL611s-17 1 .8V-3.3V PicoPLL TM K Hz to MHz Programmable Clock PCB LAYOUT CONSIDERATIONS FOR PERFORMANCE OPTIMIZATION T he following guidelines are to assist you with a performance optimized PCB design: - Keep all the PCB traces to PL611s-17 as short as possible, as well as keeping all other traces as far away from it as possible. - When a reference input clock is generated from a crystal (see diagram above), place the PL611s-17 ‘FIN’ as close as possible to the ‘Xout’ crystal pin. This will reduce the cross-talk between the reference input and the other signals. - Place the Loop Filter (LF) components as close to the package pin of PL611s-17 as possible. - Place a 0.01 F~0.1 F decoupling capacitor between VDD and GND, on the component side of the PCB, close to the VDD pin. It is not recommended to place this component on the backside of the PCB. Going through vias will reduce the signal integrity, causing additional jitter and phase noise. - It is highly recommended to keep the VDD and GND traces as short as possible. - When connecting long traces (> 1 inch) to a CMOS output, it is important to design the traces as a transmission line or ‘stripline’, to avoid reflections or ringing. In this case, the CMOS output needs to be matched to the trace impedance. Usually ‘striplines’ are designed for 50 impedance and CMOS outputs usually have lower than 50 impedance so matching can be achieved by adding a resistor in series with the CMOS output pin to the ‘stripline’ trace. - Please contact PhaseLink for the application note on how to design outputs driving long traces or the Gerber files for the PL611s-17 layout. 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 01/04/07 Page 7 ( Preliminary) PL611s-17 1 .8V-3.3V PicoPLL TM K Hz to MHz Programmable Clock PACKAGE DRAWINGS ( GREEN P ACKAGE COMPLIANT) SOT23-6 L Symbol A A1 A2 b c D E H L e SC70-6L Symbol A A1 A2 b c D E H L e DFN-6L D1 Dimension in MM Min. Max. 1.05 1.35 0.05 0.15 1.00 1.20 0.30 0.50 0.08 0.20 2.80 3.00 1.50 1.70 2.60 3.00 0.35 0.55 0.95 BSC Pin1 Dot E H D A2 A A1 e b C L Dimension in MM Min. Max. 0.80 1.00 0.00 0.09 0.80 0.91 0.15 0.30 0.08 0.25 1.85 2.25 1.15 1.35 2.00 2.30 0.21 0.41 0.65BSC Pin1 Dot E H D A2 A A1 e b C L Symbol A A1 A3 b e D E D1 E1 L Dimension in MM Min. Max. 0.50 0.60 0.00 0.05 0.152 0.152 0.15 0.25 0.40BSC 1.25 1.35 1.95 2.05 0.75 0.85 0.95 1.05 0.20 0.30 b e Pin 6 ID Chamfer E1 E D Pin1 Dot L Bottom View A A1 Top View A3 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 01/04/07 Page 8 ( Preliminary) PL611s-17 1 .8V-3.3V PicoPLL TM K Hz to MHz Programmable Clock O RDERING INFORMATION ( GREEN P ACKAGE COMPLIANT) For part ordering, please contact our Sales Department: 4 7745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 P ART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range P L611s-17-XXX X X X P ART NUMBER 3 DIGIT ID Code * (will be assigned at programming time) PACKAGE TYPE G=DFN-6L U=SC70-6L T=SOT-6L Part/Order Number PL611s-17-XXXGC-R PL611s-17-XXXUC-R PL611s-17-XXXTC-R † NONE= TUBE R=TAPE and REEL T EMPERATURE C=COMMERCIAL I=INDUSTRIAL Marking† XXX XXX 17XXX Package Option 6-Pin DFN (Tape and Reel) 6-Pin SC70 (Tape and Reel) 6-Pin SOT23 (Tape and Reel) N ote: ‘XXX’ designates marking identifier that could be independent of the part number. P haseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. L IFE SUPPORT POLICY : PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. S older reflow profile available at w ww.phaselink.com/QA/solderingGreen.pdf 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 01/04/07 Page 9