PLL602-30

P LL602-30 7 50kHz – 800MHz Low Phase Noise XO (for 12 – 25MHz Crystals) F EATURES • • 7 50kHz to 800MHz output range. L ow phase noise output (@ 10kHz frequency offset, -142dBc/Hz for 19.44MHz, -123dBc/Hz for 106.25MHz, -125dBc/Hz for 155.52MHz, 115dBc/Hz for 622.08MHz). S electable CMOS, PECL and LVDS output. S electable High Drive (30mA) or Standard Drive (10mA) output. 1 2MHz to 25MHz crystal input. O utput Enable selector. 3 .3V operation. A vailable in DIE (65 mil x 62 mil). DIE CONFIGURATION 65 mil OUTSEL0^ OUTSEL1^ SEL0^ SEL1^ VDD VDD VDD VDD (1550,1475) 17 16 25 24 23 22 21 20 19 18 GNDBUF CMOS LVDSB PECLB VDDBUF VDDBUF PECL LVDS OE_SEL^ XIN XOUT SEL3 62 mil 26 • • • • • • Die ID: A1414-14E 27 15 28 14 13 SEL2 29 12 11 OE_CTRL N/C 30 C502A 10 31 1 2 3 4 5 6 7 8 9 D ESCRIPTION T he PLL602-30 is a monolithic low jitter and low phase noise (-142dBc/Hz @ 10kHz offset) XO IC Die, with selectable CMOS, LVDS or PECL output, covering the 750kHz to 800MHz output range, using a low frequency crystal. This makes the PLL602-30 ideal as a universal die for applications ranging from low frequency to SONET. Y X (0,0) GND GND GND GND GND N/C GND OUTPUT SELECTION AND ENABLE O UTSEL1 (Pad #18) 0 0 1 1 O UTSEL0 (Pad #25) 0 1 0 1 O E_CTRL (Pad #30) 0 ( Default) 1 0 1 (Default) T ri-state T ri-state Output enabled Selected Output H igh Drive CMOS S tandard CMOS P ECL L VDS S tate Output enabled D IE SPECIFICATIONS N ame S ize R everse side P ad dimensions T hickness Value 62 x 65 mil GND 80 micron x 80 micron 10 mil O E_SELECT (Pad #9) 0 1 ( Default) B LOCK DIAGRAM P ad #9: Bond to GND to set to “0”, bond to VDD to set to “1” Pad #30: Logical states defined by PECL levels if OE_SELECT (pad #9) is “0” Logical states defined by CMOS levels if OE_SELECT is “1” VCO Divider Charge Pump + Loop Filter VCO SEL Reference Divider XTAL OSC Phase Detector CLKBAR CLK XIN XOUT OE 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 09/03/04 Page 1 GNDBUF P LL602-30 7 50kHz – 800MHz Low Phase Noise XO (for 12 – 25MHz Crystals) F REQUENCY SELECTION TABLE S EL3 (Pad #28) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SEL2 (Pad #29) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SEL1 (Pad #19) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SEL0 (Pad #20) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Selected Multiplier R eserved R eserved R eserved F in x 32 R eserved R eserved F in / 8 F in x 2 R eserved F in / 2 F in / 16 F in x 4 F in / 4 F in x 8 F in x 16 N o multiplication A ll pads have internal pull-ups (default value is 1). Bond to GND to set to 0. E LECTRICAL SPECIFICATIONS 1 . Absolute Maximum Ratings P ARAMETERS S upply Voltage I nput Voltage, dc O utput Voltage, dc S torage Temperature A mbient Operating Temperature* J unction Temperature L ead Temperature (soldering, 10s) E SD Protection, Human Body Model SYMBOL V DD VI VO TS TA TJ MIN. - 0.5 - 0.5 - 65 - 40 MAX. 4 .6 V DD +0.5 V DD +0.5 150 85 1 25 260 2 UNITS V V V °C °C °C °C kV E xposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * N ote : Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2 . Crystal Specifications P ARAMETERS C rystal Resonator Frequency C rystal Loading Rating R ecommended ESR SYMBOL F XIN C L (xtal) RE CONDITIONS P arallel Fundamental Mode A T cut MIN. 12 TYP. 20 MAX. 25 30 UNITS MHz pF Ω 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 09/03/04 Page 2 P LL602-30 7 50kHz – 800MHz Low Phase Noise XO (for 12 – 25MHz Crystals) 3 . General Electrical Specifications P ARAMETERS S upply Current, Dynamic (with Loaded Outputs) O perating Voltage O utput Clock Duty Cycle S hort Circuit Current SYMBOL I DD V DD CONDITIONS P ECL/LVDS/CMOS F out