PO74G373ATR

OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS PO54G373A, PO74G373A 10/22/07 54, 74 Series GHz Logic FEATURES: . Patented technology . Operating frequency up to 1.125GHz with 2pf load . Operating frequency up to 700MHz with 5pf load . Operating frequency up to 350MHz with 15pf load . Operating frequency up to 100MHz with 50pf load . VCC Operates from 1.65V to 3.6V . Propagation delay < 1.8ns max with 15pf load . Low input capacitance: 4pf typical . Available in 20pin TSSOP package . Available in 20pin Ceramic Dual Flatpack . Available in 20pin Leadless Ceramic Chip Carrier DESCRIPTION: Potato Semiconductor’s PO74G373A is designed for world top performance using submicron CMOS technology to achieve higher than 1.125GHz TTL /CMOS output frequency with less than 1.8ns propagation delay. This dual Octal transparent D-type latches are designed for 1.65-V to 3.6-V VCC operation. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V/5V system environment. Pin Configuration 1D 1Q OE VCC 2D 2Q 3Q 3D 4D 10 11 Pin Description INPUTS OE L L L H LE H H L X D H L X X OUTPUT Q H L Q0 Z Logic Block Diagram OE 1 LE 11 C1 2 4Q GND LE 5Q 5D OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q LE 4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13 8Q 8D 7D 7Q 6Q 6D 1D 3 1D 1Q To Seven Other Channels 1 C opyright © Potato Semiconductor Corporation OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS PO54G373A, PO74G373A 10/22/07 54, 74 Series GHz Logic Maximum Ratings Description Storage Temperature Operation Temperature Operation Voltage Input Voltage Output Voltage Max -65 to 150 -55 to 125 -0.5 to +4.6 -0.5 to +5.5 -0.5 to Vcc+0.5 Unit °C °C V V V Note: stresses greater than listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability specification is not implied. DC Electrical Characteristics Symbol Description Output High voltage Output Low voltage Input High voltage Input Low voltage Input High current Input Low current Clamp diode voltage Test Conditions Vcc=3V Vin=VIH or VIL, IOH= -12mA Vcc=3V Vin=VIH or VIL, IOH=12mA Guaranteed Logic HIGH Level (Input Pin) Guaranteed Logic LOW Level (Input Pin) Vcc = 3.6V and Vin = 5.5V Vcc = 3.6V and Vin = 0V Vcc = Min. And IIN = -18mA Min Typ M ax Unit VOH VOL VIH VIL IIH IIL VIK Notes: 1. 2. 3. 4. 5. 2.4 2 -0.5 - 3 0.3 -0.7 0.5 5.5 0.8 1 -1 -1.2 V V V V uA uA V For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25 ° C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. VoH = Vcc – 0.6V at rated current 2 Copyright © Potato Semiconductor Corporation OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS PO54G373A, PO74G373A 10/22/07 54, 74 Series GHz Logic Power Supply Characteristics Symbol Description Quiescent Power Supply Current Test Conditions (1) Vcc=Max, Vin=Vcc or GND M in Typ M ax Unit IccQ Notes: 1. 2. 3. 4. - 0.1 30 uA For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25° C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. Capacitance Parameters (1) Description Input Capacitance Output Capacitance Test Conditions Vin = 0V Vout = 0V Typ Unit Cin Cout Notes: 4 6 pF pF 1 This parameter is determined by device characterization but not production tested. Switching Characteristics Symbol Description Setup time before LE Hold time, data after LE Propagation Delay D to Q Propagation Delay LE to Q Output Enable Time Output Disable Time Rise/Fall Time Input Frequency Input Frequency Input Frequency Input Frequency CL = 15pF CL = 15pF CL = 15pF 0.8V – 2.0V CL= 50pF CL= 15pF CL= 5pF CL= 2pF Test Conditions (1) M ax tsu th tpd tPZH or tPZL tPHZ or tPLZ tr/tf fmax fmax fmax fmax Notes: - Min Unit 0.5 0.5 1.8 2.0 2.5 2.5 ns ns ns ns ns ns ns MHz MHz MHz MHz 0.8 - 100 350 700 1125 1. See test circuits and waveforms. 2. tPLH, tPHL, tsu, and th are production tested. All other parameters guaranteed but not production tested. 3. Airflow of 1m/s is recommended for frequencies above 500MHz 3 Copyright © Potato Semiconductor Corporation OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS PO54G373A, PO74G373A 10/22/07 54, 74 Series GHz Logic Test Waveforms VI Timing Input tw VI Input VM VM 0V VOLTAGE WAVEFORMS PULSE DURA TION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Data Input tsu VM th VI VM 0V VM 0V VI Input tPLH Output tPHL Output VM VM VM VM 0V tPHL VOH VM VOL tPLH VOH VM VOL VOLTAGE WAVEFORMS PROPAGA TION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Control tPZL VI VM VM 0V tPLZ VLOAD/2 VM tPZH VOL + VΔ tPHZ VM VOH - VΔ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING VOL Output Waveform 1 S1 at V LOAD (see Note B) Output Waveform 2 S1 at GND (see Note B) Test Circuit Vcc Pulse Generator D.U.T 50Ω 50pF to 2pF 4 Copyright © Potato Semiconductor Corporation OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS PO54G373A, PO74G373A 10/22/07 54, 74 Series GHz Logic Packaging Mechanical Drawing: 20 pin TSSOP 20 .169 .177 4.3 4.5 .018 .030 0.45 0.75 .238 .269 6.1 6.7 1 .252 .260 6.4 6.6 .047 1.20 Max SEATING PLANE .004 0.09 .008 0.20 .0256 BSC 0.65 .007 0.19 .012 0.30 .002 0.05 .006 0.15 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Packaging Mechanical Drawing: 20pin Leadless Ceramic Chip Carrier 5 Copyright © Potato Semiconductor Corporation OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS PO54G373A, PO74G373A 10/22/07 54, 74 Series GHz Logic Packaging Mechanical Drawing: 20pin Ceramic Dual Flatpack 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.080 (2,03) 0.064 (1,63) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 3 2 1 13 12 0.045 (1,14) 0.035 (0,89) 4 0.358 (9,09) 0.342 (8,69) 5 6 0.358 (9,09) 7 0.307 (7,80) 8 18 17 16 15 14 X.XX Denotes dimensions in inches X.XX X.XX Denotes dimensions in millimenters X.XX 9 10 11 12 13 Ordering Information Ordering Code PO74G373ATU PO74G373ATR PO54G373ALU PO54G373AFU 20pin TSSOP 20pin TSSOP 20pin Leadless Ceramic Chip Carrier 20pin Ceramic Dual Flatpack Package Tube Tape and reel Tube Tube Pb-free & Green Pb-free & Green Pb-free & Green Pb-free & Green Top-Marking PO74G373AT PO74G373AT PO54G373AL PO54G373AF TA -40°C to 85°C -40°C to 85°C -55°C to 125° C -55°C to 125° C IC Package Information PACKAGE CODE PACKAGE TYPE TAPE WIDTH (mm) TAPE PITCH (mm) PIN 1 LOCATION TAPE TRAILER LENGTH QTY PER REEL TAPE LEADER LENGTH QTY PER TUBE T L F TSSOP 20 LCCC 20 CFP 20 16 N/A N/A 8 N/A N/A Top Left Corner N/A N/A 39 (12”) N/A N/A 3000 N/A N/A 64 (20”) N/A N/A 74 55 85 6 Copyright © Potato Semiconductor Corporation