InnoSwitch3-PD Family
Off-Line QR Flyback Switcher IC with Integrated USB
Type-C and USB PD Controller, High-Voltage Switch,
Synchronous Rectification and FluxLink Feedback
Product Highlights
VBUS
InnoSwitch3-PD
VB/D
VOUT
IS
uVCC
GND
V
CONTROL
NTC
CC1
Primary Switch
and Controller
CC2
S
Highly Integrated, Compact Footprint
• Multi-mode Quasi-Resonant (QR) / DCM / CCM flyback controller,
high-voltage switch, secondary-side sensing and synchronous
rectifier driver
• Optimized efficiency across line and load range
• Integrated FluxLink™, HIPOT-isolated, feedback link
• Instantaneous transient response
• Drives low-cost N-channel FET series load switch
D
BPS
RTN
SR
USB Power Delivery 3.0 + PPS provider and QC4 support
Compliant with USB Type-C Rev. 1.3
Integrated VCONN FETs with soft start and over-current protection
Supports electronically marked cables
Configurable pull-up resistor Rp
On chip temperature sensor
Telemetry for power supply status and fault monitoring
PowiGaN™ technology – up to 100 W without heat sinks
Dedicated NTC pin for temperature sense
FWD
•
•
•
•
•
•
•
•
•
Type-C
USB Type C and PD Controller
BPP
Secondary
Control IC
PI-9205-112221
Figure 1. Typical Application Schematic.
EcoSmart™ – Energy Efficient
• No-load consumption as low as 14 mW
• Enables power supply designs that easily comply with all global
energy efficiency regulations
• Low heat dissipation
Advanced Protection / Safety Features
• Input voltage monitoring with accurate brown-in/brown-out and
overvoltage protection
• Output OV/UV fault detection with independently configured responses
• Open SR FET gate detection
• Hysteretic thermal shutdown
• Programmable watchdog timer for system faults
• Integrated high voltage FETs for VBUS short protection on CC1, CC2
Full Safety and Regulatory Compliance
•
•
•
•
Reinforced insulation
Isolation voltage >4000 VAC
100% production HIPOT compliance testing
UL1577 isolation voltage 4000 VAC (max) and TUV (EN62368) safety
approved
Green Package
• Halogen free and RoHS compliant
Applications
• High efficiency USB PD 3.0 + PPS adapters for smart phones,
tablets, notebooks, digital cameras, and Bluetooth accessories
• Quick Charge protocol based power adapters
• Direct-charge mobile device chargers
Description
The InnoSwitch™3-PD dramatically simplifies the development and
manufacturing of USB PD power supplies by incorporating primary
switch and controller, isolated feedback, secondary control and USB PD
controller into a single package.
www.power.com
Figure 2. High Creepage, Safety-Compliant InSOP-24D Package.
Output Power Table1
Product 4,5
230 VAC ± 15%
Adapter2
85-265 VAC
Open
Frame3
Adapter2
Open
Frame3
INN3865C/75C
25 W
30 W
22 W
25 W
INN3866C/76C
35 W
40 W
27 W
36 W
INN3877C
40 W
45 W
36 W
40 W
INN3867C
45 W
50 W
40 W
45 W
INN3868C
55 W
65 W
50 W
55 W
INN3878C
70 W
75 W
55 W
65 W
INN3879C
80 W
85 W
65 W
75 W
INN3870C
90 W
100 W
75 W
85 W
INN3896C
25 W
35 W
20 W
30 W
Table 1. Output Power Table.
Notes:
1. Maximum output power is dependent on the design, with maximum IC
package temperature kept tAR(SK).
The second is included to ensure that if communication is lost, the
primary tries to restart. Although this should never be the case in
normal operation, it can be useful when system ESD events (for
example) causes a loss of communication due to noise disturbing the
secondary controller. The issue is resolved when the primary
restarts after an auto-restart off-time.
The auto-restart is reset as soon as an AC reset occurs.
SOA Protection
In the event that there are two consecutive cycles where the drain
current is reached 110% of ILIM within ~500 ns (the blanking time +
current limit delay time) (including leading edge current spike), the
controller will skip 2.5 cycles or ~25 ms (based on full frequency of
100 kHz). This provides sufficient time for the transformer to reset
with large capacitive loads without extending the start-up time.
Input Line Voltage Monitoring
The UNDER/OVER INPUT VOLTAGE pin is used for input undervoltage
and overvoltage sensing and protection.
A sense resistor is tied between the high-voltage DC bulk capacitor
after the bridge (or to the AC side of the bridge rectifier for fast AC
reset) and the UNDER/OVER INPUT VOLTAGE pin to enable this
functionality. This function can be disabled by shorting the UNDER/
OVER INPUT VOLTAGE pin to primary GND.
At power-up, after the primary bypass capacitor is charged and the
ILIM state is latched, and prior to switching, the state of the UNDER/
OVER INPUT VOLTAGE pin is checked to confirm that it is above the
brown-in and below the overvoltage shutdown thresholds.
In normal operation, if the UNDER/OVER INPUT VOLTAGE pin current
falls below the brown-out threshold and remains below brown-in for
longer than tUV-, the controller enters auto-restart. Switching will
only resume once the UNDER/OVER INPUT VOLTAGE pin current is
above the brown-in threshold.
In the event that the UNDER/OVER INPUT VOLTAGE pin current is
above the overvoltage threshold, the controller will also enter
auto-restart. Again, switching will only resume once the UNDER/
OVER INPUT VOLTAGE pin current has returned to within its normal
operating range.
The input line UV/OV function makes use of a internal high-voltage
switch on the UNDER/OVER INPUT VOLTAGE pin to reduce
power consumption. The controller samples the input line at light
load conditions when the time between switching cycles is 50 msec or
more. At 89% for
the largest device.
3. Transformer primary inductance tolerance of ±10%.
4. Reflected output voltage (VOR) is set to maintain KP = 0.8 at
minimum input voltage conditions for universal line and KP = 1 for
high input line conditions.
5. Maximum conduction losses for adapter ratings is limited to 0.6 W
and 0.8 W for open frame.
6. Increased current limit is selected for peak and open frame power
columns and standard current limit for adapter columns.
7. The part is board mounted with SOURCE pins soldered to a
sufficient area of copper and/or a heat sink is used to keep the
SOURCE pin temperature at or below 110 °C.
8. Ambient temperature of 50 °C for open frame designs and 40 °C
for sealed adapters.
*Below a value of 1, KP is the ratio of ripple to peak primary current.
To prevent reduced power delivery, due to premature termination of
switching cycles, a transient KP limit of ≥0.25 is recommended. This
prevents the initial current limit (IINT) from being exceeded at switch
turn-on.
Primary-Side Overvoltage Protection
The primary-side output overvoltage protection provided by the
InnoSwitch3-PD IC triggered by a threshold current of ISD into the
PRIMARY BYPASS pin. In addition to an internal filter, the PRIMARY
BYPASS pin capacitor forms an external filter providing noise immunity
from inadvertent triggering. For the bypass capacitor to be effective
as a high frequency filter, the capacitor should be located as close as
possible to the SOURCE and PRIMARY BYPASS pins of the device.
The primary sensed OVP function can be realized by connecting a
series combination of a Zener diode and a resistor from the rectified
and filtered bias winding voltage supply to the PRIMARY BYPASS pin.
The rectified and filtered bias winding output voltage may be higher
than expected (up to 1.5x or 2x the desired value) due to poor
coupling of the bias winding with the output winding and the resulting
ringing on the bias winding voltage waveform. It is therefore
recommended that the rectified bias winding voltage be measured.
This measurement should be ideally done at the lowest input voltage
and with highest load on the output. This measured voltage should
be used to select the components required to achieve primary sensed
OVP. It is recommended that a Zener diode with a clamping voltage
approximately 6 V lower than the bias winding rectified voltage at
which OVP is expected to be triggered be selected. The value of the
series resistor required can be calculated such that a current higher
than ISD will flow into the PRIMARY BYPASS pin during any output
overvoltage.
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Rev. E 11/22
InnoSwitch3-PD
Reducing No-Load Consumption
The InnoSwitch3-PD IC can start in self-powered mode from the
PRIMARY BYPASS pin capacitor charged through the internal current
source. Use of a bias winding is however required to provide supply
current to the PRIMARY BYPASS pin once the InnoSwitch3-PD IC has
become operational. Auxiliary or bias winding provided on the
transformer is required for this purpose. The addition of a bias
winding that provides bias supply to the PRIMARY BYPASS pin
enables design of power supplies with no-load power consumption
down to 5 V).
A glass passivated standard recovery rectifier diode with low junction
capacitance is recommended to prevent the snappy recovery typically
seen with fast or ultrafast diodes that can lead to higher radiated EMI.
An aluminum capacitor of at least 22 mF with a voltage rating 1.2
times greater than the highest voltage developed across the capacitor
is recommended. Highest voltage is typically developed across this
capacitor when the supply is operated at the highest rated output
voltage and rated load with the lowest input AC supply voltage. It is
recommended to ground the bias winding capacitor to the negative of
the input bulk capacitor than the SOURCE pin.
Line UV and OV Protection
Resistors connected from the UNDER/OVER INPUT VOLTAGE pin to
the DC bus enable sensing of input voltage to provide line undervoltage and overvoltage protection. For a typical universal input
application, a resistor value of approximately 3.8 MW is recommended.
Figure 16 shows circuit configurations that enable selectively either
the line UV or the line OV feature, disabling the other.
The InnoSwitch3-PD IC features a primary sensed OV protection
feature that can be used to latch-off/AR the power supply. Once the
power supply is in latch-off/AR, it can be reset if the UNDER/OVER
INPUT VOLTAGE pin current is reduced to zero. Once the power
supply is latched off, even after input supply is turned off, it can take
considerable amount of time to reset InnoSwitch3-PD IC controller as
the energy stored in the DC bus will continue to provide bias supply
to the controller. In case of latch-off, a fast AC reset can be achieved
using the modified circuit configuration shown in Figure 17. The voltage
across capacitor CS reduces rapidly after input supply is disconnected
reducing current into the INPUT VOLTAGE MONITOR pin of the
InnoSwitch3-PD IC and resetting the InnoSwitch3-PD IC controller.
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Rev. E 11/22
InnoSwitch3-PD
+
R1
VB/D
VOUT
IS
GND
BPS
V
SR
D
FWD
R2
CONTROL
S
uVCC
CC1
CC2
BPP
InnoSwitch3-PD
(a)
+
PI-8546a-051321
R1
1N4148
VB/D
VOUT
IS
GND
BPS
V
SR
D
FWD
R2
CONTROL
S
uVCC
CC1
CC2
BPP
InnoSwitch3-PD
(b)
PI-8547a-051321
Figure 16. Figure 2. (a) Line UV Only; (b) Line OV Only.
CS
100 nF
InnoSwitch3-PD
Primary FET
and Controller
CONTROL
S
BPP
VB/D
VOUT
IS
GND
BPS
V
SR
D
FWD
SR FET
uVCC
CC1
CC2
Secondary
Control IC
PI-8548b-112221
Figure 17. Fast AC Reset Configuration.
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Rev. E 11/22
InnoSwitch3-PD
Primary Sensed OVP (Overvoltage Protection)
The voltage developed across the output of the bias winding tracks
the power supply output voltage. Though not precise, a reasonable
approximation of the state of the output voltage can be determined
by the primary-side controller using the bias winding voltage. A
Zener diode connected between the bias winding output and the
PRIMARY BYPASS pin can reliably detect a secondary overvoltage
fault and cause the primary-side controller to latch-off/AR. It is
recommended that the highest voltage at the output of the bias
winding be measured for normal (steady-state) conditions at full rated
load and lowest rated input voltage and also under transient load
conditions. A Zener diode rated, for 1.25 times this measured voltage
will ensure that OVP protection will not trigger under any normal
operating conditions but will operate in case of a fault condition.
Primary-Side Snubber Clamp
A snubber circuit should be used on the primary-side as shown in the
example circuit in Figure 15. This prevents excess voltage spikes at
the Drain of the switch at the instant of turn-off of the switch during
each switching cycle. Though conventional RCD clamps can be used,
RCDZ clamps offer the highest efficiency. The circuit example shown
in Figure 15 uses RCD clamp with a resistor in series with the clamp
diode. This resistor dampens the ringing at the drain and also limits
the reverse current through the clamp diode during reverse recovery.
Standard recovery glass passivated diodes with low junction
capacitance are recommended as these enable partial energy
recovery from the clamp thereby improving efficiency.
the SECONDARY BYPASS pin voltage at 4.4 V. For such applications,
InnoSwitch3-PD IC has an internal charge pump to regulate the
voltage of the SECONDARY BYPASS pin at 4.4 V.
FORWARD Pin Resistor
A 47 W 5% resistor is recommended to ensure sufficient IC supply
current. A lower resistor value should not be used as it can affect
device operation such as the synchronous rectifier drive timing. In
some cases a higher value should be used if pulse grouping is
observed. However this number should not exceed 150 W.
0V
VSR(TH)
VD
PI-8392-051818
Components for InnoSwitch3-PD
Secondary-Side Circuit
SECONDARY BYPASS Pin – Decoupling Capacitor
A 2.2 mF, 10 V / X7R or X5R / 0805 or larger size multi-layer ceramic
capacitor should be used for decoupling the SECONDARY BYPASS pin
of the InnoSwitch3-PD IC. Since the SECONDARY BYPASS pin voltage
needs to be 4.4 V before the output voltage reaches to the regulation
voltage level, a significantly higher BPS capacitor value could lead to
output voltage overshoot during start-up. The values lower than
1.5 mF may not offer enough capacitance, which can cause
unpredictable operation. The capacitor must be located adjacent to
the IC pins. At least 10 V is recommended voltage rating to give
enough margin from BPS voltage, and 0805 size is necessary to
guarantee the actual value in operation since the capacitance of
ceramic capacitors drops significantly with applied DC voltage
especially with small package SMD such as 0603. 6.3 V / 0603 / X5U
or Z5U type of MLCC is not recommended for this reason. The
ceramic capacitor type designations, such as X7R, X5R from different
manufacturers or different product families do not have the same
voltage coefficients. It is recommended that capacitor data sheets
be reviewed to ensure that the selected capacitor will not have more
than 20% drop in capacitance at 4.4 V. Capacitors with X5R or X7R
dielectrics should be used for best results.
Figure 18. Unacceptable FORWARD Pin Waveform After Handshake With
SR FET Conduction During Flyback Cycle.
0V
VSR(TH)
VD
PI-8393-051818
Figure 19. Acceptable FORWARD Pin Waveform After Handshake With SR FET
Conduction During Flyback Cycle.
When the output voltage of the power supply is 5 V or higher, the
supply current for the secondary-side controller is supplied by the
OUTPUT VOLTAGE (VOUT) pin of the IC as the voltage at this pin is
higher than the SECONDARY BYPASS pin voltage. During start-up
and operating conditions where the output voltage of the power
supply is below 5 V, the secondary-side controller is supplied current
from an internal current source connected to the FORWARD pin. If
the output voltage of the power supply is below 5 V and the load at
the output of the power supply is very light, the operating frequency
can drop considerably and the current supplied to the secondary-side
controller from the FORWARD pin may not be sufficient to maintain
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Rev. E 11/22
InnoSwitch3-PD
There is a slight delay between the commencement of the flyback
cycle and the turn-on of the SR FET. During this time, the body diode
of the SR FET conducts. If an external parallel Schottky diode is
used, this current mostly flows through the Schottky diode. Once the
InnoSwitch3-PD IC detects end of the flyback cycle, voltage across
SR FET RDS(ON) drops below VSR(TH), any remaining portion of the
flyback cycle is completed with the current commutating to the body
diode of the SR FET or the external parallel Schottky diode. A
Schottky diode parallel to the SR FET may be added to provide higher
efficiency. However, the gains are modest; for a 5 V, 2 A design the
external diode adds ~0.1% to full load efficiency at 85 VAC and
~0.2% at 230 VAC.
0V
VSR(TH)
VD
t1
t2
PI-8394-051818
Figure 20. Unacceptable FORWARD Pin Waveform Before Handshake With Body
Diode Conduction During Flyback Cycle.
Note:
If t1 + t2 = 1.5 ms ± 50 ns, the controller may fail to handshake
correctly and trigger a primary bias winding OVP latch-off/AR.
0V
VSR(TH)
VD
PI-8395-051818
Figure 21. Acceptable FORWARD Pin Waveform Before Handshake With Body
Diode Conduction During Flyback Cycle.
SR FET Operation and Selection
Although a simple diode rectifier and filter works for the output, use
of a SR FET enables significant improvement in operating efficiency
often necessary to meet the European CoC and the U.S. DoE energy
efficiency requirements. The secondary-side controller turns on the
SR FET once the flyback cycle begins. The SR FET gate should be
tied directly to the SYNCHRONOUS RECTIFIER DRIVE pin of the
InnoSwitch3-PD IC (with no additional resistors connected to the gate
circuit of the SR FET if a single SR FET is used). The SR FET is
turned off once the Drain voltage of the SR FET drops below 0 V.
A FET with 18 mW RDS(ON) is good for 5 V, 2 A output, and a FET with
8 mW RDS(ON) is suitable for designs rated for 12 V, 3 A output. The SR
FET driver uses the SECONDARY BYPASS pin for its supply rail, and
this voltage is typically 4.4 V. A FET with too high a threshold voltage
is therefore not suitable, and FETs with a low threshold voltage of
1.5 V to 2.5 V are ideal although FETs with a threshold voltage
(absolute maximum) as high as 4 V may be used provided their data
sheets clearly specify RDS(ON) over-temperature range for a gate
voltage of 4.5 V.
The voltage rating of the Schottky diode and the SR FET should be at
least 1.3 to 1.4 times the expected peak inverse voltage (PIV) based
on the turns ratio used for the transformer. 60 V rated FETs and
diodes are suitable for most 5 V designs that use a VOR 9 V.
The interaction between the leakage reactance of the secondary and
the SR FET capacitance (COSS) leads to ringing on SR FET drain
voltage waveform at the instance of voltage reversal at the winding
due to the primary switch turn-on. This ringing can be suppressed
using a RC snubber connected across the SR FET. A snubber resistor
in the range of 10 W to 47 W may be used (a higher resistance value
leads to noticeable drop in efficiency). A capacitance of 1 nF to 2.2 nF
is adequate for most designs. In designs where the SR FET drain
waveform is not as shown in Figure 19 during voltage transitions, and
looks similar to Figure 18 it is recommended that voltage transitions
be made in small increments of 200 mV.
Output Capacitor
Low ESR aluminum electrolytic capacitors are suitable for use with
most high frequency flyback switching power supplies though the use
of aluminum-polymer solid capacitors have gained considerable
popularity due to their compact size, stable temperature characteristics, extremely low ESR and high RMS ripple current rating. These
capacitors enable design of ultra-compact chargers and adapters.
Typically, 200 mF to 300 mF of aluminum-polymer capacitance per
ampere of output current is generally adequate. The other factor
that influences choice of the capacitance is the output ripple. Care
should be taken to ensure that capacitors have a voltage rating
higher than the highest output voltage with sufficient margin (>20%).
Output Overload Protection
The maximum power which can be delivered by the power supply is
obtained by the product of the programmed VKP and the full scale
current limit. For output voltage below the programmed VKP
threshold, the InnoSwitch3-PD IC will limit the output current once
the programmed current limit is reached (if it is less than the full
scale current limit) or voltage across the IS and GND pins exceeds the
ISV(TH) threshold and provides current limited or constant current
operation. The full scale current limit is set by the resistor between
the IS and GND pins. A lower value of current limit can be programmed
over I2C. For any output voltage above the programmed VKP threshold,
InnoSwitch3-PD IC will provide a constant power characteristic. An
increase in load current within the programmed current limit will
result in a drop in output voltage such that the product of output
voltage and current equals the maximum power set by the product of
VKP and set current limit.
Decoupling Capacitor at μVCC Pin
It is recommended that at least a 2.2 mF ceramic capacitor rated for
10 V or higher be placed between the uVCC and GND pins.
Decoupling Capacitor at VO Pin
It is recommended that a 1-2.2 mF ceramic capacitor be placed close
to the VO pin. This capacitor should have a voltage rating higher than
the highest output voltage with suitable margin (>20%).
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InnoSwitch3-PD
Decoupling Capacitor at NTC Pin
It is recommended that at least a 560 pF ceramic capacitor be placed
between the NTC and GND pins. A 10 V or higher rating capacitor
should be used. The NTC pin should be connected to GND pin if a
cost conscious customer does not intend to use the NTC.
Bypass Capacitors
The PRIMARY BYPASS and SECONDARY BYPASS pin capacitor must
be located directly adjacent to the PRIMARY BYPASS-SOURCE and
SECONDARY BYPASS-SECONDARY GROUND pins respectively and
connections to these capacitors should be routed with short traces.
CC1 and CC2 Pin Resistors, Capacitors, and Zener Diodes
These pins are connected to the USB Type-C connector for
communication. There are resistors (R20 and R21, 22 Ω
recommended) between these pins and the USB Type-C connector,
and capacitors (C15, C16, 560pF X5R or X7R with 10 V or higher
rating recommended) from these pins to output GND, which together
form low pass RC filters that improve ESD susceptibility. There are
also Zener diodes (D6 and D7, 24 V recommended) from CC1 and CC2
pins to output GND for improved ESD susceptibility.
Primary Loop Area
The area of the primary loop that connects the input filter capacitor,
transformer primary and IC should be kept as small as possible.
IS to GND Pin Capacitor
It is recommended that 2.2 mF to 4.7 mF ceramic capacitor rated for
10 V or higher to be used between the IS and GND pins of the
InnoSwitch3-PD IC for accurate constant current regulation. A 10 Ω
resistor R12 is also recommended as shown in Figure 15 to provide a
RC filter for current sense.
IS to GND Pin Current Sense Resistor
This sense resistor is chosen such that the required full scale current
produces a 32 mV drop across IS and GND pins. A 1% or lower
tolerance resistor is recommended. This resistor needs to be placed
as close to the InnoSwitch3-PD IC pins as possible for accurate
current measurement and CC regulation. This resistor is typically <
10 mohm for 3 A or higher output currents. As such the copper trace
resistance can contribute to additional effective resistance. Careful
attention should be paid to connections from InnoSwitch3-PD IC to
this resistor to minimize effects of copper trace resistance.
Output Decoupling Capacitor
A ceramic output decoupling capacitor up to 10 mF is required to pass
18 kV ESD air discharge. This capacitor should have a voltage rating
higher than the highest output voltage with sufficient margin (>20%).
Bus Switch
A low RDS(ON) N-channel FET bus switch is recommended to reduce
impact of efficiency at high load currents. The FET need not be a
logic level FET. It should be sufficiently enhanced at a gate threshold
of 4 V.
Bus Discharge
The resistor value for bus discharge is chosen as per the discharge
time requirements for high-voltage to low-voltage transitions. The
resistor value should be sized not to exceed the current rating of VB/D
pin specified in the electrical parameters table. A general purpose
diode is recommended for unidirectional current flow.
Two different bus discharge circuits have been used in some of the
reference designs and other documents. In one circuit, the bus
discharge resistor is connected between the gate of the BUS switch
and the VB/D pin. In another implementation, this resistor is
connected in series with the diode across the BUS switch gate and
source. For all new designs, the circuit configuration shown in this
data sheet and also the design example in Figure 15 is recommended.
Recommendations for Circuit Board Layout
See Figure 22 for a recommended circuit board layout for a switching
power supply using InnoSwitch3-PD IC.
Single-Point Grounding
Use a single-point ground connection from the input filter capacitor to
the area of copper connected to the SOURCE pins.
Primary Clamp Circuit
A clamp is used to limit peak voltage on the DRAIN pin at turn-off.
This can be achieved by using an RCD clamp or a Zener diode
(~200 V) and diode clamp across the primary winding. To reduce
EMI, minimize loop-distance from the clamp components to the
transformer and IC.
Thermal Considerations
The SOURCE pin is internally connected to the IC lead frame and
provides the main path to remove heat from the device. Therefore
the SOURCE pin should be connected to a copper area underneath
the IC to act not only as a single point ground, but also as a heat
sink. As this area is connected to the quiet source node, this area
should be maximized for good heat sinking. Similarly for output
SR FET, maximize the PCB area connected to the pins on the package
through which heat is dissipated from the SR FET.
Sufficient copper area should be provided on the board to keep the
IC temperature safely below the absolute maximum limits. It is
recommended that the copper area provided for the copper plane on
which the SOURCE pin of the IC is soldered is sufficiently large to
keep the IC temperature below 110 °C when operating the power
supply at full rated load and at the lowest rated input AC supply
voltage under highest rated operating temperature. Further de-rating
can be applied depending on any additional specific requirements.
Y Capacitor
The Y capacitor should be placed directly between the primary input
filter capacitor positive terminal and the output positive or return
terminal of the transformer secondary. Such a placement will route
high amplitude common mode surge currents away from the IC.
Note – if an input π (C, L, C) EMI filter is used then the inductor in the
filter should be placed between the negative terminals of the input
filter capacitors.
Output SR FET
For best performance, the area of the loop connecting the secondary
winding, the output SR FET and the output filter capacitor, should be
minimized. The Source pin connection of the SR FET should be
connected to the output capacitor negative terminal and the GND pin
of the InnoSwitch3-PD IC in a short connection to reduce the trace
impedance drop as this is critical for FWD pin sensing wrt IC GND pin
in order to turn OFF the SR FET during Discontinuous mode of
operation. The connection between the Drain of the SR FET and the
FWD pin resistor should also be made short and preferably use a
separate trace to directly connect to SR FET Drain pin. In addition,
sufficient copper area should be provided at the terminals of the
SR FET for heat sinking.
IS-GND Pin, Sense Resistor Traces
It is recommended to have the traces from the current sense resistor
to the IS-GND pins to be in a star connection at the respective two
nodes of the current sense resistor in order to have an accurate CC
set-point. The IS-GND sense traces should be at the innermost of
the solder pads of the current sense resistor to avoid measuring any
drop across the solder pads of the resistor or the load traces coming
in and out of the sense resistor.
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InnoSwitch3-PD
uVCC, CC1 and CC2 Pins
The traces to uVCC, CC1 and CC2 pins should be kept away from any
noisy node or trace. If possible a shield trace should be made in
parallel to the uVCC, CC1 and CC2 traces.
often sufficient to meet the creepage and clearance requirements of
many applicable safety standards. This is less than the InnoSwitch3-PD
IC primary to secondary spacing. To further improve ESD perfo mance,
spark gaps can be added under common mode chokes.
VO Pin, Output Voltage Sense Traces
It is recommended to have the output voltage sense traces directly
from the VO pin to the output capacitor positive terminal, to avoid the
influence of the voltage drop on power trace.
Drain Node
The drain switching node is the dominant noise generator. As such
the components connected to the drain node should be placed close
to the IC and away from sensitive feedback circuits. The clamp
circuit components should be located physically away from the
PRIMARY BYPASS pin and associated circuit trace lengths should be
minimized.
ESD
Sufficient clearance should be maintained (>8 mm) between the
primary-side and secondary-side circuits to enable easy compliance
with any ESD / hi-pot requirements.
The spark gap is best placed directly between output positive rail and
one of the AC inputs. In this configuration a 6.4 mm spark gap is
The loop area of the loop comprising of the input rectifier filter
capacitor, the primary winding and the IC primary-side switch should
be kept as small as possible.
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InnoSwitch3-PD
Layout Example
Maximize source area for
good source heat sinking
FWD pin sensing connection to
SR DRAIN pin directly
Optional Y capacitor connection
to the plus bulk rail on the
primary-side for surge protection
Keep output SR FET and output
filter capacitor loop short
PCB Top Side
6.4 mm spark gap
Keep BPP and BPS
capacitors near the IC
Vo pin sensing connection to
output capacitor + terminal directly
Maximize source area for
good source heat sinking
Keep drain and clamp loop short;
keep drain components away from
PRIMARY BYPASS and UNDER/
OVER INPUT VOLTAGE pin circuitry
Minimize bias rectifier
loop area for good EMI
Keep IS-GND sense
resistor close to IC
Place VOLTAGE pin
sense resistor close
to the VOLTAGE pin
Place forward sense
resistor near the IC
Place ESD capacitors and diodes
close to type C connector
l
PCB Bottom Side
6.4 mm spark gap
Place thermistor to measure
connector temperature underneath
the Type-C connector
Keep Vo/uVCC/IS pin
capacitors close to IC
Figure 22. PCB Layout Recommendation.
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Rev. E 11/22
InnoSwitch3-PD
Recommendations for EMI Reduction
1. Appropriate component placement and small loop areas of the
primary and secondary power circuits help minimize radiated and
conducted EMI. Care should be taken to achieve a compact loop
area and keeping the switching nodes/traces away from the quiet
nodes/traces.
2. A small capacitor in parallel to the clamp diode on the primaryside can help reduced radiated EMI.
3. A resistor in series with the bias winding helps reduce radiated
EMI.
4. Common mode chokes are typically required at the input of the
power supply to sufficiently attenuate common mode noise. The
same can be achieved by using shield windings on the transformer.
Shield windings can also be used in conjunction with common
mode filter inductors at input to achieve improved conducted and
radiated EMI margins.
5. The RC snubber connected across the output SR FET can help
reduce high frequency radiated and conducted EMI.
6. A π filter comprising of differential inductors and capacitors can
be used in the input rectifier circuit to reduce low frequency
differential EMI.
7. A 1 mF or higher ceramic capacitor when connected at the output
of the power supply helps to reduce radiated EMI.
Recommendations for Transformer Design
Transformer design must ensure that the power supply is able to
deliver the rated power at the lowest input voltage. The lowest
voltage on the rectified DC bus of the power supply depends on the
capacitance of the filter capacitor used. At least 2 mF / W is
recommended to keep the DC bus voltage always above 70 V, though
3 mF / W provides sufficient margin. The ripple on the DC bus should
be measured and care should be taken to verify this voltage to
confirm the design calculations for transformer primary-winding
inductance selection.
Switching Frequency (FSW)
It is a unique feature in InnoSwitch3-PD ICs that a designer can set
the switching frequency at full load between 25 kHz to 95 kHz
depending on the design specification. To have lower device
temperature, the switching frequency can be set to around 60 kHz.
To have smaller size transformer, the switching frequency needs to be
set to a value closer to a maximum of 95 kHz. When setting the full
load switching frequency, it is important to consider primary
inductance and peak current tolerances to ensure that average
switching frequency does not exceed 110 kHz which may trigger
auto-restart due to overload protection. The following table provides
a guide for frequency selection based on the device size. This
represents the best compromise between the overall device losses
(conduction and switching losses) based on size of the internal
high-voltage switch and transformer size.
INN3865C / INN3875C
80 kHz
INN3866C / INN3876C
75 kHz
INN3877C
70 kHz
INN3896C
70 kHz
INN3867C / INN3868C
65 kHz
PowiGaN device INN3878C
70 kHz
PowiGaN device INN3879C
65 kHz
PowiGaN device INN3870C
60 kHz
Reflected Output Voltage, VOR (V)
This parameter describes the effect on the primary switch Drain
voltage of the secondary-winding voltage during the diode / SR
conduction which is reflected back to the primary through the turns
ratio of the transformer. To make full use of QR capability and ensure
flattest efficiency over line / load, it is better to set reflected output
voltage (VOR) to maintain KP = 0.8 at minimum input voltage conditions
for universal line input and KP = 1 for high-line input only conditions.
The following should be kept in mind for design optimization:
1. Higher VOR allows increased power delivery at VMIN, which
minimizes the value of the input capacitor and maximizes power
delivery from a given InnoSwitch3-PD device.
2. Higher VOR reduces the voltage stress on the output diodes and
SR FETs.
3. Higher VOR increases leakage inductance that reduces efficiency
of the power supply.
4. Higher VOR increases peak and RMS current on the secondary-side
which may increase secondary-side copper and diode losses.
There are some exceptions to this. For very high output currents
where the VOR should be reduced to get highest efficiency, and higher
output voltages above 15 V, VOR should be higher to maintain a
reasonable PIV across the output synchronous rectifier.
Ripple to Peak Current Ratio, KP
A KP below 1, indicates continuous conduction mode, KP is the ratio of
ripple-current to peak-primary-current (Figure 23).
KP ≡ KRP = IR/IP
A value of KP higher than 1, indicates discontinuous conduction mode.
In this case, KP is the ratio of primary switch off-time to the secondary
diode conduction-time.
KP ≡ KDP = (1 – D) × T / t = VOR × (1 – DMAX) /
(VMIN – VDS) × DMAX
It is recommended that a KP close to 0.9 at the minimum expected DC
bus voltage should be used for most InnoSwitch3-PD designs.
A KP value of 1
T = 1/fS
Primary
D×T
(1-D) × T = t
Secondary
(b) Borderline Discontinuous/Continuous, KP = 1
PI-2578-103114
Figure 24. Discontinuous Mode Current Waveform, KP ≥ 1.
23
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Rev. E 11/22
InnoSwitch3-PD
Transformer Construction for Mitigation of Audible Noise
Although InnoSwitch3-PD features audible noise reduction engine
which prevents operation in the predominant audible range, application of the thixotropic epoxy glue in the transformer air gap is
recommended. This helps to damp any audible noise when the
power supply operates at light load which results in the low frequency
operation.
VOR and the clamp voltage VCLM should be selected such that the peak
drain voltage is lower than 650 V for all normal operating conditions.
This provides sufficient margin to ensure that occasional increase in
voltage during line transients such as line surges will maintain the
peak drain voltage well below 750 V under abnormal transient
operating conditions. This ensures excellent long term reliability and
design margin.
Design Considerations When Using PowiGaN
Devices (INN3878C, INN3879C and INN3870C)
VOR choice will affect the operating efficiency and should be selected
carefully. Table below shows the typical range of VOR for optimal
performance:
For a flyback converter configuration, typical voltage waveform at the
drain pin of the IC is shown in Figure 25.
VOR is the reflected output voltage across the primary winding when
the secondary is conducting. VBUS is the DC voltage connected to one
end of the transformer primary winding.
In addition to VBUS + VOR, the drain also sees a large voltage spike at turn
off that is caused by the energy stored in the leakage inductance of the
primary winding. To keep the drain voltage from exceeding the rated
maximum continuous drain voltage, a clamp circuit is needed across the
primary winding. The forward recovery of the clamp diode will add a
spike at the instant of turn-OFF of the primary switch. VCLM in Figure 25
is the combined clamp voltage including the spike. The peak drain
voltage of the primary switch is the total of VBUS, VOR and VCLM.
Table 3.
Output Voltage
Optimal Range for VOR
5V
45 - 70
12 V
80 - 120
15 V
100 - 135
20 V
120 - 150
24 V
135 - 180
Optimal Range of VOR for different Output Voltage.
750 V = VMAX(NON-REPETITIVE)
Safe Surge Voltage
Region (SSVR)
Typical margin (150 V)
gives de-rating of >80%
650 V = VMAX(CONTINUOUS)
VCLM
VOR
380 VDC
VBUS
Primary Switch Voltage Stress (264 VAC)
PI-8769-071218
Figure 25. Peak Drain Voltage for 264 VAC Input Voltage.
Quick Design Checklist
As with any power supply design, all InnoSwitch3-PD designs should
be verified on the bench to make sure that component limits are not
exceeded under worst-case conditions.
The following minimum set of tests is strongly recommended:
1. Maximum Drain Voltage – Verify that VDS of InnoSwitch3-PD and
SR FET do not exceed 90% of breakdown voltages at highest
input voltage and peak (overload) output power in normal
operating and start-up conditions.
2. Maximum Drain Current – At maximum ambient temperature,
maximum input voltage and peak output (overload) power, verify
drain current waveforms for any signs of transformer saturation
and excessive leading edge current spikes at start-up. Repeat
under steady-state conditions and verify that the leading edge
current spike event is below ILIMIT(MIN) at the end of the tLEB(MIN).
Under all conditions, the maximum drain current should be below
the specified absolute maximum ratings.
Thermal Check – At specified maximum output power, minimum input
voltage and maximum ambient temperature, verify that the temperature specification limits are not exceeded for InnoSwitch3-PD IC,
transformer, output SR FET, and output capacitors. Enough thermal
margin should be allowed for part-to-part variation of the RDS(ON) of
InnoSwitch3-PD IC as specified in the data sheet.
Under low-line, maximum power, a maximum InnoSwitch3-PD IC
SOURCE pin temperature of 110 °C is recommended to allow for
these variations.
24
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Rev. E 11/22
InnoSwitch3-PD
Thermal Resistance Test Conditions for
PowiGaN Devices (INN3878C, INN3879C and
INN3870C)
Thermal resistance value is for primary power device junction to
ambient only.
Testing performed on custom thermal test PCB as shown in Figure 26.
The test board consists of 2 layers of 2 oz. Cu with the InSOP
package mounted to the top surface and connected to a bottom layer
Cu heat sinking area of 550 mm2.
Connection between the two layers was made by 82 vias in a 5 x 17
matrix outside the package mounting area. Vias are spaced at
40 mils, with 12 mil diameter and plated through holes are not filled.
Figure 26. Thermal Resistance Test Conditions for PowiGaN
Devices
(INN3878C,
INN3870C).
Thermal resistance
value
is for INN3879C
primary and
power
device junction to
ambient only.
Firmware Configuration
Testing performed
Name
Function
OVA
Overvoltage Threshold
UVA
Undervoltage Threshold
CVO
Constant Voltage Only
OVL
Overvoltage Fault Response
UVL
Undervoltage Fault Response
CVOL
UVL Timer
CVOL Timer
on custom thermal test PCB as shown in the figure
Cu Switch
with the InSOP
above. The test board consists of 2 layers of 2 oz.Bus
package mounted
to the top surface
and connected
to a bottom
PDO
APDO
Disabled
State layer
(Default)
Cu heatsinking area of 550mm2.
1.1 × V
1
1.1 × V
1
6.2 V
OUTMAX
OUTMAX
Connection between
the two layers was
made by 82 vias in a 5 x 17
3.1 package
V
3.1 area.
V
3.6 V at 40 mils,
Vias are spaced
matrix outside the
mounting
with 12 mil diameter and plated through holes are not filled.
Enabled
Disabled
Disabled
AR
AR
AR
AR
AR
AR
AR
Not Applicable
NR
UVL Fault Timer
8 ms
8 ms
64 ms
CVOL Fault Timer
8 ms
Not Applicable
8 ms
300 mV
0 mV
0 mV
Figure xx. Thermal Resistance Test Conditions for INN3379C and INN3370C
Constant Voltage Mode Fault Response
CDC
Cable Drop Compensation
VKP
Constant Output Power Knee Voltage
24 V
24 V
24 V
CCSC
Output Short-Circuit Fault Detection
AR
AR
AR
ISSC
IS Pin Short Fault Response and Detection Frequency
NR
50 kHz
NR
50 kHz
NR
50 kHz
OTP
Secondary Over-Temperature Fault Hysteresis
40 °C
40 °C
40 °C
Enabled
Enabled
Disabled
40 mA
40 mA
40 mA
Disabled
Disabled
Disabled
VCONN OCP
VCONN OCP Threshold
Type-C OTP
VCONN Over-Current Protection
VCONN Over-Current Protection Threshold
Connector Over-Temperature Fault Protection
NOTES:
1. VOUT(MAX) = MAX {VOUT(MAX)APDO, VOUT(MAX)PDO}
Table 4.
Firmware Configuration Table (Subject to change based on Firmware).
25
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Rev. E 11/22
InnoSwitch3-PD
Absolute Maximum Ratings1,2
DRAIN Pin Voltage: INN3865C−INN3868C ................. -0.3 V to 650 V
INN3875C−INN3877C ................. -0.3 V to 725 V
INN3896C ................................... -0.3 V to 900 V
DRAIN Pin Voltage5: INN3878C−INN3870C................... -0.3 V to 750 V
DRAIN Pin Peak Current: INN3865C........................................ 3.87 A7
INN3875C........................................ 4.11 A7
INN3866C........................................4.88 A7
INN3876C........................................ 5.19 A7
INN3867C........................................5.57 A7
INN3896C........................................ 5.72 A7
INN3877C........................................ 5.92 A7
INN3868C........................................ 6.24 A7
PowiGaN device INN3878C.................6.5 A7
PowiGaN device INN3879C..................10 A7
PowiGaN device INN3870C..................14 A7
BPP/BPS Pin Voltage..........................................................-0.3 to 6 V
BPP/BPS Pin Current ............................................................ 100 mA
CC1, CC2 Pin Voltage...................................................... -0.3 to 28 V
NTC Pin Voltage................................................................-0.3 to 6 V
uVCC Pin Voltage .......................................................-0.3 V to 5.5 V
FWD Pin Voltage ....................................................... -1.5 V to 150 V
SR Pin Voltage ..............................................................-0.3 V to 6 V
V Pin Voltage ............................................................ -0.3 V to 650 V
VOUT Pin Voltage ....................................................... -0.3 V to 27 V
VB/D Pin Voltage ......................................................... -0.3 V to 35 V
IS Pin Voltage ...............................................................-0.3 V to 0.3 V6
Storage Temperature .................................................. -55 to 150 °C
Operating Junction Temperature3.................................. -40 to 150 °C
Ambient Temperature.................................................. -40 to 105 °C
Lead Temperature4................................................................ 260 °C
Notes:
1. All voltages referenced to SOURCE and Secondary GROUND,
TA = 25 °C.
2. Maximum ratings specified may be applied one at a time without
causing permanent damage to the product. Exposure to Absolute
Maximum Ratings conditions for extended periods of time may
affect product reliability.
3. Normally limited by internal circuitry.
4. 1/16” from case for 5 seconds.
5. PowiGaN devices:
Maximum drain voltage (non-repetitive pulse).........-0.3 V to 750 V
Maximum continuous drain voltage.........................-0.3 V to 650 V
6. Absolute maximum voltage for less than 500 ms is 3 V.
7. Please refer to Figures 27, 33, 41 and 42 for maximum allowable
voltage and current combinations.
Thermal Resistance
Thermal Resistance:
INN38x5C to INN38x7C
(qJA)............................. 76 °C/W1, 65 °C/W2
(qJC)..............................................8 °C/W3
PowiGaN devices INN3878C / 3879C / 3870C
(qJA)............................................ 50 °C/W4
Notes:
1. Soldered to 0.36 sq. inch (232 mm2) 2 oz. (610 g/m2) copper clad.
2. Soldered to 1 sq. inch (645 mm2), 2 oz. (610 g/m2) copper clad.
3. The case temperature is measured on the top of the package.
4. Please see Figure 26.
26
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Rev. E 11/22
InnoSwitch3-PD
Symbol
Conditions
SOURCE = 0 V
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Min
Typ
Start-Up Switching
Frequency
fSW
TJ = 25 °C
23
25
kHz
Jitter Modulation
Frequency
fM
TJ = 25 °C
fSW = 100 kHz
0.7
1.15
kHz
Maximum On-Time
tON(MAX)
TJ = 25 °C
Minimum Primary
Feedback Block-Out
Timer
tBLOCK
Parameter
Max
Units
Control Functions
IS1
BPP Supply Current
IS2
VBPP = VBPP + 0.1 V
(Switch not Switching)
TJ = 25 °C
VBPP = VBPP + 0.1 V
(Switch Switching
at 132 kHz)
TJ = 25 °C
14.6
16.9
µs
tOFF(MIN)
µs
INN38x5C –
INN38x7C
145
200
425
INN3878C –
INN3870C
145
266
425
INN3865C
0.65
1.03
INN3866C
0.86
1.21
INN3867C
1.03
1.38
INN3868C
1.20
1.75
INN3875C
0.79
1.10
INN3876C
1.02
1.38
INN3877C
1.20
1.73
INN3896C
0.90
1.35
INN3878C
1.24
1.79
INN3879C
INN3870C
1.95
2.81
mA
mA
ICH1
VBP = 0 V, TJ = 25 °C
-1.75
-1.35
ICH2
VBP = 4 V, TJ = 25 °C
-5.98
-4.65
BPP Pin Voltage
VBPP
TJ = 25 °C
4.65
4.90
BPP Pin Voltage
Hysteresis
VBPP(H)
TJ = 25 °C
BPP Shunt Voltage
VSHUNT
IBPP = 2 mA
5.15
5.36
5.65
V
VBPP(RESET)
TJ = 25 °C
2.8
3.15
3.50
V
INN38x5C –
INN38x7C
23.6
25.8
28.0
INN3878C –
INN3870C
22.9
24.9
27.2
INN38x5C –
INN38x7C
20.0
22.0
24.5
INN3878C –
INN3870C
19.0
21.7
23.6
BPP Pin Charge Current
BPP Power-Up Reset
Threshold Voltage
UV/OV Pin Brown-In
Threshold
IUV+
UV/OV Pin Brown-Out
Threshold
IUV-
Brown-Out Delay Time
tUV-
TJ = 25 °C
TJ = 25 °C
mA
5.15
0.39
35
V
V
µA
µA
ms
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Rev. E 11/22
InnoSwitch3-PD
Parameter
Symbol
Conditions
SOURCE = 0 V
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Min
Typ
Max
INN38x5C –
INN38x7C
106
115
118
INN3878C –
INN3870C
106
112
118
Units
Control Functions (cont.)
UV/OV Pin Line
Overvoltage Threshold
IOV+
UV/OV Pin Line
Overvoltage Hysteresis
IOV(H)
UV/OV Pin Line
Overvoltage Recovery
Threshold
IOV-
TJ = 25 °C
TJ = 25 °C
TJ = 25 °C
8
INN38x5C –
INN38x7C
100
INN3878C –
INN3870C
98
µA
µA
106
µA
104
Line Fault Protection
VOLTAGE Pin Line Overvoltage Deglitch Filter
tOV+
TJ = 25 °C
VOLTAGE Pin
Voltage Rating
VV
TJ = 25 °C
3
µs
650
V
Circuit Protection
Standard Current Limit
(BPP) Capacitor =
0.47 mF
See Note D
Increased Current Limit
(BPP) Capacitor =
4.7 mF
See Note D
Overload Detection
Frequency
di/dt = 213 mA/ms
TJ = 25 °C
INN38x5C
883
950
1017
di/dt = 238 mA/ms
TJ = 25 °C
INN38x6C
1162
1250
1338
INN3877C
1255
1350
1445
INN3867C
1348
1450
1552
INN3868C
1534
1650
1766
INN3878C
1581
1700
1819
di/dt = 425 mA/ms
TJ = 25 °C
INN3879C
1767
1900
2033
di/dt = 525 mA/ms
TJ = 25 °C
INN3870C
2139
2300
2461
di/dt = 213 mA/ms
TJ = 25 °C
INN38x5C
1040
1143
1246
di/dt = 238 mA/ms
TJ = 25 °C
INN38x6C
1297
1425
1553
INN3877C
1410
1550
1689
INN3867C
1494
1642
1790
INN3868C
1683
1850
2017
INN3878C
1714
1884
2054
di/dt = 425 mA/ms
TJ = 25 °C
INN3879C
1919
2109
2299
di/dt = 525 mA/ms
TJ = 25 °C
INN3870C
2325
2555
2785
102
110
di/dt = 300 mA/ms
TJ = 25 °C
ILIMIT
di/dt = 375 mA/ms
TJ = 25 °C
di/dt = 300 mA/ms
TJ = 25 °C
ILIMIT+1
di/dt = 375 mA/ms
TJ = 25 °C
fOVL
TJ = 25 °C
mA
mA
kHz
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Rev. E 11/22
InnoSwitch3-PD
Symbol
Conditions
SOURCE = 0 V
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Min
Typ
BYPASS Pin Fault
Shutdown Threshold
Current
ISD
TJ = 25 °C
5.8
7.4
Auto-Restart On-Time
t AR
TJ = 25 °C
75
82
Auto-Restart Trigger
Skip Time
t AR(SK)
TJ = 25 °C
See Note A
1.3
Auto-Restart Off-Time
t AR(OFF)
TJ = 25 °C
2
t AR(OFF)SH
TJ = 25 °C
See Note A
0.20
Parameter
Max
Units
Circuit Protection
Short Auto-Restart
Off-Time
mA
89
ms
sec
2.11
sec
sec
Output
INN3865C
ID = ILIMIT+1
ON-State Resistance
RDS(ON)
1.95
2.24
TJ = 100 °C
3.02
3.47
INN3875C
ID = ILIMIT+1
TJ = 25 °C
1.95
2.24
TJ = 100 °C
3.02
3.47
INN3866C
ID = ILIMIT+1
TJ = 25 °C
1.30
1.50
TJ = 100 °C
2.02
2.32
INN3876C
ID = ILIMIT+1
TJ = 25 °C
1.34
1.54
TJ = 100 °C
2.08
2.39
INN3867C
ID = ILIMIT+1
TJ = 25 °C
1.02
1.17
TJ = 100 °C
1.58
1.82
TJ = 25 °C
1.20
1.38
TJ = 100 °C
1.86
2.14
TJ = 25 °C
0.91
1.05
INN3877C
ID = ILIMIT+1
INN3868C
ID = ILIMIT+1
INN3896C
ID = ILIMIT+1
INN3878C
ID = ILIMIT+1
INN3879C
ID = ILIMIT+1
INN3870C
ID = ILIMIT+1
OFF-State Drain
Leakage Current
TJ = 25 °C
TJ = 100 °C
1.33
1.53
TJ = 25 °C
2.35
2.80
TJ = 100 °C
3.40
4.20
TJ = 25 °C
0.52
0.68
TJ = 100 °C
0.78
1.02
TJ = 25 °C
0.35
0.44
TJ = 100 °C
0.49
0.62
TJ = 25 °C
0.29
0.39
TJ = 100 °C
0.41
0.54
IDSS1
VBPP = VBPP + 0.1 V
VDS = 80% Peak Drain Voltage
TJ = 125 °C
IDSS2
VBPP = VBPP + 0.1 V
VDS = 325 V
TJ = 25 °C
Drain Supply Voltage
200
15
TSD
See Note A
Thermal Shutdown
Hysteresis
TSD(H)
See Note A
135
mA
mA
50
Thermal Shutdown
W
V
142
70
150
°C
°C
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Rev. E 11/22
InnoSwitch3-PD
Symbol
Conditions
SOURCE = 0 V
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Min
Typ
fSREQ
TJ = 25 °C
118
132
Minimum Off-Time
tOFF(MIN)
TJ = 25 °C
2.7
3.6
BPS Pin Latch
Command Shutdown
Threshold Current
IBPS(SD)
5.2
8.9
5
Parameter
Max
Units
Secondary
Maximum Secondary
Frequency
Start-Up VOUT Pin
Regulation Voltage
kHz
4.6
mA
VOUTREG
TJ = 25 °C
4.85
VOUT(R)
Default = 5 V
TOLVOUT
Tolerance
TJ = 25 °C
Output Voltage
Step Size
∆VOUT
TJ = 25 °C
Report-Back Output
Voltage Tolerance
VOUT(T)
TJ = 25 °C
-3
3
0.6 - 1.0
TJ = 25 °C, See Note C
-5
5
0.2
TJ = 25 °C, See Note C
-15
Output Voltage
Programming Range
ms
5.15
V
3.00
24.00
V
-3
+3
%
10
mV
%
Normalized Output
Current Tolerance
IOUT
Normalized Output
Current Step Size
∆IOUT
TJ = 25 °C
0.78
%
Internal Current Limit
Voltage Threshold
ISV(TH)
TJ = 25 °C
Across External IS to GND Pin Resistor
See Note E
32
mV
TOLφCD
100 mV ≤ CDC ≤ 400 mV
TJ = 25 °C
-35
+35
mV
Output Overvoltage
Programming Range
VOVA
Default = 6.2 V
6.2
25
V
Output Overvoltage
Tolerance
TOLOVA
TJ = 25 °C
-3
3
%
Output Undervoltage
Programming Range
VUVA
Default = 3.6 V
3
24
V
Output Undervoltage
Tolerance
TOLUVA
TJ = 25 °C
-3
3
%
VB/D Drive Voltage
V VB/D
With Respect to VOUT Pin
4
10
V
VB/D Turn-On Time
tR(VB/D)
TJ = 25 °C
CLOAD = 10 nF
4
10
ms
VB/D Turn-Off Time
tF(VB/D)
TJ = 25 °C
CLOAD = 10 nF
4
10
ms
VB/D Pin Load
Discharge Internal
On-State Resistance
RB/D(ON)
See Note H
32
CDC Tolerance
%
15
W
30
www.power.com
Rev. E 11/22
InnoSwitch3-PD
Parameter
Symbol
Conditions
SOURCE = 0 V
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Min
Typ
Max
Units
Secondary (cont.)
VB/D Pin Load
Discharge Internal
Off-State Resistance
RB/D(OFF)
VOUT Pin
Bleeder Current
IVOBLD
VOUT = 5 V
TJ = 0 ‒ 125 °C
uVCC Supply Voltage
uVCC
VOUT = 5 V
uVCC Reset Voltage
Threshold
uVCCRST
See Note B
BPS Pin Voltage
BPS Pin Current
80
ISNL
BPS Pin Undervoltage
Threshold
VBPS(UVLO)TH
BPS Pin Undervoltage
Hysteresis
VBPS(UVLO)TH
Soft Start Frequency
Ramp Time
tSS(RAMP)
FORWARD Pin
Breakdown Voltage
BVFWD
270
3.42
4.2
VBPS
kW
mA
3.60
3.78
V
2.8
3.0
V
4.4
V
TJ = 25 °C
VBUS Switch Open
0.7
0.9
TJ = 25 °C
VBUS Switch Closed
1.03
1.3
3.8
4.0
mA
3.6
TJ = 25 °C
V
0.65
V
11.8
ms
150
V
Synchronous Rectifier @ TJ = 25 °C
SR Pin Drive Voltage
SR Pin Voltage
Threshold
4.2
VSR
4.4
-5.0
VSR(TH)
V
0
mV
Rise Time
tR(SR)
TJ = 25 °C
CLOAD = 2nF
See Note B
10-90%
50
ns
Fall Time
tF(SR)
TJ = 25 °C
CLOAD = 2nF
See Note B
90-10%
30
ns
Output Pull-Up
Resistance
RPU
TJ = 25 °C
VBPS + 0.1 V
ISR = 30 mA
10
13
W
Output Pull-Down
Resistance
RPD
TJ = 25 °C
VBPS + 0.2 V
ISR = 30 mA
5.0
5.8
W
31
www.power.com
Rev. E 11/22
InnoSwitch3-PD
Parameter
Symbol
Conditions
SOURCE = 0 V
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Min
Typ
Max
Units
PD Controller - Type C Configuration Channels CC1 and CC2
Source 0.5 A Current
Advertisement
IRP(0P5A)
64
80
96
mA
Source 1.5 A Current
Advertisement
IRP(1P5A)
166
180
194
mA
Source 3.0 A Current
Advertisement
IRP(3P0A)
304
330
356
mA
BMC Receiver
RX Input Detection
Threshold
VRXTH
Receiver Input
Impedance
RBMCRX
See Note F
550
mV
1.3
MW
See Note G
40
mA
VCONN = VCC, Current = 10 mA
6.5
W
45
mA
VCONN Switch
Over Current Detection
Threshold
Total Resistance (VCONN
Switch + Protection
Switch)
IVCONN_OCP_
CURRENT
RVCONN(CC)
NTC and Internal Temperature Sense
NTC Pin Current Source
ISOURCE(NTC)
ADC Accuracy On NTC
TOL ADC
Input Voltage Range
VADC_IN
TJ = 25 °C
0.25
2
%
2.20
V
NOTES:
A.
B.
C.
D.
This parameter is derived from characterization.
This parameter is guaranteed by design.
Use 1% tolerance resistor.
To ensure correct current limit it is recommended that nominal 0.47 mF / 4.7 mF capacitors are used. In addition, the BPP capacitor value
tolerance should be equal or better than indicated below across the ambient temperature range of the target application. The minimum and
maximum capacitor values are guaranteed by characterization.
Nominal BPP Pin
Capacitor Value
BPP Capacitor Value Tolerance
Minimum
Maximum
0.47 mF
-60%
+100%
4.7 mF
-50%
N/A
Recommended to use at least 10 V / 0805 / X7R SMD MLCC.
E. This parameter should be used only for calculation of typical value of current sense resistor. Firmware programs the register to regulate
output current. The tolerance is specified in the Normalized Output Current parameter (IOUT).
F. This parameter is indirectly tested.
G. Only at 5 V output, VCONN can supply up to 40 mA current for 0.5 seconds.
H. The current into VB/D pin during the discharge should be limited to 600
V
Ratings for UL1577
Primary-Side
Current Rating
Primary-Side
Power Rating
Secondary-Side
Power Rating
Package Characteristics
Transient Isolation
Voltage
Comparative Tracking
Index (CTI)
*For INN3878C rating is 1.0 A.
39
www.power.com
Rev. E 11/22
InnoSwitch3-PD
Parameter
Symbol
Conditions
Rating
Units
Package Characteristics
Clearance
CLR
11.4
mm (min)
Creepage
CPG
11.4
mm (min)
Distance Through
Insulation
DTI
0.4
mm
Comparative Tracking
Index
CTI
>600
V
Isolation Resistance,
Input to Output
R IO
Isolation Capacitance,
Input to Output
CIO
VIO = 500 V, TJ = 25 °C (See Note 1)
1012
VIO = 500 V, 100 °C ≤ TJ ≤ 125 °C (See Note 1)
1011
(See Note 1)
1
INN386xC
512
INN387xC
530
INN389xC
636
INN386xC
650
INN387xC
725
INN389xC
900
Test Voltage = VIOTM, t = 60 s
(Qualification)
6.6
t=1s
(100% Production)
8
Surge Test 1.2/50 usec
Table 2 IEC 60747-17
10.4
W (min)
pF
Package Insulation Characteristics (See Note 2)
Maximum RMS Working
Isolation Voltage
Maximum Repetitive
Peak Isolation Voltage
VIORM(RMS)
VIORM(PK)
Maximum Transient
Peak Isolation Voltage
VIOTM
Maximum Surge
Isolation Voltage
VIOSM
Method A, After Environmental Tests
Subgroup 1,
VPD = 1.6 × VIORM, t = 10 s (qualification)
Partial Discharge < 5 pC
Input to Output Test
Peak Voltage
VPD
Method A, After Input / Output Safety Test
Subgroup 2/3,
VPD = 1.2 × VIORM, t = 10 s, (qualification)
Partial Discharge < 5 pC
Method B1, 100% Production Test,
VPD = 1.875 × VIORM, t = 1 s
Partial Discharge < 5 pC
Insulation Resistance
Climatic Category
RS
VIO = 500 V at TS
VRMS (max)
VPK (max)
kVPK (max)
INN386xC
1040
INN387xC
1160
INN389xC
1440
INN386xC
780
INN387xC
870
INN389xC
1080
INN386xC
1220
INN387xC
1360
INN389xC
1688
>109
kVPK (max)
VPEAK(min)
W
40/125/21
40
www.power.com
Rev. E 11/22
InnoSwitch3-PD
Parameter
Conditions
Specifications
Material Group
I
Rated Mains RMS voltage ≤ 150 V
I - IV
Rated Mains RMS voltage ≤ 300 V
I - IV
Rated Mains RMS voltage ≤ 600V
I - IV
Rated Mains RMS voltage ≤ 1000 V
I - III
IEC 60664-1 Rating Table
Basic Isolation Group
Insulation
Classification
Note 1: All pins on each side of the barrier tied together creating a two-terminal device
Note 2: VDE 0884-11 only applies to devices with following H-codes: -H608, -H609, -H610, -H611 and –H612
Note 3: VDE 0884-11 certification is pending for INN369x devices.
41
www.power.com
Rev. E 11/22
InnoSwitch3-PD
Feature Code Table
Summary Features
H801
ILIM Selectable
Yes
Over-Temperature Protection
Hysteretic
Line OV/UV
Enabled
Line UV Timer (35 ms or 400 ms)
35 ms
Primary Bypass Output Overvoltage Protection
Latch-Off
Part Ordering Table – Standard Offering
Part
Number
Feature
Code
POUT
(W)
INN3865C/
INN3875C
H801
20
5V/3A
9 V / 2.22 A
12 V / 1.67 A
3.3-5.9 V / 3 A
3.3-11 V / 2.2 A
INN3866C/
INN3876C
H801
30
5V/3A
9V/3A
12 V / 2.5 A
15 V / 2 A
20 V / 1.5 A
3.3-11 V / 3 A
3.3-16 V /
2A
INN3867C/
INN3877C
H801
33
5V/3A
9V/3A
12 V / 2.75 A
15 V / 2.2 A
20 V / 1.65 A
3.3-11 V / 3 A
3.3-16 V /
2.05 A
INN3878C/
INN3868C
H801
45
5V/3A
9V/3A
12 V / 3 A
15 V / 3 A
20 V / 2.25 A
3.3-16 V / 3 A
3.3-21 V /
2.25 A
INN3879C
H801
60
5V/3A
9V/3A
15 V / 3 A
20 V / 3 A
3.3-21 V / 3 A
INN3870C
H801
65
5V/3A
9V/3A
12 V / 3 A
15 V / 3 A
20 V / 3.25 A
PDOs & APDOs
3.3-21 V / 3 A
Parts listed above meet standard USB Type-C and PD3.0 requirements.
Please contact Power Integrations Factory or local Sales Office for availability of additional part numbers.
MSL Table
Part Number
MSL Rating
INN38xxC
3
ESD and Latch-Up Table
Test
Conditions
Results
Latch-up at 125 °C
JESD78D
Charge Device Model ESD
ANSI/ESDA/JEDEC JS-002-2014
> ±1 kV on all pins
Human Body Model ESD
ANSI/ESDA/JEDEC JS-002-2014
> ±2 kV on all pins, except on VB/D pin
> ±1 kV on VB/D pin
> ±100 mA or > 1.5 × VMAX on all pins
Part Ordering Information
• InnoSwitch3 Product Family
• PD Series Number
• Package Identifier
C
InSOP-24D
• Feature Code – Firmware and product Configuration
• Tape & Reel and Other Options
INN 3865 C - H801 - TL
TL
Tape & Reel, 2 k pcs per reel.
42
www.power.com
Rev. E 11/22
InnoSwitch3-PD
Notes
43
www.power.com
Rev. E 11/22
Revision Notes
Date
C
Code A release.
09/21
D
Added par numbers: INN3875/3876/3877/3868/3896.
12/21
E
Updated UL1577 isolation voltage on page 1. Updated Package and Insulation Characteristics Parameter Table and IEC
60664-1 Rating Table Notes 2 and 3.
11/22
For the latest updates, visit our website: www.power.com
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations
does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY
HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.
Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one
or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of
Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set
forth at www.power.com/ip.htm.
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POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:
1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose
failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or
death to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or effectiveness.
Power Integrations, the Power Integrations logo, CAPZero, ChiPhy, CHY, DPA-Switch, EcoSmart, E-Shield, eSIP, eSOP, HiperPLC, HiperPFS,
HiperTFS, InnoSwitch, Innovation in Power Conversion, InSOP, LinkSwitch, LinkZero, LYTSwitch, SENZero, TinySwitch, TOPSwitch, PI, PI Expert,
PowiGaN, SCALE, SCALE-1, SCALE-2, SCALE-3 and SCALE-iDriver, are trademarks of Power Integrations, Inc. Other trademarks are property of
their respective companies. ©2021, Power Integrations, Inc.
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