HiperLCS Family
Integrated LLC Controller, High-Voltage
Power MOSFETs and Drivers
Product Highlights
B+
Features
• LLC half-bridge power stage incorporating controller, high and
•
•
•
•
•
•
•
•
•
low-side gate drives, and high-voltage power MOSFETs
• Eliminates up to 30 external components
High maximum operating frequency of 1 MHz
• Nominal steady-state operation up to 500 kHz
• Dramatically reduces magnetics size and allows use of SMD
ceramic output capacitors
Precise duty symmetry balances output rectifier current, improving
efficiency
• 50% ±0.3% typical at 300 kHz
Comprehensive fault handling and current limiting
• Programmable brown-in/out thresholds and hysteresis
• Undervoltage (UV) and overvoltage (OV) protection
• Programmable over-current protection (OCP)
• Short-circuit protection (SCP)
• Over-temperature protection (OTP)
Programmable dead-time for optimized design
Programmable burst mode maintains regulation at no-load and
improves light load efficiency
Programmable soft-start time and delay before soft-start
Accurate programmable minimum and maximum frequency limits
Single package designed for high-power and high-frequency
• Reduces assembly cost and reduces PCB layout loop areas
• Simple single clip attachment to heat sink
• Staggered pin arrangement for simple PC board routing and
high-voltage creepage requirements
Paired with HiperPFS PFC product gives complete, high efficiency,
low part count PSU solutions
Applications
•
•
•
•
•
D
VCCH
High-efficiency power supplies (80 PLUS Silver, Gold and Platinum)
LCD TV power supplies
LED street and area lighting
Printer power supplies
Audio amplifier
CONTROL
Standby
Supply
VCC
+V
HB
HV DC
Input
OV/UV
VREF
RTN
RFMAX
DT/BF
IS
HiperLCS
RBURST
FB
B-
G
S1/S2
LLC Feedback Circuit
PI-6159-060211
Figure 1. Typical Application Circuit – LCD TV and PC Main Power Supply.
Output Power Table
Product
Maximum Practical Power1
LCS700HG/LG
110 W
LCS701HG/LG
170 W
LCS702HG/LG
220 W
LCS703HG/LG
275 W
LCS705HG/LG
350 W
LCS708HG/LG
440 W
Table 1. Output Power Table.
Notes:
1. Maximum practical power is the power the part can deliver when properly
mounted to a heat sink and a maximum heat sink temperature of 90 °C.
Description
The HiperLCS™ is an integrated LLC power stage incorporating a
multi-function controller, high-side and low-side gate drivers, plus two
power MOSFETs in a half-bridge configuration. Figure 1 shows a
simplified schematic of a HiperLCS based power stage where the LLC
resonant inductor is integrated into the transformer.
The variable frequency controller provides high-efficiency by
switching the power MOSFETs at zero voltage (ZVS), eliminating
switching losses.
www.power.com
May 2017
This Product is Covered by Patents and/or Pending Patent Applications.
LCS700-708
VCC
VREF
DRAIN (D)
3.4 V
REGULATOR
UVLO
VCCH
LLC_ON
+
OV/UV
VSDH/
VSDL
UVLO
SOFT-START DELAY
131,072 LLC
CLOCK CYCLES
DEBOUNCE
3 LLC CLOCK
CYCLES
+
VOVH/
VOVL
OVERTEMPERATURE
PROTECTION
+
IS
HB
LEVEL
SHIFT
VISF
7 CONSECUTIVE
LLC CLOCK
CYCLES
+
VISS
LLC_CLK
VREF
FEEDBACK (FB)
LLC
CLOCK
DT/BF
+
DT/BF
RESISTOR
SENSOR
DEAD-TIME
GENERATOR
OUTPUT
CONTROL
LOGIC
DEBOUNCE
3 LLC CLOCK
CYCLES
Bursting
Thresholds
Control
GROUND (G)
PI-5755-060111
SOURCE (S1/S2)
Figure 2. Block Diagram.
2
Rev. G 05/17
www.power.com
LCS700-708
Pin Functional Description
VCC Pin
IC power pin. In a typical application, VCC is connected to the 12 V
system standby supply via a 5 W resistor. This resistor helps provide
filtering and improves noise immunity.
H Package (eSIP-16J)
(Front View)
CURRENT-SENSE (IS) Pin
The CURRENT-SENSE pin is used for sensing transformer primary
current, to detect overload and fault conditions, through a current
sense resistor or a capacitive divider plus sense resistor circuit. It
resembles a reverse diode to ground, and does not require a rectifier
circuit for preventing negative pulses from reaching the pin, provided
the reverse current is limited to 0.9 V. Both will invoke a 131,072 cycle
restart cycle. VCC can also be pulled down to shut the device off, but
when it is pulled up, the FEEDBACK pin is pulled up to the VREF pin to
discharge the soft-start capacitor for only 1024 fMAX clock cycles. If
this scheme is used, the designer must ensure that the time the VCC
is pulled down, plus 1024 cycles, is sufficient to discharge the
soft-start capacitor, or if not, that the resulting lower starting
frequency is high enough so as not to cause excessive primary
currents that may cause the over-current protection to trip.
Current Sense
The IS pin senses the primary current. It resembles a reverse diode
to the GROUND pin. It is tolerant of negative voltages provided the
negative current is limited to 220 Ω. Thus
it can accept an AC waveform and does not need a rectifier or peak
detector circuit. If the IS pin senses a nominal positive peak voltage
of 0.5 V for 7 consecutive cycles, an auto-restart will be invoked. The
IS pin also has a second, higher threshold at nominally 0.9 V, which
will invoke an auto-restart with a single pulse. The minimum pulse
width requirement for detection of both voltage thresholds is
nominally 30 ns. i.e. the thresholds have to be exceeded for >30 ns
for proper detection.
Over-Temperature Shutdown
The HiperLCS has latching OTP. VCCH must be cycled to resume
operation once the unit drops down below the OTP threshold.
VCCH Pin UVLO
The VCCH pin is the supply pin for the high-side driver. It also
has a UVLO function similar to the VCC pin, with a threshold
lower than the VCC pin. This is to allow for a VCCH voltage that is
slightly lower than VCC because the VCCH pin is fed by a bootstrap
diode and series current-limiting resistor from the
VCC supply.
5
www.power.com
Rev. G 05/15
LCS700-708
Basic Layout Guidelines
The HiperLCS is a high-frequency power device and requires careful
attention to circuit board layout in order to achieve maximum
performance.
The bypass capacitors need to be positioned and laid out carefully to
minimize trace lengths to the pins they serve. SMD components are
recommended for minimum component and trace stray inductance.
Table 2 describes the recommended bypass capacitor values for pins
that require filtering/bypassing. The table lists the pins in the order
of most to least sensitive. The bypass capacitor of the pin at the top
of the list being the most sensitive, receives higher priority in bypass
capacitor positioning to minimize trace lengths, than the bypass
capacitor of the pin below it. Noise entering the two most sensitive
pins on the list, namely the FEEDBACK and DT/BF pins, will cause
duty cycle, and dead-time imbalance, respectively.
Figure 5 and Figure 6 show two alternate schemes for routing ground
traces for optimum performance. Figure 5 shows a layout footprint
for the LCS with oval pads. These allow a trace to be passed between
pins 3 and 5, directly connecting the ground systems for the bypass
capacitors located on each side of the IC.
Figure 6 shows an LCS layout footprint with round pads that do not
allow traces to be routed between them due to insufficient space. In
this case, a jumper (JP1, a 1206 size 0 W resistor) is used to connect
the ground systems together and allow a connection for pin 3 to be
routed under JP1 to the optocoupler.
Transformer T1 is a source of both high di/dt signals and dv/dt noise.
The first can couple magnetically to sensitive circuitry, while the
second can inject noise via electrostatic coupling. Electrostatic noise
coupling can be reduced by grounding the transformer core, but it is
not economically feasible to reduce the stray magnetic field around
the transformer without drastically reducing its efficiency. Sensitive
traces and components (such as the optocoupler) should be located
away from the transformer to avoid noise pickup.
Pin
Returned to Pin
Recommended Value
Notes
FEEDBACK (FB)
GROUND
4.7 nF (at 250 kHz)
Increase value proportionally for lower nominal frequency
(e.g. 10 nF at 100 kHz). Forms a pole with FEEDBACK pin
input impedance which is part of feedback loop characteristic. Must not introduce excessive phase shift at expected
gain crossover frequency. Noise entering FEEDBACK pin will
cause duty cycle imbalance.
DEAD-TIME/BURST
FREQUENCY (DT/BF)
GROUND
4.7 nF
Time constant of this capacitor and the source impedance
of the resistors connected to DT/BF pin must be 300 kHz start to lose significant
efficiency due to increased eddy current losses in the copper, and
due to the fact that a more significant percentage of time is spent on
the primary slew time (ZVS transition time) which erodes the
percentage of time that power is transferred to the secondary.
Resonant Tank and Transformer Design
Please refer to the Application Note AN-55 for guidance on using the
PIXls HiperLCS spreadsheet which assists in the entire design
process.
Primary Inductance
The optimal powertrain design for the HiperLCS uses a primary inductance that results in minimal loss of ZVS at any steady-state condition. Some loss of ZVS during non-steady-state conditions is acceptable. Reducing primary inductance produces higher magnetizing
current which increases the range of ZVS operation, but the increased
magnetizing current increases losses and reduces efficiency.
The calculation of the primary inductance to be used for a first-pass
design is based on device size, rated load, minimum input voltage,
and desired operating frequency. It is provided in the PIXls spread-
sheet. LPRI is the primary inductance of an integrated transformer
(high leakage inductance), or in the case of the use of an external
series inductance, the sum of this inductance and the transformer
primary inductance.
Leakage Inductance
The parameter KRATIO is a function of leakage inductance:
K RATIO = L PRI - 1
L RES
The recommended KRATIO is from 2.5 - 7. This determines the
acceptable range of leakage inductance.
LRES is the leakage inductance in an integrated transformer; if a
separate series inductor is used, it is the sum of this inductance and
the leakage inductance of the transformer.
A low KRATIO (high leakage inductance) may not be capable of
regulation at the minimum input voltage, and may show increased
transformer copper losses due to the leakage flux. A high KRATIO (low
leakage inductance) will have high peak and RMS currents at low-line,
and require a lower primary inductance to achieve ZVS operation over
a suitably wide range, which increases the resonant circulating
current, reducing efficiency.
The core and bobbin designs available to the designer may limit the
adjustability of leakage inductance. Fortunately, excellent performance can be achieved over a relatively wide range of leakage
inductance values.
The KRATIO directly affects the frequency range that the LLC needs to
operate in order to maintain regulation over the input voltage range.
Increasing KRATIO increases this frequency range, lowering fMIN.
A low fMIN is only a potential problem for low frequency designs which
typically run at higher nominal BAC. This may allow the core to reach
saturation when operating at fMIN. Operating at fMIN occurs when the
input voltage is at a minimal (input brown-out).
For a design with a separate resonant inductor, running the inductance on the low side of the range (KRATIO = 7), minimizes the size and
cost of the inductor.
Adjusting Leakage Inductance
Sectioned bobbins (separated primary and secondary) are commonly
used for LLC converters. Increasing or decreasing both primary and
secondary turns (while maintaining turns ratio) will change the
leakage inductance proportionally to the square of primary turns.
If the leakage inductance is too high, one possible solution is to use a
3-section bobbin, where the secondary is in the middle section, and
the primary winding is split into 2 halves connected in series.
Lastly, if the leakage inductance is too low an external inductor may
be added.
11
www.power.com
Rev. G 05/15
LCS700-708
Resonant Frequency
The series resonant frequency is a function of LRES and CRES, the
resonant capacitor. For any given value of LRES, the value of CRES can
be adjusted for the desired series resonant frequency fRES. For best
efficiency the resonant frequency is set close to the target operating
frequency at nominal input voltage.
Operating Frequency and Frequency Ratio
The operating to resonant frequency ratio fRATIO is defined as:
fRATIO =
fSW
fRES
fRATIO = 1 signifies the converter is operating at the series resonant
frequency.
The main determinant of fRATIO is the transformer turns ratio.
Increasing primary turns lowers fRATIO for a given input and output
voltage.
The recommended fRATIO at nominal input voltage is 0.92 – 0.97.
Operating at resonance often yields the highest efficiency for the
resonant powertrain if output rectifier selection is ignored. However,
operating slightly below resonance (which puts the rectifiers in
discontinuous conduction mode), allows the use of lower voltage
diodes or synchronous MOSFETs, which have lower losses, increasing
overall efficiency. This is because at high-line, when the converter
needs to operate above resonance, the rectifiers operate less deeply
in continuous mode, reducing the magnitude of their current
commutation, reducing their stray inductance voltage spikes. (The
stray inductance is comprised of the leakage inductance between
secondary phases and the stray inductance in the connections to the
rectifiers and output capacitors).
Conversely, operating at a very low fRATIO (fSTOP.
12.0
250
1000
Figure 16. FEEDBACK Pin and DT/BF Pin Current vs. Frequency.
13.0
BT1
BT2
BT3
450
fSTART (kHz)
350
RFMAX (kΩ)
500
PI-6150-052011
450
PI-6457-051911
LCS700-708
500
FEEDBACK Pin
The FEEDBACK pin is the voltage regulation FEEDBACK pin. It has a
nominal Thevenin equivalent circuit of 0.65 V and 2.5 kΩ. In normal
operation, it sinks current. During the off-period of auto-restart, and
during the clocked delay before start-up, it pulls up internally to VREF in
order to discharge the soft-start capacitor. The current entering the pin
determines switching frequency. Higher current yields higher
frequency and thus reduces LLC output voltage. In a typical application
an optocoupler connected to the VREF pin pulls up on the FEEDBACK
pin, via a resistor network. The optocoupler is configured to source
increasing FEEDBACK pin current, as the output rises. The resistor
network between the optocoupler, FEEDBACK pin, and VREF pin,
determine the minimum and maximum FEEDBACK pin current (and
thus the minimum and maximum operating frequency), that the
optocoupler can command as it goes from cutoff to saturation. This
network also contains the soft-start timing capacitor, CSTART (Figure 19).
The minimum frequency as set by this network must be lower than the
frequency required by the powertrain at minimum input voltage.
In Figure 19 this is determined by the sum of RFMIN and RSTART. The
FEEDBACK pin current is determined by these two resistors when the
optocoupler is cut off. CSTART can be ignored during normal operation.
14
Rev. G 05/17
www.power.com
Bursting Duty ≈ 50%
10 μs / div
3.4 V
VREF
CSTART
RFMIN
RSTART
D1
FB
CFB
4.7 nF
U1B
IPRI
VHB
PI-6463-060711
LCS700-708
850 ns / div
ROPTO
RLOAD
GND
~850 kHz
Figure 19. Feedback Network Shown with Additional Load Resistor.
Figure 20. Bursting at fMAX Causes High Internal Dissipation Due to Loss of
ZVS and Should be Avoided.
300
The FEEDBACK pin current at start-up is determined by the value of
RSTART because the voltage on CSTART will be zero. For minimum start-up
peak currents, this current should match or slightly exceed the DT/BF
pin current so that start-up switching frequency begins at fMAX. The
resulting value of RSTART will be approximately 10% lower than the value
of the pull-up resistor on the DT/BF pin. The frequency will slide down
as CSTART charges. If RSTART is smaller than that which provides start-up
at fMAX, it will create an additional delay before start-up switching.
Please see the PIXls HiperLCS spreadsheet.
100
Capacitor CSTART should be sized at the minimum possible value that
exhibits a 7 consecutive-cycle peak current at start-up that is just
below the peak current measured at brown-out and full load. A larger
value will slow down start-up and will make it more likely that fSTOP is
not reached. This can prevent exiting start-up mode when the
HiperLCS is powered up at high-line and minimum load, and may
subsequently cause the HiperLCS to burst at fMAX instead of between
fSTART and fSTOP.
RFB (kΩ)
Do not confuse RSTART, which determines start-up frequency, and fSTART,
which is the burst mode start (lower) threshold frequency.
Resistor RLOAD provides a load on the optocoupler, and speeds up the
large signal transient response during burst mode. The recommended
value is ~4.7 kΩ. Diode D1 prevents RLOAD from loading RFMIN when the
optocoupler is cut off. Diode D1 can be omitted and a combination of
resistor values found to achieve the desired fMIN but the resulting
tolerances will be poor. Resistor ROPTO will improve the ESD and surge
immunity of the PSU. It also improves burst mode output ripple
voltage. Its maximum value must be such that the FEEDBACK pin
current is equal to the DT/BF pin current when the optocoupler is in
saturation and the FEEDBACK pin is at 2.0 V (please see PIXls HiperLCS
spreadsheet). This is to ensure that if the HiperLCS does not exit
start-up mode, because the feedback loop did not allow the switching
frequency to drop below fSTOP, then it can regulate at light load by
bursting at fMAX. Note however bursting at fMAX can lead to high internal
dissipation due to loss of ZVS and should be avoided. See Figure 20.
Severe Loss of ZVS
PI-6151-060911
PI-6118-051711
50
20
10
4
20
50
100
200
500
1000
Frequency (kHz)
Figure 21. VREF to FB External Resistance vs. Frequency.
In order to calculate RFMIN and RSTART, use the following equation which
describes nominal resistance from FEEDBACK pin to VREF pin, vs.
frequency:
R FB =
3574
f ^0.6041 + 0.1193 # LOG^ f hh
Where RFB is in kΩ and f is in kHz.
To calculate the minimum RSTART, which produces start-up at fMAX, use
the above equation with f = fMAX from the equation relating dead-time
and fMAX.
To set fMIN, use the above equation with f = fMIN × 0.93. Where 0.93 is
to ensure that, despite the worst case frequency tolerance of -7%, the
frequency can go below fMIN, guaranteeing regulation at VBROWNOUT.
Using the resulting calculated value for RFB, calculate RFMIN:
R FMIN = R FB - R START
The sum of RFMIN and RSTART determines fMIN.
15
www.power.com
Rev. G 05/15
LCS700-708
At start-up, this state remains for 1024 clock cycles at frequency fMAX.
During the off-state of auto-restart, or if the OV/UV or IS pin is
triggered while the VCC remains above its UVLO threshold, this state
remains for 131,072 clock cycles.
After 1024 or 131,072 cycles (as the case may be), the HiperLCS turns
off the internal pull-up transistor, the soft-start capacitor begins to
charge, the output MOSFETs switch at fMAX, current in the FEEDBACK
pin diminishes, the frequency begins to drop, and the PSU output rises.
For example, for fMAX = 800 kHz, the start-up delay after VCC power-up
is 1.3 ms. If IS, or the OV/UV pin are tripped, auto-restart is invoked,
with a restart delay of 164 ms.
The FEEDBACK pin has a current limit equal to the current flowing into
the DT/BF pin. This limits the maximum current that charges the
soft-start capacitor at start-up. If RSTART is smaller than that which
allows the FEEDBACK pin current to match the DT/BF pin current at
start-up, an additional delay is introduced. CSTART will charge at the
current limit, and switching will only commence when the FEEDBACK
pin voltage drops below 2.0 V. Thus the designer can add an additional
start-up delay if desired.
As the soft-start capacitor continues to charge, the current through
RSTART and thus the FEEDBACK pin decreases, reducing switching
frequency. The output voltage climbs; and when the feedback loop
closes, the optocoupler conducts and starts controlling the switching
frequency thus the output voltage.
Remote-Off
Remote-off can be invoked by pulling down the OV/UV pin to ground,
or by pulling up the IS pin to >0.9 V. Both will invoke a 131,072 cycle
restart cycle. VCC can also be pulled down to shut the device off, but
when it is pulled up, the FEEDBACK pin is pulled up to the VREF pin to
discharge the soft-start capacitor for only 1024 fMAX clock cycles. If this
scheme is used, the designer must ensure that the time the VCC is
pulled down, plus 1024 cycles, is sufficient to discharge the soft-start
capacitor, or if not, that the resulting lower starting frequency is high
enough so as not to cause excessive primary currents that may cause
the over-current protection to trip.
IS Pin
The IS pin has 2 thresholds: nominally 0.5 V and 0.9 V. The IS pin
can tolerate small negative voltages and currents, and thus does not
A
4
B
80
70
60
2
Primary Current
0
50
-2
40
-4
30
-6
Volts (V)
Start-Up and Auto-Restart
At start-up and during the off-state of the auto-restart cycle, the
FEEDBACK pin is internally pulled up to the VREF pin. This keeps the
output MOSFETs off and discharges the soft-start capacitor, in
preparation for soft-start.
PI-6471-052411
6
Amps (A)
It should be noted that the 4.7 nF decoupling capacitor, CFB (see Figure
19), in conjunction with the 2.5 kΩ input resistance presented by the
FEEDBACK pin, form a pole in the LLC transfer function. This can add
significant phase lag to the feedback loop. A typical value for a 250 kHz
design with a 3 kHz crossover frequency is 4.7 nF. To prevent loop
instability, the value of the 4.7 nF capacitor should not be increased
arbitrarily. At the other extreme, insufficient FEEDBACK pin bypass
capacitance or poor layout may cause duty cycle asymmetry.
20
Output Voltage
10
-8
0
-10
0
0.5
1
1.5
2
2.5
3
3.5
Time (ms)
4
4.5
5
Figure 22. Typical Start-up Waveform. Observe Initial Current Spike ‘A’ to
Ensure it is Below the 1-Cycle Current Limit. A Higher f MAX Reduces
it. Size the Soft-Start Capacitor so that the Peak of ‘B’ is just Below
the Peak Current at VBROWNOUT at Full Load.
need a peak detector or rectifier circuit. The pin has a reverse-biased
diode to ground equivalent circuit, and can tolerate a maximum
negative current of 5 mA. The primary current is sampled by a
primary, B- referenced current sense resistor, or by a capacitor current
divider + current sense resistor combination circuit. In order to limit
the negative current to 5 mA, a current limiting resistor between the
sense resistor and the IS pin is necessary, with a minimum value of
220 Ω. Using the minimum value maximizes the IS pin bypass
capacitor value and thus pin noise rejection, for a given RC pole
frequency. The IS pin will invoke a restart if it sees 7 consecutive
pulses >0.5 V. It will also invoke a restart if a single pulse exceeds
0.9 V. The minimum pulse detection time is nominally 30 ns – i.e. the
pulses must be higher than the threshold voltage for >30 ns.
The “capacitive divider” circuit in Figure 23 reduces power dissipation
and improves efficiency over a simple current sense resistor circuit.
The two capacitors, main resonant capacitor C11, and sense capacitor
C12, form a current divider. The portion of the primary current
routed through C12 is
C12
C11 + C12
.
Consequently, the voltage at the IS pin is equal to
IP #
C12
C11 + C12
# R11,
where IP is the primary current flowing from the HB pin through the
transformer primary. The current in the sense capacitor passes
through sense resistor R11. Resistor R11 is the main means for
tuning current limit. The signal on R11, an AC voltage, passes
through low-pass filter R12 and C7, to the IS pin. Note that R11 is
returned to the GROUND pin and not to SOURCE pin.
16
Rev. G 05/17
www.power.com
LCS700-708
24.1
24.0
HB Voltage (V)
Burst Mode Operation and Tuning
Burst mode will produce a typical waveform such as in Figure 24.
During the burst pulse train, the switching frequency rises from fSTART
to fSTOP.
PI-6469-062811
Output Ripple Voltage (V)
The recommended series resistor value of 220 W and the bypass
capacitor form a low-pass filter, and its time constant must not cause
significant attenuation of the current sense signal at the nominal
operating frequency. The effect of the attenuation is greatest for the
first pulse in the start-up current waveform, and can also affect
proper shutdown during short-circuit testing, which typically trips the
7-cycle current limit. Place a close-coupled probe across the IS pin
bypass capacitor and compare the waveform to the primary current.
400
23.9
300
200
100
0
LLC
Transformer
0
HB Pin
25
Time (μs)
50
Figure 25. Zoom in of First Few Switching Cycles of Burst Pulse Train of Figure
24. The First 2 Cycles Show That the High-Side Driver has not
Turned on yet. The Switching Frequency of the First Few Cycles is
fSTART, 335 kHz in This Case. The Ringing on the Output is from the
Output Filter.
C12
47 pF
1 kV
C11
6.8 nF
1 kV
IS Pin
C7
GROUND 220 pF
Pin
R12
1 kΩ
R11
24 Ω
S Pin
PI-6161-093010
I = C # dv
dt
Figure 23. Capacitive Divider Current Sense Circuit.
Where I = load current. C is the total output capacitance.
PI-6468-062811
24.1
Output Ripple Voltage (V)
HB Voltage (V)
24.0
23.9
400
300
200
100
0
Burst Repetition Rate
0
50
Time (ms)
If the initial output ripple spike at the beginning of the burst pulse
train is ignored, the output ripple somewhat resembles a sawtooth.
See the output ripple waveform in Figure 24. When the HiperLCS is
switching, the output rises. When it stops switching, the output falls.
The top of the sawtooth is where the burst pulse train ends, because
the feedback loop has commanded a frequency = fSTOP. The bottom of
the sawtooth is where the burst pulse train begins, because the
feedback loop has commanded a frequency = fSTART. As such, the
burst mode control resembles a hysteretic controller, where the top
and bottom of the sawtooth are fixed by the feedback loop gain. The
downward slope of the sawtooth is merely the output capacitors
discharging into the load, with dv/dt:
100
The upward slope of the sawtooth is dependent on the difference
between the current delivered by the powertrain, and the current
drawn by the load. For a given design, the upward slope increases
with input voltage.
The burst repetition rate (frequency) then increases with load. When
the load reaches a point where the powertrain can regulate at a
frequency 30 N applied to the center of the package.
3. Junction to case thermal resistance is based on hottest
junction, case temperature measured at center of package
back surface.
4. Temperature difference between hottest junction and over temperature sensor.
Conditions
SOURCE = 0 V;
TJ = -40 °C to 125 °C (D)
VCC = 12 V, VCCH = 12 V
(Unless Otherwise Specified)
Min
Typ
Max
Units
Half-Bridge
OFF-State Current
Breakdown Voltage
IDSS
BVDSS
Measured from D to
HB or from HB to S
TJ = 100 °C, VCC = 12
V, VCCH = 12 V,
VD = 424 V
LCS700
60
LCS701
60
LCS702
65
LCS703
80
LCS705
120
LCS708
200
VCC = 12 V, VCCH = 12 V, 250 mA, TJ = 25 °C
Measured from D to HB or from HB to S
530
mA
V
19
www.power.com
Rev. G 05/15
LCS700-708
Parameter
Symbol
Conditions
SOURCE = 0 V;
TJ = -40 °C to 125 °C (D)
VCC = 12 V, VCCH = 12 V
(Unless Otherwise Specified)
BVDSS(TC)
Measured from D to HB or from HB to S
Min
Typ
Max
Units
Half-Bridge (cont.)
Breakdown Voltage
Temperature
Coefficient
ON-State Resistance
ON-State Resistance
Half-Bridge
Capacitance
Diode Forward
Voltage
RDS(ON)
RDS(ON)
CHB
VFWD
Measured from D to
HB or from HB to S
VCC = 12 V, VCCH = 12
V, TJ = 25 °C
Measured from D to
HB or from HB to S
VCC = 12 V, VCCH = 12
V, TJ = 100 °C
V/°C
LCS700, I = 0.8 A
1.53
1.82
LCS701, I = 1.2 A
1.00
1.24
LCS702, I = 1.6 A
0.74
0.92
LSC703, I = 2.0 A
0.60
0.73
LCS705, I = 3.0 A
0.40
0.49
LCS708, I = 4.8 A
0.26
0.31
LCS700, I = 0.8 A
2.15
2.63
LCS701, I = 1.2 A
1.42
1.78
LCS702, I = 1.6 A
1.05
1.33
LCS703, I = 2.0 A
0.85
1.06
LCS705, I = 3.0 A
0.58
0.71
LCS708, I = 4.8 A
0.36
0.45
LCS700
134
Effective half-bridge
capacitance.
VHB swinging from
0 V to 400 V or
400 V to 0 V,
See Note A
Measured from HB to
D or from S to HB
TJ = 125 °C
0.2
LCS701
201
LCS702
268
LCS703
335
LCS705
503
LCS708
804
LCS700, I = 0.8 A
1.15
LCS701, I = 1.2 A
1.15
LCS702, I = 1.6 A
1.15
LSC703, I = 2.0 A
1.15
LCS705, I = 3.0 A
1.15
LCS708, I = 4.8 A
1.15
W
W
pF
V
Power Supply
VCC Supply
Voltage Range
VCC
See Note C
11.4
12
15
V
VCCH Supply
Voltage Range
VCCH
See Note C
11.4
12
15
V
ICC(OFF)
Undervoltage lockout state: VCC = 7 V
120
170
mA
ICC(INHIBIT)
VCC = 12 V, OV/UV < VSD(L)
450
650
mA
LCS700
2.8
5.2
LCS701
3.3
5.8
LCS702
3.8
6.5
LCS703
4.2
7.1
LCS705
5.4
8.8
LCS708
7.4
11.8
Start-Up Current
Inhibit Current
VCC Operating
Current
VCCH Operating
Current
ICC(ON)
ICCH(ON)
Typical at VCC = 12 V
Maximum at VCC =
15 V Measured at
300 kHz, HB Open
and VD = 15 V
Typical at VCCH = 12 V
Maximum at VCCH =
15 V Measured at
300 kHz, HB Open and
VD = 15 V
LCS700
2.4
4.6
LCS701
2.9
5.2
LCS702
3.3
5.8
LSC703
3.7
6.4
LCS705
4.8
7.9
LCS708
6.8
10.7
mA
mA
20
Rev. G 05/17
www.power.com
LCS700-708
Parameter
Symbol
Conditions
SOURCE = 0 V;
TJ = -40 °C to 125 °C (D)
VCC = 12 V, VCCH = 12 V
(Unless Otherwise Specified)
Min
Typ
Max
Units
VCCH Supply Undervoltage Lockout
VCC Start Threshold
VUVLO(+)
Device exits UVLO state when VCC exceeds
UVLO+, TJ = 0 to 100 °C
10
10.5
11.4
V
VCC Shutdown Threshold
VUVLO(-)
Device enters UVLO state when VCC falls below
UVLO+, TJ = 0 to 100 °C
9.1
9.5
10.5
V
VCC Start-Up/
Shutdown Hysteresis
VUVLO(HYST)
TJ = 0 to 100 °C
0.7
1.0
1.2
V
VCCH Start Threshold
VUVLO(H+)
Driver exits UVLO state when VCCH exceeds
UVLOH+
8.2
8.5
8.9
V
VCCH Shutdown Threshold
VUVLO(H-)
Driver enters UVLO state when VCCH falls
below UVLOH-
7.2
7.5
7.9
V
0.8
1.0
1.2
V
VCCH Start-Up/Shutdown Hysteresis
VUVLO(H)HYST
High-Voltage Supply Undervoltage/Overvoltage Enable
OV/UV Overvoltage
Shutdown Threshold
VOV(H)
Overvoltage assertion threshold
129
131
133
% of VSD(H)
OV/UV Overvoltage
Recovery Threshold
VOV(L)
Overvoltage de-assertion threshold
124
126
128
% of VSD(H)
OV/UV Undervoltage
Start Threshold
VSD(H)
Undervoltage de-assertion threshold
2.35
2.40
2.45
V
OV/UV Undervoltage
Shutdown Threshold
VSD(L)
Undervoltage assertion threshold
77
79
81
% of VSD(H)
R IN(OVUV)
OV/UV pin resistance to G
TJ = 25 °C
4.0
5.0
6.0
MW
OV/UV Pin
Input Resistance
OV/UV Pin Input
Resistance Temperature
Coefficient
R IN(OVUVTC)
-0.4
%/°C
Reference
Reference Voltage
VREF
Current Source Capability of VREF Pin
IREF
VREF Capacitance
CREF
IREF = 4 mA
Required external coupling on VREF pin
3.20
3.40
3.50
V
4
mA
1
mF
LLC Oscillator
Frequency Range
Accuracy of Minimum
Frequency Limit
Accuracy of Maximum
Frequency Limit
Duty Balance
Dead-TimeB
DT/BF Control
Current Range
FRANGE
25
1000
kHz
FMIN(ACC)
RFB = 37.9 kW to VREF , 180 kHz
-5.0
5.0
FMIN(ACL)
RFB = 154 kW to VREF , 48 kHz
TJ = 25 °C
-7.5
7.5
FMAX(ACC)
IFB = IDT/BF, RFMAX = 12.5 kW,
FMAX = 510 kHz, TJ = 0 to 100 °C
-7.5
7.5
%
DLLC
Duty symmetry of the half-bridge waveform,
CFB = 4.7 nF, CDT/BF = 4.7 nF, 250 kHz
Use recommended layout
49
51
%
tD
RFMAX = 7 kW, RBURST = 39.6 kW
IDT/BF
330
30
%
ns
430
mA
21
www.power.com
Rev. G 05/15
LCS700-708
Symbol
Conditions
SOURCE = 0 V;
TJ = -40 °C to 125 °C (D)
VCC = 12 V, VCCH = 12 V
(Unless Otherwise Specified)
ISTOP1
Threshold applies after exiting soft-start mode
for burst setting BT1
52.0
ISTOP2
Threshold applies after exiting soft-start mode
for burst setting BT2
46.0
ISTOP3
Threshold applies after exiting soft-start mode
for burst setting BT3
39.0
IBURST(HYST)
ISTART is IBURST(HYST) below ISTOP
5
6.8
8
VBT1
Required VDT/BF at start-up to enable burst
setting BT1
93.5
95
96.3
VBT2
Required VDT/BF at start-up to enable burst
setting BT2
88.5
90
91.3
VBT3
Required VDT/BF at start-up to enable burst
setting BT3
83.5
85
86.3
RCDT/BF
This time constant must be less than the
specified maximum to ensure correct setting
of burst mode.
Feedback Current
Maximum
IFB
Determines the maximum control
frequency that can be set by IFB
Feedback Control
Current Range
IFB
IFB is limited by the current into DT/BF
Feedback Virtual
Voltage
VFB
FB input appears as R IN(FB) in series with VFB,
30 mA < IFB < IDT/BF
0.65
V
Feedback Input
Resistance
R IN(FB)
FB input appears as R IN(FB) in series with VFB,
30 mA < IFB < IDT/BF
2.5
kW
Feedback Input
Resistance During
Soft-Start
RFB(SS)
FB input appears as RFB(SS) in series with VREF
during the soft-start delay interval or when
OV/UV < VSD or OV/UV > VOV
750
W
Parameter
Min
Typ
Max
Units
LLC Oscillator (cont.)
IFB Threshold to Stop
LLC Switching
IFB Threshold
Hysteresis
DT/BF Voltage to
Program Burst Setting
Time Constant for the
Combination of RFMAX,
RBURST and the Decoupling Cap on DT/BF
% of IDT/BF
100
100
15
% of IDT/BF
% of VREF
ms
%IDT/BF
430
mA
Over-Current Protection
Fast Over-Current Fault
Voltage
Threshold4
VIS(F)
Slow Over-Current Fault
Voltage
Threshold
VIS(S)
7 LLC clock cycle debounce
tIS
Minimum time VIS exceeds VIS(F)/VIS(S) per cycle
to trigger fault protection
Over-Current Fault
Pulse Width
0.855
0.905
0.955
V
0.455
0.505
0.555
V
30
ns
125
°C
Over-Temperature Protection
Over-Temperature
Shutdown ThresholdA
TOT
NOTES:
A. Guaranteed by design.
B. Typical apparent dead-time at the HB pin under resonant ZVS conditions.
C. VCC/VCCH operating range to achieve power capabilities specified in data sheet power table.
D. Operation possibly limited by over-temperature shutdown.
22
Rev. G 05/17
www.power.com
LCS700-708
Typical Performance Characteristics
12
Current (mA)
12
10
8
6
LCS700
LCS701
LCS702
LCS703
LCS705
LCS708
4
2
200
300
400
500
Frequency (kHz)
600
700
2
Power (mW)
600
500
400
300
LCS700
LCS701
LCS702
LCS703
LCS705
LCS708
200
100
300
400
500
Frequency (kHz)
600
700
200
300
400
500
Frequency (kHz)
600
700
800
LCS700
LCS701
LCS702
LCS703
LCS705
LCS708
1000
800
600
400
0
800
0
50
100
150
200
250
300
350
400
Half-Bridge Voltage (V)
Figure 30. Half-Bridge Small Signal Capacitance vs. Half-Bridge Voltage.
PI-6758-050812
1.80
RDS(ON)
(Normalized To Room Temperature)
100
200
Figure 29. Control Power vs. Frequency.
1.60
1.40
1.20
1.00
1.50
1.00
0.50
0.00
-0.50
.80
.60
-40
0
1200
Capacitance (pF)
700
200
0
800
PI-6183-022912
800
100
LCS700
LCS701
LCS702
LCS703
LCS705
LCS708
Figure 28. VCCH Current vs. Frequency.
900
0
6
PI-6184-112910
100
8
PI-6759-050812
0
10
4
Figure 27. VCC Current vs. Frequency.
0
14
Shift In FMIN(ACC)
From Room Temperature (%)
Current (mA)
14
PI-6182-022912
16
0
16
PI-6181-022912
18
-1.00
-20
0
20
40
60
Temperature (°C)
Figure 31. Normalized R DS(ON) vs. Temperature.
80
100
120
-1.50
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
Figure 32. Typical FMIN(ACC) Shift vs. Temperature.
23
www.power.com
Rev. G 05/15
LCS700-708
4.00
528
Shift In FMIN(ACL)
From Room Temperature (%)
530
526
524
522
520
518
2.00
1.00
0.00
-2.00
514
-20
0
20
40
60
80
100
-3.00
-40
120
-20
0
Figure 33. Normalized BVDSS vs. Temperature.
40
80
100
120
80
100
120
80
100
120
6.00
PI-6762-050812
1.50
5.50
1.00
RIN(OVUV) (MΩ)
5.00
-0.50
-0.00
-0.50
4.50
4.00
3.50
-1.00
3.00
-1.50
2.50
-20
0
20
40
60
80
100
2.00
-40
120
-20
0
20
40
3.45
50.5
3.44
3.43
50.4
50.3
Duty Balance (%)
3.42
3.41
3.40
3.39
3.38
50.2
50.1
50.0
49.9
49.8
3.37
49.7
3.36
49.6
0
20
40
60
Temperature (°C)
Figure 37. Typical VREF vs. Temperature.
80
100
120
PI-6765-050812
Figure 36. Typical R IN(OVUV) vs. Temperature.
PI-6764-051412
Figure 35. Typical FMAX(ACC) vs. Temperature.
-20
60
Temperature (°C)
Temperature (°C)
3.35
-40
60
Figure 34. Typical FMIN(ACL) vs. Temperature.
2.00
VREF (V)
20
Temperature (°C)
PI-6763-051412
512
-40
Temperature (°C)
Shift In FMAX(ACC)
From Room Temperature (%)
3.00
-1.00
516
-2.00
-40
PI-6761-050812
532
PI-6760-050812
BVDSS
(Normalized To 530 V at Room Temperature)
Typical Performance Characteristics
49.5
-40
-20
0
20
40
60
Temperature (°C)
Figure 38. Typical Duty Balance vs. Temperature.
24
Rev. G 05/17
www.power.com
LCS700-708
Typical Performance Characteristics
465
PI-6767-050812
470
1.030
460
Normalized ICC(ON)
ICC(INHIBIT) (μA)
1.050
PI-6766-050812
475
455
450
445
440
1.010
0.990
0.970
435
430
425
-40
-20
0
20
40
60
80
100
0.950
-40
120
-20
0
Figure 39. Typical ICC(INHIBIT) vs. Temperature.
60
80
100
120
1.02
100
120
PI-6769-050812
10.6
VCC UVLO Threshold (V)
LCS700
LCS701
LCS702
LCS703
LCS705
LCS708
1.04
10.8
PI-6768-060712
Normalized ICCH(ON) (µA)
40
Figure 40. Normalized ICC(ON) vs. Temperature.
1.06
1
0.98
0.96
0.94
-40
20
Temperature (°C)
Temperature (°C)
10.4
10.2
VCC-UVLO(+)
VCC-UVLO(-)
10.0
9.8
9.6
9.4
-20
0
20
40
60
80
100
9.2
-40
120
-20
0
Figure 41. Typical ICCH(ON) vs. Temperature (Normalized to Room Temperature).
40
60
80
Figure 42. Typical VCC UVLO vs. Temperature.
PI-6770-050812
8.8
8.6
VCCH UVLO Threshold (V)
20
Temperature (°C)
Temperature (°C)
8.4
8.2
VCC-UVLO(+)
VCC-UVLO(-)
8.0
7.8
7.6
7.4
7.2
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
Figure 43. Typical VCCH UVLO vs. Temperature.
25
www.power.com
Rev. G 05/15
Rev. G 05/17
1
5
6
9
10 11
END VIEW
0.628 [15.95] Ref.
0.060 [1.52] Ref.
FRONT VIEW
7 8
Pin 1 I.D.
0.653 [16.59]
0.647 [16.43]
0.038 [0.97]
3 4
0.019 [0.48] Ref.
A
2
13 14
16
2
0.140 [3.56]
0.120 [3.05]
Detail A
SIDE VIEW
0.118 [3.00]
0.047 [1.19]
0.016 [0.41]
Ref.
0.290 (7.37]
Ref.
0.027 [0.70]
0.023 [0.58]
0.020 [0.50]
Detail A (Scale = 9×)
0.016 [0.41] 13×
0.011 [0.28]
0.020 M 0.51 M C
3
0.021 [0.53]
0.019 [0.48]
0.048 [1.22]
0.046 [1.17]
10° Ref.
All Around
0.056 [1.42] Ref.
0.325 [8.25]
0.320 [8.13]
B
0.081 [2.06]
0.077 [1.96]
C
eSIP-16J (H Package)
3
Dimensions in inches, (mm).
All dimensions are for reference.
PCB FOOT PRINT
0.118 (3.00)
0.029 Dia Hole
0.062 Dia Pad
BACK VIEW
4
0.024 [0.61] 13×
0.019 [0.48]
0.010 M 0.25 M C A B
0.207 [5.26]
0.187 [4.75]
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions noted are determined at the outermost
extremes of the plastic body exclusive of mold flash,
tie bar burrs, gate burrs, and interlead flash, but
including any mismatch between the top and bottom
of the plastic body. Maximum mold protrusion is 0.007
[0.18] per side.
3. Dimensions noted are inclusive of plating thickness.
4. Does not include interlead flash or protrusions.
5. Controlling dimensions in inches [mm].
PI-6632-120211
0.076 (1.93)
0.038 (0.97)
0.012 (0.30] Ref.
0.076 [1.93]
0.519 [13.18]
Ref.
LCS700-708
26
www.power.com
www.power.com
1
5
6
END VIEW
0.628 (15.95) Ref.
0.060 (1.52) Ref.
11
13
0.056 (1.42) Ref.
9
10
FRONT VIEW
Typ. 9 Places
7
8
Pin 1 I.D.
0.038 (0.97)
3
4
0.019 (0.48) Ref.
A
2
0.653 (16.59)
0.647 (16.43)
14
16
2
0.094 (2.40)
Detail A
0.048 (1.22)
0.046 (1.17)
0.021 (0.53)
0.019 (0.48)
10° Ref.
All Around
R0.012 (0.30)
Typ., Ref.
0.016 (0.41) 13×
0.011 (0.28)
0.020 M 0.51 M C
3
0.325 (8.25)
0.320 (8.13)
B
SIDE VIEW
0.027 (0.70)
0.023 (0.58)
0.020 (0.50)
0.128 (3.26)
0.122 (3.10)
0.144 (3.66) Ref.
0.047 (1.19) Ref.
0.050 (1.26) Ref.
0.290 (7.37)
Ref.
Detail A (N.T.S.)
0.081 (2.06)
0.077 (1.96)
C
eSIP-16K (L Package)
14
13
11
10
3
5
4
4
3
1
0.173 (4.39)
0.163 (4.14)
0.024 (0.61) 13×
0.019 (0.48)
0.010 M 0.25 M C A B
7
6
0.076 (1.93)
0.038 (0.97)
BACK VIEW
9
8
Dimensions in inches, (mm).
All dimensions are for reference.
PCB FOOT PRINT
0.094 (2.40)
0.029 Dia Hole
0.062 Dia Pad
16
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions noted are determined at the outermost
extremes of the plastic body exclusive of mold flash,
tie bar burrs, gate burrs, and interlead flash, but
including any mismatch between the top and bottom
of the plastic body. Maximum mold protrusion is 0.007
[0.18] per side.
3. Dimensions noted are inclusive of plating thickness.
4. Does not include interlead flash or protrusions.
5. Controlling dimensions in inches (mm).
PI-6454-020212
Typ. 3 Pieces
0.076 (1.93)
0.079 (1.99)
0.069 (1.74)
LCS700-708
Rev. G 05/15
27
LCS700-708
Part Ordering Information
• Hiper Product Family
• LCS Series Number
• Package Identifier
H
Plastic eSIP-16J
L
Plastic eSIP-16K
• Pin Finish
LCS 700
H
G
G
Halogen Free and RoHS Compliant
28
Rev. G 05/17
www.power.com
LCS700-708
Revision Notes
Date
B
Initial Release.
C
Added L bend parts.
06/20/11
02/12
C1
Removed backside metal H package option.
06/12
D
Not implemented.
E
Overmold change, extended temperature change.
E
Updated BVDSS(TC) unit, Junction Temperature range and added Note 7.
08/30/12
06/12
E
Corrected error in Figure 3.
12/02/14
F
Updated with new Brand Style.
06/15
G
Added LG package parts for LCS705 and LCS708.
05/17
29
www.power.com
Rev. G 05/15
For the latest updates, visit our website: www.power.com
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations
does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY
HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.
Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one
or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of
Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set
forth at http://www.power.com/ip.htm.
Life Support Policy
POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:
1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose
failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or
death to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or effectiveness.
The PI logo, TOPSwitch, TinySwitch, SENZero, SCALE, SCALE-iDriver, Qspeed, PeakSwitch, LYTSwitch, LinkZero, LinkSwitch, InnoSwitch, HiperTFS,
HiperPFS, HiperLCS, DPA-Switch, CAPZero, Clampless, EcoSmart, E-Shield, Filterfuse, FluxLink, StakFET, PI Expert and PI FACTS are trademarks of
Power Integrations, Inc. Other trademarks are property of their respective companies. ©2017, Power Integrations, Inc.
Power Integrations Worldwide Sales Support Locations
World Headquarters
5245 Hellyer Avenue
San Jose, CA 95138, USA
Main: +1-408-414-9200
Customer Service:
Worldwide: +1-65-635-64480
Americas: +1-408-414-9621
e-mail: usasales@power.com
China (Shanghai)
Rm 2410, Charity Plaza, No. 88
North Caoxi Road
Shanghai, PRC 200030
Phone: +86-21-6354-6323
e-mail: chinasales@power.com
China (Shenzhen)
17/F, Hivac Building, No. 2, Keji Nan
8th Road, Nanshan District,
Shenzhen, China, 518057
Phone: +86-755-8672-8689
e-mail: chinasales@power.com
Germany (AC-DC/LED Sales)
Lindwurmstrasse 114
D-80337 München
Germany
Phone: +49-89-5527-39100
e-mail: eurosales@power.com
Germany (IGBT Driver Sales)
HellwegForum 1
59469 Ense
Germany
Tel: +49-2938-64-39990
e-mail: igbt-driver.sales@
power.com
India
#1, 14th Main Road
Vasanthanagar
Bangalore-560052 India
Phone: +91-80-4113-8020
e-mail: indiasales@power.com
Italy
Via Milanese 20, 3rd. Fl.
20099 Sesto San Giovanni (MI) Italy
Phone: +39-024-550-8701
e-mail: eurosales@power.com
Japan
Kosei Dai-3 Bldg.
2-12-11, Shin-Yokohama,
Kohoku-ku
Yokohama-shi, Kanagawa
222-0033 Japan
Phone: +81-45-471-1021
e-mail: japansales@power.com
Korea
RM 602, 6FL
Korea City Air Terminal B/D, 159-6
Samsung-Dong, Kangnam-Gu,
Seoul, 135-728, Korea
Phone: +82-2-2016-6610
e-mail: koreasales@power.com
Singapore
51 Newton Road
#19-01/05 Goldhill Plaza
Singapore, 308900
Phone: +65-6358-2160
e-mail: singaporesales@power.com
Taiwan
5F, No. 318, Nei Hu Rd., Sec. 1
Nei Hu Dist.
Taipei 11493, Taiwan R.O.C.
Phone: +886-2-2659-4570
e-mail: taiwansales@power.com
UK
Building 5, Suite 21
The Westbrook Centre
Milton Road
Cambridge
CB4 1YG
Phone: +44 (0) 7823-557484
e-mail: eurosales@power.com
工商网监
湘ICP备2023018690号
