LNK584DG

LNK584-586 LinkZero-AX ™ Zero Standby Consumption Integrated Off-Line Switcher Product Highlights Lowest System Cost with Zero Standby Consumption • Simple system configuration provides zero consumption standby/Power-Down with user controlled wake up • Very tight IC parameter tolerances improves system manufacturing yield • Suitable for low-cost clampless designs • Frequency jittering greatly reduces EMI filter cost • Extended package creepage improves system field reliability Advanced Protection/Safety Features • Hysteretic thermal shutdown protection – automatic recovery reduces field returns • Universal input range allows worldwide operation • Auto-restart reduces delivered power by >85% during short-circuit and open loop fault conditions • Simple ON/OFF control, no loop compensation needed • High bandwidth provides fast turn on with no overshoot EcoSmart™ – Energy Efficient • Standby/Power-Down consumption less than 3 mW at 325 VDC input (Note 1) • Easily meets all global energy efficiency regulations with no added components • ON/OFF control provides constant efficiency to very light loads Applications • Ultra low consumption isolated or non-isolated standby and auxiliary supplies + PIN 132 VAC to withstand the instantaneous power dissipated when AC is first applied. The output voltage is directly sensed through feedback resistors R3 and R9, and regulated by LinkZero-AX (U1) via the FEEDBACK pin. Capacitor C7 provides high frequency filtering on the FEEDBACK pin to filter noise and to avoid switching cycle pulse bunching. The controller in U1 receives feedback from the output through feedback resistors R9 and R3. Based on that feedback, it enables or disables the switching of its integrated MOSFET to maintain output regulation. Switching cycles are skipped once the FEEDBACK pin threshold voltage (1.70 V) is exceeded. When the voltage on the FEEDBACK pin falls below the disable threshold (1.70 V), switching cycles are re-enabled. By adjusting the ratio of enabled to disabled switching cycles the output voltage is regulated. At increased loads, beyond the output peak power point, where all switching cycles are enabled, the FEEDBACK pin voltage begins to reduce as the power supply output voltage falls. Under this condition the switching frequency is also reduced to limit the maximum output overload power. When the FEEDBACK pin voltage drops below the auto-restart threshold (typically 0.9 V on the FEEDBACK pin), the power supply enters the auto-restart mode. In this mode, the power supply will turn off for approximately 1.2 s and then turn back on for approximately 145 ms. The auto-restart function reduces the average output current during an output short-circuit condition. Applications Example The circuit shown in Figure 4 is a typical non-isolated 5 V, 300 mA output auxiliary power supply using LinkZero-AX. Isolated configurations are also fully compatible with the LinkZero-AX where the FEEDBACK pin receives a signal from a primary feedback/bias winding or through an optocoupler. The circuit of Figure 4 is typical of auxiliary supplies in white goods where isolation is often not required. AC input differential filtering is C4 R8 220 pF 5.1 Ω 100 V L3 1 mH R2 4.7 kΩ D1 1N4007 D2 1N4007 1 10 T1 3 EE16 8 D6 SS15 L4 1.8 µH C6 220 µF 25 V C8 R13 56 µF 510 Ω 16 V 5 V, 300 mA RTN RF1 10 Ω 2W C1 3.3 µF 400 V C2 3.3 µF 400 V D C9 330 nF 50 V LinkZero-AX U1 LNK584DG FB BP/M S R9 1 kΩ 1% 85 - 265 VAC Q1 MMBT3904 R16 750 Ω R11 100 Ω R12 20 kΩ R10 20 kΩ PD Set D3 1N4007 D4 1N4007 C5 150 nF 25 V C10 47 µF 25 V C7 1 nF 50 V R3 511 Ω 1% SW1 Q2 MMBT3904 R4 10 kΩ R14 2 kΩ PD Reset RTN PI-6121-101210 Figure 4. Schematic of Non-Isolated 1.5 W, 5 V, 300 mA, 0.00 W Standby Consumption Power Supply. 4 Rev. B 05/11 www.powerint.com LNK584-586 The LinkZero-AX device is self biased through the DRAIN pin. An optional external bias, can be derived either from a third winding or from an output voltage rail in non-isolated designs. By providing an external supply current in excess of IS2 (310 mA for the LNK584) the internal 5.85 V regulator circuit is disabled providing a simple way to reduce device temperature and improve efficiency, especially at high line. A clampless primary circuit is achieved due to the very tight tolerance current limit device, plus the transformer construction techniques used. The peak drain voltage is therefore limited to typically less than 550 V at 265 VAC, providing significant margin to the 700 V minimum drain voltage specification (BVDSS). Output rectification and filtering is achieved with output rectifier D6 and filter capacitor C6. Due to the auto-restart feature, the average short-circuit output current is significantly less than 1 A, allowing low current rating and low cost rectifier D6 to be used. Output circuitry is designed to handle a continuous short-circuit on the power supply output. In this design a preload resistor R13 is used at the output of the supply to prevent automatic triggering of the Power-Down mode when the load is removed. LinkZero-AX Power-Down (PD) Mode Design Considerations LinkZero-AX goes into Power-Down mode when 160 consecutive switching cycles have been skipped. This condition occurs when the output load is low or the FEEDBACK pin is pulled high (for example through Q1 and R16 in Figure 4). The value of the BYPASS pin capacitor must be high enough to sustain enough current through R16 for more than the period of 160 switching cycles to successfully trigger the Power-Down mode. At low line input voltage (90 VAC) the 160 switching cycle period is ~1.6 ms as the internal oscillator frequency is 100 kHz. However as the input line voltage increases, the internal oscillator frequency is gradually reduced to keep the maximum output power relatively constant. At high line (265 VAC) therefore, the internal oscillator frequency can be as low as 78 kHz (see parameter table Note C). Therefore to provide sufficient margin to ensure Power-Down mode is triggered it is recommended that the Power-Down pulse (see Figure 1) is 2.5 ms (200 switching cycles at 80 kHz). LinkZero-AX stops switching once the Power-Down mode is triggered. The IC does not resume switching until the BYPASS pin is pulled below 1.5 V using the reset/wake up pulse (see Figure 1) and then allowed to recharge back up to 5.85 V through the drain connected 5.85 V regulator block. Transistor Q2 or mechanical switch SW1 can be used for resetting the Power-Down mode either electronically or mechanically. It is important to design the power supply to ensure that load transients and other external events do not unintentionally trigger Power-Down mode by causing 160 consecutive switching cycles to be skipped. It is recommended that a preload resistor is added to draw ~2% of the full load current (12 mA at 5 V in a 3 W power supply). Although this reduces full load efficiency slightly, it has no influence on the power consumption during Power-Down mode since the power supply output is fully discharged under this condition. Low value feedback resistors may also be used as a preload too. Recommended value of the feedback resistors is such that they should draw ~1% of full load current. Finally a capacitor in parallel to the high side feedback resistor can be used to increase the speed of the loop (C9 in Figure 4). These recommendations apply for full load to zero load transients. For applications with more limited load range, the preload and the capacitor in parallel to the high side feedback resistor may not be necessary. Layout Considerations LinkZero-AX Layout Considerations Layout See Figure 5 for a recommended circuit board layout for LinkZero-AX (U1). Single Point Grounding Use a single point ground (Kelvin) connection from the input filter capacitor to the area of copper connected to the SOURCE pins. Bypass Capacitor (CBP), FEEDBACK Pin Noise Filter Capacitor (CFB) and Feedback Resistors To minimize loop area, these two capacitors should be physically located as near as possible to the BYPASS and SOURCE pins, and FEEDBACK pin and source pins respectively. Also note that to minimize noise pickup, feedback resistors RFB1 and RFB2 are placed close to the FEEDBACK pin. Primary Loop Area The area of the primary loop that connects the input filter capacitor, transformer primary and LinkZero-AX should be kept as small as possible. Primary Clamp Circuit An external clamp may be used to limit peak voltage on the DRAIN pin at turn off. This can be achieved by using an RCD clamp or a Zener (~200 V) and diode clamp across the primary winding. In all cases, to minimize EMI, care should be taken to minimize the circuit path from the clamp components to the transformer and LinkZero-AX (U1). Thermal Considerations The copper area underneath the LinkZero-AX (U1) acts not only as a single point ground, but also as a heat sink. As it is connected to the quiet source node, this area should be maximized for good heat sinking of U1. The same applies to the cathode of the output diode. Y Capacitor The placement of the Y-type capacitor (if used) should be directly from the primary input filter capacitor positive terminal to the common/return terminal of the transformer secondary. Such a placement will route high magnitude common-mode surge currents away from U1. Note: If an input π EMI filter is used, the inductor in the π filter should be placed between the negative terminals on the input filter capacitors. 5 www.powerint.com Rev. B 05/11 LNK584-586 CB DBP RBP RFB2 CFB CBP RFB1 U1 DB RS CS DO CO Transformer R6 J3 HV DC IN LV DC OUT + PI-6098-092410 T1 + Figure 5. PCB Layout of a 2.1 W, 6 V, 350 mA Charger. Output Diode (DO) For best performance, the area of the loop connecting the secondary winding, the output diode (DO) and the output filter capacitor (CO) should be minimized. In addition, sufficient copper area should be provided at the anode and cathode terminals of the diode for heat sinking. A larger area is preferred at the electrically “quiet” cathode terminal. A large anode area can increase high frequency conducted and radiated EMI. Resistor RS and CS represent the secondary side RC snubber. Quick Design Checklist As with any power supply design, all LinkZero-AX designs should be verified on the bench to make sure that component specifications are not exceeded under worst-case conditions. The following minimum set of tests is strongly recommended: 1. Maximum drain voltage – Verify that VDS does not exceed 660 V at the highest input voltage and peak (overload) output power. This margin to the 700 V BVDSS specification gives margin for design variation, especially in clampless designs. 2. Maximum drain current – At maximum ambient temperature, maximum input voltage and peak output (overload) power, verify drain current waveforms for any signs of transformer saturation and excessive leading-edge current spikes at start-up. Repeat under steady state conditions and verify that the leading-edge current spike event is below ILIMIT(MIN) at the end of the tLEB(MIN). Under all conditions, the maximum drain current should be below the specified absolute maximum ratings. 3. Thermal check – At specified maximum output power, minimum input voltage and maximum ambient temperature, verify that the temperature specifications are not exceeded for LinkZero-AX, transformer, output diode and output capacitors. Enough thermal margin should be allowed for part-to-part variation of the RDS(ON) of LinkZero-AX as specified in the data sheet. Under low line and maximum power, maximum LinkZero-AX source pin temperature of 100 °C is recommended to allow for these variations. 6 Rev. B 05/11 – – www.powerint.com LNK584-586 Absolute Maximum Ratings(1,6) DRAIN Voltage .................................. ........................-0.3 V to 700 V Peak DRAIN Current (2): LNK584 ........................... 200 (375) mA LNK585 ........................... 370 (680) mA LNK586 ........................... 440 (825) mA Peak Negative Pulsed Drain Current(3)............................. -100 mA Feedback Voltage ......................................................... -0.3 V to 9 V Feedback Current ................................................................ 100 mA BYPASS Pin Voltage ...................................... ............. -0.3 V to 9 V BYPASS Pin Voltage in Power-Down Mode(7) ....... -0.3 V to 11 V Storage Temperature ........................................... -65 °C to 150 °C Operating Junction Temperature(4) ....................-40 °C to 150 °C Lead Temperature(5) ....................................................... ......... 260 °C Thermal Resistance Thermal Resistance: D Package: (qJA) .................................. 100 °C/W(2); 80 °C/W(3) (qJC) .........................................................30 °C/W(1) G Package: (qJA) .................................... 70 °C/W(2); 60 °C/W(3) (qJC) ......................................................... 11 °C/W(1) Notes: 1. Measured on the SOURCE pin close to plastic interface. 2. Soldered to 0.36 sq. in. (232 mm2), 2 oz. copper clad. 3. Soldered to 1 sq. in. (645 mm2), 2 oz. copper clad. Notes: 1. All voltages referenced to SOURCE, TA = 25 °C. 2. Higher peak DRAIN current allowed while DRAIN source voltage does not exceed 400 V. 3. Duration not to exceed 2 ms. 4. Normally limited by internal circuitry. 5. 1/16 in. from case for 5 seconds. 6. Maximum ratings specified may be applied, one at a time without causing permanent damage to the product. E xposure to Absolute Maximum ratings for extended periods of time may affect product reliability. 7. Maximum current into pin is 300 mA. Parameter Control Functions Output Frequency Frequency Jitter Ratio of Output Frequency at Auto-Restart to fOSC Maximum Duty Cycle FEEDBACK Pin Voltage FEEDBACK Pin Voltage at AutoRestart Minimum Switch ON-Time Symbol Conditions SOURCE = 0 V; TJ = -40 to 125 °C (Unless Otherwise Specified) Min Typ Max Units fOSC TJ = 25 °C VFB = 1.70 V, See Note B Peak-Peak Jitter Compared to Average Frequency, TJ = 25 °C 93 100 ±3 107 kHz % fOSC(AR) fOSC DCMAX VFB TJ = 25 °C VFB = VFB(AR) 60 1.63 60 63 1.70 1.77 % % V VFB(AR) 0.8 0.9 1.05 V tON(MIN) IS1 Feedback Voltage > VFB (MOSFET not Switching) LNK584 IS2 0.9 V ≤ VFB ≤ 1.70 V (MOSFET Switching) LNK585 LNK586 700 200 260 275 285 260 310 330 340 ns mA DRAIN Supply Current mA 7 www.powerint.com Rev. B 05/11 LNK584-586 Parameter Control Functions (cont.) Symbol Conditions SOURCE = 0 V; TJ = -40 to 125 °C (Unless Otherwise Specified) Min Typ Max Units BYPASS Pin Charge Current ICH1 VBP = 0 V, TJ = 25 °C VBP = 4 V, TJ = 25 °C LNK584 LNK585-586 LNK584 LNK585-586 -5.5 -7.0 -3.8 -4.8 5.60 0.8 6.1 -3.8 -5.3 -2.5 -3.5 5.85 1.0 6.5 -1.8 -3.3 -1.0 -2.0 6.10 1.2 6.9 V V V mA mA ICH2 BYPASS Pin Voltage BYPASS Pin Voltage Hysteresis BYPASS Pin Shunt Voltage BYPASS Pin Supply Current Circuit Protection VBP VBP(H) BPSHUNT IBPSC See Note D 84 di/dt = 40 mA/ms TJ = 25 °C Current Limit ILIMIT di/dt = 75 mA/ms TJ = 25 °C di/dt = 90 mA/ms TJ = 25 °C di/dt = 40 mA/ms TJ = 25 °C Power Coefficient I2f di/dt = 75 mA/ms TJ = 25 °C di/dt = 90 mA/ms TJ = 25 °C Leading Edge Blanking Time BYPASS Pin Shutdown Threshold Current Thermal Shutdown Temperature Thermal Shutdown Hysteresis Power-Down (PD) Mode OFF-State Drain Leakage in Power-Down Mode BYPASS Pin Overvoltage Protection in Power-Down Mode BYPASS Pin Power-Up Reset Threshold (in Power-Down Mode or at Power Supply Start-up) 8 Rev. B 05/11 LNK584 LNK585 LNK586 LNK584 LNK585 LNK586 126 232 279 1665 5625 8100 220 5.0 135 136 250 300 1850 6250 9000 265 6.5 142 70 146 268 321 2091 7063 10170 ns 8.0 150 mA °C °C A2Hz mA tLEB ISD TSD TSD(H) TJ = 25 °C VBP = BPSHUNT See Note F See Note A See Note A IDSS(PD) VBP(PDP) TJ = 25 °C, VDRAIN = 325 V See Figure 21 IBP = 300 mA -5 °C ≤ TJ ≤ 100 °C 7.0 6.5 9 mA V 8.5 10.9 VBP(PU) 1.5 3 4 V www.powerint.com LNK584-586 Parameter Symbol Conditions SOURCE = 0 V; TJ = -40 to 125 °C (Unless Otherwise Specified) Min Typ Max Units Power-Down (PD) Mode (cont.) BYPASS Pin Voltage in Power-Down Mode BYPASS PinPowerDown to Power-Up Threshold Delta BYPASS Pin Supply Current in Power-Down Mode Output LNK584 ID = 13 mA ON-State Resistance RDS(ON) LNK585 ID = 26 mA LNK586 ID = 33 mA Breakdown Voltage DRAIN Supply Voltage Auto-Restart ON-Time Auto-Restart Duty Cycle Output Enable Delay NOTES: A. This parameter is derived from characterization. B. Output frequency specification applies to low line input voltage in the final application. The controller is designed to reduce output frequency by approximately 20% at high line input voltages to balance low line and high line maximum output power. C. The auto-restart on-time/off-time is increased by 20% from low to high line voltage input (85 VAC to 265 VAC). D. IBPSC is the current that can be supplied from the BYPASS pin at 5.85 V when in normal switching mode of operation to power an optional external circuit. The current will be supplied from the Drain via the internal BYPASS pin voltage regulator. When calculating the power consumption the IBPSC (84 mA max) and the drain voltage has to be taken into account. More current can be sourced during Power-Down mode – see Note F. E. IBPSC(PD) is the current that can be supplied from the BYPASS pin at 4 V when in Power-Down mode to power an optional external circuit. The current will be supplied from the Drain via the internal BYPASS pin voltage regulator. Lower current is available during normal operation - see Note E. If the external circuit requires current in excess of IBP(PD) in Power-Down mode, it must be supplied from an external source such as a bias winding. The IBP(PD) current adds to power supply power consumption during Power-Down mode – for example at 230 VAC (325 VDC rectified DC rail voltage) the power consumption with be 325 × IBP(PD). F. LinkZero-AX shuts down if the current into the BYPASS pin reaches ISD at the BPSHUNT voltage. tEN tAR VIN = 85 VAC, TJ = 25 °C, See Note C See Figure 8 BVDSS TJ = 25 °C TJ = 100 °C TJ = 25 °C TJ = 100 °C TJ = 25 °C TJ = 100 °C 700 50 145 11 14 48 76 24 38 19 30 55 88 28 44 22 35 V V ms % ms W VBP(PD) VBP(PD) - VBP(PU) IBP(PD) VBP = VBP(PD) See Note E IBP = 500 mA 0.5 4 V V 500 mA VBP = 6.2 V, TJ = 25 °C 9 www.powerint.com Rev. B 05/11 LNK584-586 BP/M FB S S S 0.1 µF 0-2 V S1 50 V 470 Ω 5W D S PI-6067-072110 Figure 6. General Test Circuit. t2 (internal signal) tP DCMAX HV 90% DRAIN VOLTAGE 0V t1 90% FB t D= 1 t2 10% tP = PI-2048-033001 VDRAIN 1 fOSC tEN PI-3707-112503 Figure 7. Duty Cycle Measurement. Figure 8. Output Enable Timing. Figure 9. Peak Negative Pulsed DRAIN Current Waveform. 10 Rev. B 05/11 PI-4021-101305 www.powerint.com LNK584-586 Typical Performance Characteristics PI-2213-012301 Breakdown Voltage (Normalized to 25 °C) Output Frequency (Normalized to 25 °C) 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 1.0 0.9 -50 -25 0 25 50 75 100 125 150 100 125 Junction Temperature (°C) Figure 10. Breakdown vs. Temperature. Junction Temperature (°C) Figure 11. Frequency vs. Temperature. 1.0 0.8 0.6 0.4 0.2 0 -50 0 50 100 150 FEEDBACK Pin Voltage (Normalized to 25 °C) 1.2 Current Limit (Normalized to 25 °C) PI-6066-071910 1.0 0.9 -50 -25 0 25 50 75 100 125 150 Temperature (°C) Figure 12. Current Limit vs. Temperature. Temperature (°C) Figure 13. FEEDBACK Pin Voltage vs. Temperature. PI-2240-012301 BYPASS Pin Voltage (V) 6 5 4 3 2 1 0 175 DRAIN Current (mA) 150 125 100 75 50 25 0 0 2 4 6 0 0.2 0.4 0.6 0.8 1.0 8 10 12 14 16 18 20 Time (ms) Figure 14. BYPASS Pin Start-up Waveform (CBP = 0.22 mF). DRAIN Voltage (V) Figure 15. Output Characteristics. PI-3927-083104 7 200 PI-4057-071905 1.4 1.1 PI-6065-071910 1.1 1.2 11 www.powerint.com Rev. B 05/11 LNK584-586 Typical Performance Characteristics (cont.) PI-3928-083104 PI-6068-071910 1000 110 100 Drain Capacitance (pF) 100 Frequency (kHz) 90 80 70 10 1 0 100 200 300 400 500 600 60 0 10 20 30 40 50 60 70 Drain Voltage (V) Figure 16. CDSS vs. Drain Voltage. Duty Cycle (%) Figure 17. Frequency Reduction vs. Duty Cycle (Line Voltage). PI-6070-072110 FEEDBACK Pin Current (µA) 40 30 20 10 0 -10 -20 -30 0.0 1.0 2.0 3.0 4.0 5.0 6.0 FEEDBACK Pin Current (µA) -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 7.0 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 FEEDBACK Pin Voltage (V) Figure 18. FEEDBACK Pin Input Characteristics. FEEDBACK Pin Voltage (V) Figure 19. FEEDBACK Pin Input Characteristics During Output Power Limiting (1.70 V to 0.9 V). 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 PI-6139-091010 FEEDBACK Pin Current (µA) 9 Drain Current (µA) 8 7 6 5 4 3 2 1 0 Auto-Restart 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -50 -25 0 25 50 75 100 125 Frequency Normalized to 1 Figure 20. Frequency Cut Back During Output Power Limiting. Temperature (°C) Figure 21. Typical Drain Current vs. Temperature in Power-Down Mode. 12 Rev. B 05/11 www.powerint.com PI-6111-081810 10 PI-6071-072110 50 0 LNK584-586 SO-8C (D Package) 4 B 2 4.90 (0.193) BSC A 8 4 5 GAUGE PLANE 0.10 (0.004) C A-B 2X DETAIL A D 2 3.90 (0.154) BSC 6.00 (0.236) BSC SEATING PLANE C 1.04 (0.041) REF 0-8 0.10 (0.004) C D 2X Pin 1 ID 1.27 (0.050) BSC 1 4 0.20 (0.008) C 2X 7X 0.31 - 0.51 (0.012 - 0.020) 0.25 (0.010) M C A-B D 1.25 - 1.65 (0.049 - 0.065) 0.10 (0.004) C 7X SEATING PLANE C H 0.25 (0.010) BSC 0.40 (0.016) 1.27 (0.050) 1.35 (0.053) 1.75 (0.069) 0.10 (0.004) 0.25 (0.010) DETAIL A 0.17 (0.007) 0.25 (0.010) Reference Solder Pad Dimensions 2.00 (0.079) 4.90 (0.193) Notes: 1. JEDEC reference: MS-012. 2. Package outline exclusive of mold flash and metal burr. 3. Package outline inclusive of plating thickness. 4. Datums A and B to be determined at datum plane H. 5. Controlling dimensions are in millimeters. Inch dimensions are shown in parenthesis. Angles in degrees. D07C 1.27 (0.050) 0.60 (0.024) PI-4526-040110 13 www.powerint.com Rev. B 05/11 LNK584-586 SMD-8C (G Package) ⊕ D S .004 (.10) -E.086 .240 (6.10) .260 (6.60) .372 (9.45) .388 (9.86) ⊕ E S .010 (.25) .186 .286 .420 .046 .060 .060 .046 .080 Notes: 1. Controlling dimensions are inches. Millimeter sizes are shown in parentheses. 2. Dimensions shown do not include mold flash or other protrusions. Mold flash or protrusions shall not exceed .006 (.15) on any side. 3. Pin locations start with Pin 1, and continue counter-clockwise to Pin 8 when viewed from the top. Pin 3 is omitted. 4. Minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.48 mm). 5. Lead width measured at package body. 6. D and E are referenced datums on the package body. Pin 1 .137 (3.48) MINIMUM Pin 1 .100 (2.54) (BSC) Solder Pad Dimensions -D- .367 (9.32) .387 (9.83) .057 (1.45) .068 (1.73) (NOTE 5) .125 (3.18) .145 (3.68) .032 (.81) .037 (.94) .048 (1.22) .053 (1.35) .004 (.10) .009 (.23) .004 (.10) .012 (.30) .036 (0.91) .044 (1.12) 0°- 8° G08C PI-4015-101507 14 Rev. B 05/11 www.powerint.com LNK584-586 Part Ordering Information • LinkSwitch Product Family • AX Series Number • Package Identifier D G G Blank LNK 584 D G - TL TL Plastic SO-8C Plastic SMD-8C GREEN: Halogen Free and RoHS Compliant Standard Configurations Tape & Reel, 2.5 k pcs minimum for D package, 1 k pcs minimum for G Package. • Package Material • Tape & Reel and Other Options 15 www.powerint.com Rev. B 05/11 Revision A B Notes Initial release Added LNK585 and LNK586 Date 10/10 05/11 For the latest updates, visit our website: www.powerint.com Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS. Patent Information The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more U.S. and foreign patents, or Power Integrationslly by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrations patents may be found at www.powerint.com. Power Integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm. Life Support Policy POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein: 1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or death to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, PeakSwitch, CAPZero, SENZero, LinkZero, HiperPFS, HiperTFS, Qspeed, EcoSmart, Clampless, E-Shield, Filterfuse, StakFET, PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©2011, Power Integrations, Inc. Power Integrations Worldwide Sales Support Locations World Headquarters 5245 Hellyer Avenue San Jose, CA 95138, USA. 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