LYT2002-2005
LYTSwitch-2 Family
Energy-Efficient, Accurate Primary-Side Regulation
CC/CV Switcher for LED Lighting Applications
Product Highlights
Accurate CC Regulation, Meets ±3% in a Typical
Design1
Controller Automatically Compensates For:
• Transformer inductance variation
• External component changes with temperature
• Input line voltage variations
This enhances production yield
Cost-Effective, Small Size Designs
Eliminates the optocoupler and secondary CC control circuitry
Eliminates control loop compensation circuitry
Frequency-jitter greatly reduces EMI filter cost
Programmable switching frequency reduces transformer size
725 V switching power MOSFET enables clampless flyback designs
•
•
•
•
•
AC
IN
D
LYTSwitch-2
FB
BP
S
PI-7037a-051914
Figure 1. Typical Flyback Implementation – Not a Simplified Circuit.
Advanced Protection/Safety Features
• Auto-restart protection reduces power delivered by >90% for output
short-circuit and control loop faults (open and short-circuit components)
• Hysteretic thermal shutdown – with automatic recovery
• Meets high-voltage creepage requirements between DRAIN and all
other pins both on the PCB and at the package
Output Power Table2
EcoSmart™– Energy Efficient
• No-load consumption 86 % Average Efficiency, 86% and
80%.
Discontinuous mode operation (KP >1.3).
The LYTSwitch-2 part is either board mounted with SOURCE pins
soldered to a sufficient area of copper to keep the SOURCE pin
temperature at or below 100 °C, or (in the case of the E package)
attached to a sufficiently sized heat sink to limit device temperature to below 110 °C.
Ambient temperature of less than 50 °C for open frame designs
and an internal enclosure temperature of 60 °C for enclosed
ballast-type designs.
Note: Higher output powers are achievable if an output CC tolerance
> ±10% is acceptable, and allowing the device to be operated at a
higher SOURCE pin temperature.
Output Tolerance
LYTSwitch-2 K and E package parts provides an overall CC mode
output current tolerance of ±5% including line voltage, normal
board-to-board component variation and across a temperature range
of 0 °C to 110 °C. For the D package (SO-8) additional CC variance
may occur due to stress caused by manufacturing (i.e. solder-wave
immersion or IR reflow).
A sample power supply build is recommended to verify production
tolerances for each design.
BYPASS Pin Capacitor Selection
A 1 mF BYPASS pin capacitor is recommended. The capacitor voltage
rating should be greater than 7 V. The capacitor can be ceramic or
electrolytic but tolerance of capacitor should be ≤ ±50%. The
capacitor must be physically located close to the LYTSwitch-2 BYPASS
pin for effective noise decoupling.
LYTSwitch-2 Layout Considerations
Circuit Board Layout
The LYTSwitch-2 family of ICs present a highly integrated power
supply solution that integrates, both, the controller and the highvoltage power MOSFET onto a single die. The presence of high
switching currents and voltages together with analog signals makes
it especially important to follow good PCB design practice to ensure
stable and trouble free operation of the power supply. See Figures 5
and 6 for a recommended circuit board layout for LYTSwitch-2.
When designing a printed circuit board layout for the LYTSwitch-2 based
power supply, it is important to follow these guidelines:
Single Point Grounding
Use a single point (Kelvin) connection at the negative terminal of the
input filter capacitor for the LYTSwitch-2 SOURCE pin and bias
winding return. This improves surge capabilities by returning surge
currents from the bias winding directly to the input filter capacitor.
Bypass Capacitor
The BYPASS pin capacitor should be located as close as possible to
the SOURCE and BYPASS pins for effective noise decoupling.
Feedback Resistors
Place the feedback resistors (R7 and R8) very close to the FEEDBACK
pin of the LYTSwitch-2 device. This minimizes noise coupling.
Thermal Considerations (D and K Package)
The copper area connected to the SOURCE pins provides heat sinking.
A good estimate of expected power dissipation is to assume is that
the LYTSwitch-2 will dissipate 5% of the output power. Provide
enough copper area to keep the SOURCE pin temperature below
100 °C. Higher temperatures are allowable but output current (CC)
tolerance will increase. In this case a maximum SOURCE pin temperature below 100 °C is recommended to provide margin for part-to-part
RDS(ON) variation.
Secondary Loop Area
To minimize leakage inductance and EMI the area of the loop
contained within the connections between the secondary winding
(T1), the output diode (D3) and the output filter capacitor (C6) should
be minimized. In addition, sufficient copper area should be to the
rectifier diode for heat sinking preferably connected to the quiet
cathode terminal. A large anode area can increase high frequency
radiated EMI.
Electrostatic Discharge Spark Gap
A trace is placed at one of the AC line inputs to form one electrode of
a spark gap. The other electrode on the secondary is formed by the
output return node. The spark gap directs most ESD energy from the
secondary back to the AC input during a surge event. The trace from
the AC input to the spark gap electrode should be spaced away from
other traces to prevent unwanted arcing occurring and possible circuit
damage. If R1 and R2 are removed additional spark gaps across the
EMI filter inductors (L1 and L2) to prevent excessive build-up of
voltage across them during surge.
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Rev. B 09/15
LYT2002-2005
Figure 5. PCB Layout Example using SO-8C Package.
Figure 6. PCB Layout Example using eSIP Package.
Drain Clamp Optimization
LYTSwitch-2 ICs use primary-side sensing to regulate the output.
The voltage that appears on the primary winding is a reflection of the
secondary winding voltage while the internal is off. Leakage inductance
induced ringing can affect output regulation. Optimizing the drain
clamp to minimize high frequency ringing will give the best regulation.
Figure 7 shows the desired drain voltage waveform; while Figure 8
shows a large undershoot due to a leakage inductance induced ring.
Ringing can be reduced (and hence regulation improved) by adjusting
the value of the resistor in series with the primary clamp diode.
Quick Design Checklist
Addition of a Bias Circuit for Higher Light Load Efficiency and
Lower No-load Input Power Consumption
The addition of a bias circuit can decrease the no-load input power
from ~200 mW to less than 30 mW at 230 VAC input.
The power supply schematic shown in Figure 4 has the bias circuit
incorporated. Diode D2, C5 and R9 form the bias circuit.
Diode D2 rectifies the output and C5 is the filter capacitor. A 1 mF
capacitor is recommended to maintain the minimum bias voltage at
low switching frequencies.
The recommended current into the BYPASS pin is equal to IC supply
current (~0.5 mA) at the minimum bias winding voltage. The BYPASS
pin current should not exceed 3 mA at the maximum bias winding
voltage. The value of R9 is calculated according to (VBIAS-VBP)/IS2,
where VBIAS (10 V typical) is the voltage across C5, IS2 (0.5 mA typ.) is
the IC supply current and VBP (6.2 V typ.) is the BYPASS pin voltage.
As with any power supply design, all LYTSwitch-2 family designs should
be verified on the bench to make sure that component specifications
are not exceeded under worst-case conditions. The following set of
tests is strongly recommended:
1. Maximum drain voltage – Verify that the peak VDS does not
exceed 680 V at the highest input voltage and maximum output
power.
2. Drain current – At maximum ambient temperature, maximum and
minimum input voltage and maximum output load, review drain
current waveforms at start-up for any signs of transformer
saturation or excessive leading edge current spikes. LYTSwitch-2
devices have a leading edge blanking time to prevent premature
termination of the ON-cycle, but limit leading edge spikes to less
than the maximum time as specified in the data sheet.
3. Thermal check – At maximum output power, for both minimum
and maximum input voltage and maximum ambient temperature;
verify that temperature limits are not exceeded for LYTSwitch-2,
transformer, output diodes and output capacitors. Thermal
margin should be provided to allow for part-to-part variation in the
RDS(ON) of the LYTSwitch-2 device. For optimum regulation, a
SOURCE pin temperature of 90 ºC is recommended.
Design Tools
Up-to-date information on design tools can be found at the Power
Integrations web site: www.power.com
The parameters IS2 and VBP are provided in the parameter table of the
LYTSwitch-2 data sheet. Diode D2 can be a low-cost type such as
FR102, 1N4148 or BAV19/20/21.
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Rev. B 09/15
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LYT2002-2005
An overshoot is acceptable
Negative ring may increase
output ripple and/or degrade
output regulation
Figure 7.
Desired Drain Voltage Waveform with Minimal Leakage Ringing
Undershoot.
Figure 8. Undesirable Drain Voltage Waveform with Large Leakage Ring
Undershoot.
C7
1 nF
500 VAC
R1
10 kΩ
1/8 W
R2
220 kΩ
L1
470 µH
C3
1000 pF
630 V
2
R4
100 Ω
BR1
B10S-G
1000 V
L
90 - 265
VAC
N
C1
4.7 µF
400 V
C6
100 µF
100 V
9
48 V
R10
130 kΩ
J5
RTN
J6
NC
5
D1
S1ML
F1
2A
J2
D3
UF5404
10
1
4
T1
EE19
C2
33 µF
400 V
LYTSwitch-2
U1
LYT2005E
J1
D
R7
140 kΩ
1%
1/8 W
FB
BP
S
C4
1 µF
50 V
R8
8.06 kΩ
1%
1/8 W
PI-7284-043014
Figure 9.
Example Schematic of LYTSwitch-2 Flyback Power Supply without Bias Supply.
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Rev. B 09/15
LYT2002-2005
Absolute Maximum Ratings(1,6)
DRAIN Voltage..........................................................-0.3 V to 725 V
DRAIN Pin Peak Current(5): .LYT2002.......................... 504 (750) mA(2)
LYT2003.......................... 654 (980) mA(2)
LYT2004......................... 686 (1029) mA(2)
LYT2005......................... 784 (1176) mA(2)
Peak Negative Pulsed Drain Current................................... -100 mA(3)
FEEDBACK Pin Voltage .................................................... -0.3 to 9 V
FEEDBACK Pin Current..........................................................100 mA
BYPASS Pin Voltage......................................................... -0.3 to 9 V
Storage Temperature .................................................. -65 to 150 °C
Operating Junction Temperature(4)................................ -40 to 150 °C
Lead Temperature(5)............................................................... 260 °C
Notes:
1. All voltages referenced to SOURCE, TA = 25 °C.
2. Higher peak Drain current allowed while Drain to Source
voltage does not exceed 400 V.
3. Duration not to exceed 2 ms.
4. Normally limited by internal circuitry.
5. 1/16 in. from case for 5 seconds.
6. Absolute Maximum Ratings specified may be applied, one
at a time without causing permanent damage to the
product. Exposure to Absolute Maximum Ratings for
extended periods of time may affect product reliability.
Thermal Resistance
Thermal Resistance: D Package:
(qJA) ....................................... 100 °C/W(2), 80 °C/W(3)
(qJC)(1).......................................................... 30 °C/W
E Package
(qJA)............................................... 105
(qJC)...................................................2
K Package
(qJA) ............................... 45 °C/W(6), 38
(qJC)...................................................2
Parameter
Symbol
°C/W(4)
°C/W(5)
°C/W(7)
°C/W(5)
Notes:
1. Measured on pin 8 (SOURCE) close to plastic interface.
2. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad.
3. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad.
4.
5.
6.
Free standing with no heat sink.
Measured at the back surface of tab.
Soldered (including exposed pad for K package) to typical
application PCB with a heat sinking area of 0.36 sq. in.
(232 mm2), 2 oz. (610 g/m2) copper clad.
7. Soldered (including exposed pad for K package) to typical
application PCB with a heat sinking area of 1 sq. in. (645 mm2),
2 oz. (610 g/m2) copper clad.
Conditions
SOURCE = 0 V; TJ = 0 to 100 °C
(Unless Otherwise Specified)
Min
Typ
Max
Units
85
kHz
Control Functions
Programmable
Maximum Frequency
Minimum Operation
Frequency
fOSC
TJ = 25 °C
tON × IFB = 1.4 mA-ms
See Note A
fOSC(MIN)
TJ = 25 °C
VFB = VFBth
VFB = VFBth
LYT2002-2003
300
330
365
LYT2004
775
850
930
LYT2005
510
580
645
Frequency Ratio
(Constant Current)
fRATIO(CC)
TJ = 25 °C
Between VFB = 1.0 V and VFB = 1.6 V
1.550
1.593
1.635
Frequency Ratio
(Inductance
Correction)
fRATIO(IC)
Between tON × IFB = 1.4 mA and
tON × IFB = 2 mA-ms
1.160
1.210
1.260
Frequency Jitter
Peak-to-Peak Jitter Compared to Average
Frequency, TJ = 25 °C
±7
Hz
%
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Rev. B 09/15
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LYT2002-2005
Parameter
Symbol
Conditions
SOURCE = 0 V; TJ = 0 to 100 °C
(Unless Otherwise Specified)
DCMAX
See Notes D, E
Min
Typ
Max
Units
Control Functions (cont.)
Maximum Duty Cycle
TJ = 25 °C
FEEDBACK Pin Voltage
VFB(TH)
CBP = 1 mF
TJ = 100 °C
See Note E
FEEDBACK Pin Voltage at
Turn-Off Threshold
VFB(AR)
Minimum Switch
ON-Time
tON(MIN)
See Note E
FEEDBACK Pin
Sampling Delay
tFB
TJ = 25 °C
IS1
FB Voltage > VFBth
(MOSFET Not Switching)
DRAIN Pin
Supply Current
IS2
ICH1
FB Voltage = VFBth
-0.1 V,
Switch ON-Time =
tON (MOSFET
Switching at fOSC)
VBP = 0 V
BYPASS Pin
Charge Current
ICH2
VBP = 4 V
55
%
1.915
1.940
1.965
1.90
1.94
1.98
0.69
0.75
0.81
700
2.35
V
V
ns
2.55
2.75
ms
320
370
mA
LYT2002
500
560
LYT2003
550
600
LYT2004
600
680
LYT2005
700
800
LYT2002
-7.0
-4.8
-2.5
LYT2003
-7.2
-5.8
-3.2
LYT2004
-8.5
-6.3
-3.2
LYT2005
-8.5
-6.3
-3.2
LYT2002
-5.6
-3.2
-1.4
LYT2003
-5.6
-4.0
-2.0
LYT2004
-6.0
-4.4
-2.0
LYT2005
-6.0
-4.4
-2.0
mA
mA
BYPASS Pin
Voltage
VBP
5.65
5.9
6.25
V
BYPASS Pin
Voltage Hysteresis
VBPH
0.70
0.95
1.20
V
VSHUNT
6.2
6.4
6.8
V
BYPASS Pin
Shunt Voltage
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Rev. B 09/15
LYT2002-2005
Parameter
Symbol
Conditions
SOURCE = 0 V; TJ = 0 to 100 °C
(Unless Otherwise Specified)
Min
Typ
Max
LYT2002D
di/dt = 80 mA/ms
293
315
337
LYT2003D
di/dt = 100 mA/ms
363
390
417
LYT2004D
di/dt = 105 mA/ms
390
420
450
LYT2004E/K
di/dt = 125 mA/ms
460
495
530
LYT2005E/K
di/dt = 135 mA/ms
511
550
589
Units
Circuit Protection
Current Limit
Minimum Current Limit
Scale Factor
Normalized Output
Current
ILIMIT
VBP = 5.9 V
TJ = 25 °C
ILIMIT(MIN)
TJ = 25 °C
0.28
0.32
0.39
IO
TJ = 25 °C
0.975
1.000
1.025
170
215
135
142
TJ = 25 °C
Leading Edge
Blanking Time
tLED
Thermal Shutdown
Temperature
TSD
See Note E
Thermal Shutdown
Hysteresis
TSDH
See Note E
See Note E
mA
ns
150
60
°C
°C
Output
LYT2002D
ID = 63 mA
LYT2003D
ID = 78 mA
ON-State
Resistance
RDS(ON)
LYT2004D
ID = 84 mA
LYT2004E/K
ID = 99 mA
LYT2005E/K
ID = 110 mA
TJ = 25 °C
13
15.5
TJ = 100 °C
20
23.5
TJ = 25 °C
8
9.2
TJ = 100 °C
12
14
TJ = 25 °C
5
5.9
TJ = 100 °C
7.5
8.60
TJ = 25 °C
5
5.9
TJ = 100 °C
7.5
8.60
TJ = 25 °C
3.2
3.8
TJ = 100 °C
4.6
5.40
W
10
Rev. B 09/15
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LYT2002-2005
Parameter
Symbol
Conditions
SOURCE = 0 V; TJ = 0 to 100 °C
(Unless Otherwise Specified)
Min
Typ
Max
Units
Output (cont.)
OFF-State
Leakage
IDSS1
IDSS2
Breakdown
Voltage
BVDSS
VDS = 560 V
50
TJ = 125 °C, See Note C
V
DS
mA
= 375 V
15
TJ = 50 °C
TJ = 25 °C
DRAIN Pin
Supply Voltage
725
V
50
V
100
ms
0.32
s
Auto-Restart
ON-Time
t AR-ON
tON × IFB = 1.4 mAms
fOSC = 12 kHz
VFB = 0
See Notes A, E
Auto-Restart
OFF-Time
t AR-OFF
See Note E
IOL
See Note E
-45
mA
See Note E
1.4
ms
Open-Loop
FEEDBACK Pin
Current Threshold
Open-Loop
ON-Time
NOTES:
A. Auto-restart on-time is a function of switching frequency programmed by tonx IFB and minimum frequency in CC mode.
B. The current limit threshold is compensated to cancel the effect of current limit delay. As a result the output current stays constant across
the input line range.
C. IDSS1 is the worst-case off-state leakage specification at 80% of BVDSS and maximum operating junction temperature. IDSS2 is a typical
specification under worst-case application conditions (rectified 265 VAC) for no-load consumption calculations.
D. When the duty cycle exceeds DCMAX the LYTSwitch-2 operates in on-time extension mode.
E. This parameter is derived from characterization.
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Rev. B 09/15
LYT2002-2005
Typical Performance Characteristics
0.800
0.600
0.400
0.200
0.85
-40
-15
10
35
60
85
1.000
0.800
0.600
0.400
0.200
0.85
-40
110 135
PI-7291-050214
Current Limit
(Normalized to 25 °C)
1.000
1.200
Output Frequency
(Normalized to 25 °C)
PI-7290-050114
1.200
-15
Temperature (°C)
1.000
0.800
0.600
0.400
0.200
10
35
60
85
0.800
0.600
0.400
0.200
-15
0.800
0.600
0.400
0.200
35
60
85
Temperature (°C)
Figure 14. Feedback Voltage vs. Temperature.
35
60
85
110 135
110 135
Figure 13. Frequency Ratio vs. Temperature (Inductor Current).
PI-7289-050114
1.200
Normalized Output Current
(Normalized to 25 °C)
1.000
10
Temperature (°C)
PI-5089-040508
Feedback Voltage
(Normalized to 25 °C)
1.200
10
110 135
1.000
0.000
-40
110 135
Figure 12. Frequency Ratio vs. Temperature (Constant Current).
-15
85
1.200
Temperature (°C)
0.000
-40
60
PI-5088-040508
PI-5087-040508
Frequency Ratio
(Normalized to 25 °C)
1.200
-15
35
Figure 11. Output Frequency vs. Temperature.
Frequency Ratio
(Normalized to 25 °C)
Figure 10. Current Limit vs. Temperature.
0.000
-40
10
Temperature (°C)
1.000
0.800
0.600
0.400
0.200
0.000
-40
-15
10
35
60
85
110 135
Temperature (°C)
Figure 15. Normalized Output Current vs. Temperature.
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Rev. B 09/15
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LYT2002-2005
1.0
300
TCASE=25 °C
TCASE=100 °C
250
Drain Current (mA)
PI-2213-012301
200
150
100
Scaling Factors:
LYT2002 1.5
LYT2003 2.6
LYT2004 4.1
LYT2005 6.7
50
0.9
-50 -25
0
0
25
50
0
75 100 125 150
2
30
PI-7287-091715
10
Scaling Factors:
LYT2002 1.5
LYT2003 2.6
LYT2004 4.1
LYT2005 6.7
25
Power (mW)
Drain Capacitance (pF)
8
10
Figure 17. Output Characteristic.
Scaling Factors:
LYT2002 1.5
LYT2003 2.6
LYT2004 4.1
LYT2005 6.7
100
6
DRAIN Voltage (V)
Junction Temperature (°C)
Figure 16. Breakdown vs. Temperature.
1000
4
PI-7286-091715
Breakdown Voltage
(Normalized to 25 °C)
1.1
PI-7285-091715
Typical Performance Characteristics
20
15
10
5
1
0
0
100
200
300
400
Drain Voltage (V)
Figure 18. COSS vs. Drain Voltage.
500
600
0
100
200
300
400
500
600
DRAIN Voltage (V)
Figure 19. Drain Capacitance Power.
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Rev. B 09/15
LYT2002-2005
SO-8C (D Package)
4
B
0.10 (0.004) C A-B 2X
2
DETAIL A
4.90 (0.193) BSC
A
4
8
D
5
2 3.90 (0.154) BSC
GAUGE
PLANE
SEATING
PLANE
6.00 (0.236) BSC
0-8
C
1.04 (0.041) REF
2X
0.10 (0.004) C D
Pin 1 ID
1
4
1.35 (0.053)
1.75 (0.069)
0.25 (0.010)
BSC
0.40 (0.016)
1.27 (0.050)
0.20 (0.008) C
2X
7X 0.31 - 0.51 (0.012 - 0.020)
0.25 (0.010) M C A-B D
1.27 (0.050) BSC
o
1.25 - 1.65
(0.049 - 0.065)
DETAIL A
0.10 (0.004)
0.25 (0.010)
7X
0.10 (0.004) C
H
SEATING PLANE
C
Reference
Solder Pad
Dimensions
+
2.00 (0.079)
+
D07C
0.17 (0.007)
0.25 (0.010)
1.27 (0.050)
4.90 (0.193)
+
+
0.60 (0.024)
Notes:
1. JEDEC reference: MS-012.
2. Package outline exclusive of mold flash and metal burr.
3. Package outline inclusive of plating thickness.
4. Datums A and B to be determined at datum plane H.
5. Controlling dimensions are in millimeters. Inch dimensions
are shown in parenthesis. Angles in degrees.
PI-4526-040110
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Rev. B 09/15
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LYT2002-2005
eSIP-7C (E Package)
C
2
0.403 (10.24)
0.397 (10.08)
A
0.264 (6.70)
Ref.
0.081 (2.06)
0.077 (1.96)
B
Detail A
2
0.290 (7.37)
Ref.
0.519 (13.18)
Ref.
0.325 (8.25)
0.320 (8.13)
Pin #1
I.D.
0.140 (3.56)
0.120 (3.05)
3
0.207 (5.26)
0.187 (4.75)
0.016 (0.41)
Ref.
3
0.047 (1.19)
0.070 (1.78) Ref.
0.050 (1.27)
0.198 (5.04) Ref.
0.016 (0.41) 6×
0.011 (0.28)
0.020 M 0.51 M C
FRONT VIEW
0.118 (3.00)
SIDE VIEW
4
0.033 (0.84) 6×
0.028 (0.71)
0.010 M 0.25 M C A B
0.100 (2.54)
BACK VIEW
0.100 (2.54)
10° Ref.
All Around
0.021 (0.53)
0.019 (0.48)
0.050 (1.27)
0.020 (0.50)
0.060 (1.52)
Ref.
0.050 (1.27)
PIN 1
0.378 (9.60)
Ref.
0.048 (1.22)
0.046 (1.17)
0.019 (0.48) Ref.
0.059 (1.50)
0.155 (3.93)
0.023 (0.58)
END VIEW
PIN 7
0.027 (0.70)
0.059 (1.50)
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions noted are determined at the outermost
extremes of the plastic body exclusive of mold flash,
tie bar burrs, gate burrs, and interlead flash, but including
any mismatch between the top and bottom of the plastic
body. Maximum mold protrusion is 0.007 [0.18] per side.
DETAIL A
0.100 (2.54)
0.100 (2.54)
MOUNTING HOLE PATTERN
(not to scale)
3. Dimensions noted are inclusive of plating thickness.
4. Does not include inter-lead flash or protrusions.
5. Controlling dimensions in inches (mm).
PI-4917-061510
15
www.power.com
Rev. B 09/15
LYT2002-2005
eSOP-12B (K Package)
0.356 [9.04]
Ref.
0.004 [0.10] C A 2X
2
0.400 [10.16]
Pin #1 I.D.
(Laser Marked)
0.325 [8.26]
Max. 7
2X
7
0.004 [0.10] C B
0.059 [1.50]
Ref, Typ
0.460 [11.68]
0.059 [1.50]
Ref, Typ
0.008 [0.20] C 1
2X, 5/6 Lead Tips
2
3
4
6
H
4
0.010 [0.25]
12
Gauge Plane
2
Seating Plane
0°- 8°
0.225 [5.72]
Max. 7
0.034 [0.85]
0.026 [0.65]
6
1
0.120 [3.05] Ref
BOTTOM VIEW
0.020 [0.51]
Ref.
0.092 [2.34]
0.086 [2.18]
0.032 [0.80]
0.029 [0.72]
0.006 [0.15]
0.000 [0.00]
Seating plane to
package bottom
standoff
0.004 [0.10] C
C
Seating
Plane
Detail A
0.217 [5.51]
0.022 [0.56]
Ref.
0.016 [0.41]
0.011 [0.28]
11×
END VIEW
Land Pattern
Dimensions
1
12
2
11
3
10
0.028 [0.71]
0.321 [8.15]
9
4
3
0.019 [0.48]
Ref.
0.306 [7.77]
Ref.
SIDE VIEW
0.067 [1.70]
0.049 [1.23]
0.046 [1.16]
0.028 [0.71]
Ref.
0.070 [1.78]
TOP VIEW
0.098 [2.49]
0.086 [2.18]
C
DETAIL A (Scale = 9X)
B
3
0.055 [1.40] Ref.
0.350 [8.89]
0.023 [0.58]
11×
0.018 [0.46]
0.010 (0.25) M C A B
0.010 [0.25]
Ref.
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions noted are determined at the outermost
extremes of the plastic body exclusive of mold flash,
tie bar burrs, gate burrs, and interlead flash, but
including any mismatch between the top and bottom of
the plastic body. Maximum mold protrusion is 0.007
[0.18] per side.
3. Dimensions noted are inclusive of plating thickness.
4. Does not include interlead flash or protrusions.
5. Controlling dimensions in inches [mm].
6
0.429 [10.90]
8
6. Datums A and B to be determined at Datum H.
7
7. Exposed pad is nominally located at the centerline of
Datums A and B. “Max” dimensions noted include both
size and positional tolerances.
PI-5748a-100311
16
Rev. B 09/15
www.power.com
LYT2002-2005
Part Ordering Information
• LYTSwitch Product Family
• 2 Series Number
• Package Identifier
D
SO-8C
E
eSIP-7C
K
eSOP-12B
• Tape & Reel and Other Options
Blank
LYT 2002 D - TL
TL
Standard Configuration
Tape & Reel, 2.5 k pcs for D package, 1 k pcs for K package
17
www.power.com
Rev. B 09/15
Revision Notes
Date
A
Code A.
05/19/14
A
Updated Figure 2.
06/12/14
A
Updated VFB(TH) parameter table information.
12/08/14
B
Removed LYT2001D part number from data sheet.
09/15
For the latest updates, visit our website: www.power.com
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations
does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY
HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.
Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one
or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of
Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set
forth at http://www.power.com/ip.htm.
Life Support Policy
POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:
1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose
failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or
death to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or effectiveness.
The PI logo, TOPSwitch, TinySwitch, LinkSwitch, LYTSwitch, InnoSwitch, DPA-Switch, PeakSwitch, CAPZero, SENZero, LinkZero, HiperPFS,
HiperTFS, HiperLCS, Qspeed, EcoSmart, Clampless, E-Shield, Filterfuse, FluxLink, StakFET, PI Expert and PI FACTS are trademarks of Power
Integrations, Inc. Other trademarks are property of their respective companies. ©2015, Power Integrations, Inc.
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