TOP209/210
TOPSwitch Family
Three-terminal Off-line PWM Switch
Product Highlights
Cost Effective Switcher for Low Power Applications
• Replaces linear power supplies
• Replaces discrete switcher and 20 to 50 components
– cuts cost, increases reliability
• Stand-by power supplies for Green or energy efficient
products such as personal computers, monitors, UPS,
copiers, fax machines, etc.
• Housekeeping or "keep-alive" power supply applications
such as TV, appliances, industrial control and personal
computers
• Meets 'Blue Angel' low power stand-by specification
• Controlled MOSFET turn-on reduces EMI and EMI filter
costs
• 80% smaller and lighter compared to linear supply
• 50% smaller compared to discrete switcher
Over 80% Efficiency in Flyback Topology
• Built-in start-up and current limit reduce DC losses
• Low capacitance 700 V MOSFET cuts AC losses
• CMOS controller/gate driver consumes only 6 mW
• 70% maximum duty cycle minimizes conduction losses
Simplifies Design – Reduces Time to Market
• Supported by reference design boards
• Integrated PWM Controller and 700 V MOSFET in
industry standard eight pin DIP package
• Only one external capacitor needed for compensation,
bypass and start-up/auto-restart functions
• Easily interfaces with both opto and primary feedback
+
Wide-Range
DC Input
D
CONTROL
TOPSwitch
C
S
-
PI-2043-052397
Figure 1. Typical Application.
TOPSwitch Selection Guide
OUTPUT POWER RANGE
ORDER
PART
NUMBER
PACKAGE
TOP209P
DIP-8
TOP209G
SMD-8
TOP210PFI
DIP-8
TOP210G
SMD-8
230 VAC or
110 VAC
w/Doubler
85-265
VAC
0-4 W
0-2 W
0-8 W
0-5 W
System Level Fault Protection Features
• Auto-restart and cycle-by-cycle current limiting functions
handle both primary and secondary faults
• On-chip thermal shutdown with hysteresis protects the
entire system against overload
Description
The TOP209/210 implements all functions necessary for an
off-line switched mode control system: high voltage N-channel
power MOSFET with controlled turn-on gate driver, voltage
mode PWM controller with integrated oscillator, high voltage
start-up bias circuit, bandgap derived reference, bias shunt
regulator/error amplifier for loop compensation and fault
protection circuitry. Compared to discrete MOSFET and
controller or self oscillating (RCC) switching converter
solutions, a TOPSwitch integrated circuit can reduce total
cost, component count, size, weight and at the same time
increase efficiency and system reliability. The TOP209/210 are
intended for 100/110/230 VAC off-line Power Supply
applications in the 0 to 8 W (0 to 5 W universal) range.
TM
August 2016
TOP209/210
VC
0
CONTROL
DRAIN
ZC
SHUTDOWN/
AUTO-RESTART
SHUNT REGULATOR/
ERROR AMPLIFIER
+
+
1
5.7 V
4.7 V
-
INTERNAL
SUPPLY
÷8
5.7 V
POWER-UP
RESET
+
-
VI
LIMIT
IFB
THERMAL
SHUTDOWN
WITH
HYSTERESIS
CONTROLLED
TURN-ON
GATE
DRIVER
OSCILLATOR
DMAX
CLOCK
SAW
-
S
Q
+
R
Q
LEADING
EDGE
BLANKING
PWM
COMPARATOR
MINIMUM
ON-TIME
DELAY
RE
SOURCE
PI-1742-011796
Figure 2. Functional Block Diagram.
Pin Functional Description
2
DRAIN Pin:
Output MOSFET drain connection. Provides internal bias
current during start-up operation via an internal switched highvoltage current source. Internal current sense point.
CONTROL Pin:
Error amplifier and feedback current input pin for duty cycle
control. Internal shunt regulator connection to provide internal
bias current during normal operation. It is also used as the
supply bypass and auto-restart/compensation capacitor
connection point.
SOURCE Pin:
Control circuit common, internally connected to output
MOSFET source.
SOURCE (HV RTN) Pin:
Output MOSFET source connection for high voltage return.
2
SOURCE 1
8
SOURCE (HV RTN)
N/C 2
7
N/C
N/C 3
6
N/C
CONTROL 4
5
DRAIN
P Package (DIP-8)
G Package (SMD-8)
PI—2044-040901
Figure 3. Pin Configuration.
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TOP209/210
TOPSwitch Family Functional Description
During normal operation, the internal
output MOSFET duty cycle linearly
decreases with increasing CONTROL
pin current as shown in Figure 4. To
implement all the required control, bias,
and protection functions, the DRAIN
and CONTROL pins each perform
several functions as described below.
Refer to Figure 2 for a block diagram
and Figure 6 for timing and voltage
waveforms of the TOPSwitch integrated
circuit.
Control Voltage Supply
CONTROL pin voltage VC is the supply
or bias voltage for the controller and
driver circuitry. An external bypass
capacitor closely connected between the
CONTROL and SOURCE pins is
required to supply the gate drive current.
The total amount of capacitance
connected to this pin (CT) also sets the
auto-restart timing as well as control
loop compensation. VC is regulated in
either of two modes of operation.
Hysteretic regulation is used for initial
start-up and overload operation. Shunt
regulation is used to separate the duty
cycle error signal from the control circuit
supply current. During start-up, VC
current is supplied from a high-voltage
switched current source connected
internally between the DRAIN and
CONTROL pins. The current source
provides sufficient current to supply the
control circuitry as well as charge the
total external capacitance (CT).
Auto-restart
IB
DMAX
Slope = PWM Gain
-16%/mA
Duty Cycle (%)
TOPSwitch is a self biased and protected
linear control current-to-duty cycle
converter with an open drain output.
High efficiency is achieved through the
use of CMOS and integration of the
maximum number of functions possible.
CMOS significantly reduces bias
currents as compared to bipolar or
discrete solutions. Integration eliminates
external power resistors used for current
sensing and/or supplying initial start-up
bias current.
DMIN
ICD1 2.5
6.5
IC (mA)
PI-2047-060497
Figure 4. Relationship of Duty Cycle to CONTROL Pin Current.
VC
5.7 V
4.7 V
IC
Charging CT
0
DRAIN
VIN
Off
0
Switching
(a)
IC
Charging CT
VC
ICD2
Discharging CT
ICD1
Discharging CT
5.7 V
4.7 V
8 Cycles
0
95%
DRAIN
VIN
Off
5%
Off
Off
0
Switching
Switching
(b)
CT is the total external capacitance
connected to the CONTROL pin
PI-1124A-060694
Figure 5. Start-up Waveforms for (a) Normal Operation and (b) Auto-restart.
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3
TOP209/210
TOPSwitch Family Functional Description (cont.)
The first time VC reaches the upper threshold, the high-voltage
current source is turned off and the PWM modulator and output
transistor are activated, as shown in Figure 5(a). During normal
operation (when the output voltage is regulated) feedback
control current supplies the VC supply current. The shunt
regulator keeps VC at typically 5.7 V by shunting CONTROL
pin feedback current exceeding the required DC supply current
through the PWM error signal sense resistor RE. The low
dynamic impedance of this pin (ZC) sets the gain of the error
amplifier when used in a primary feedback configuration. The
dynamic impedance of the CONTROL pin together with the
external resistance and capacitance determines the control loop
compensation of the power system.
If the CONTROL pin external capacitance (CT) should discharge
to the lower threshold, then the output MOSFET is turned off
and the control circuit is placed in a low-current standby mode.
The high-voltage current source is turned on and charges the
external capacitance again. Charging current is shown with a
negative polarity and discharging current is shown with a
positive polarity in Figure 6. The hysteretic auto-restart
comparator keeps VC within a window of typically 4.7 to 5.7 V
by turning the high-voltage current source on and off as shown
in Figure 5(b). The auto-restart circuit has a divide-by-8
counter which prevents the output MOSFET from turning on
again until eight discharge-charge cycles have elapsed. The
counter effectively limits TOPSwitch power dissipation by
reducing the auto-restart duty cycle to typically 5%. Autorestart continues to cycle until output voltage regulation is
again achieved.
2
Bandgap Reference
All critical TOPSwitch internal voltages are derived from a
temperature-compensated bandgap reference. This reference
is also used to generate a temperature-compensated current
source which is trimmed to accurately set the oscillator frequency
and MOSFET gate drive current.
Oscillator
The internal oscillator linearly charges and discharges the
internal capacitance between two voltage levels to create a
sawtooth waveform for the pulse width modulator. The oscillator
sets the pulse width modulator/current limit latch at the beginning
of each cycle. The nominal frequency of 100 kHz was chosen
to minimize EMI and maximize efficiency in power supply
applications. Trimming of the current reference improves
oscillator frequency accuracy.
Pulse Width Modulator
The pulse width modulator implements a voltage-mode control
4
loop by driving the output MOSFET with a duty cycle inversely
proportional to the current flowing into the CONTROL pin.
The error signal across RE is filtered by an RC network with a
typical corner frequency of 7 kHz to reduce the effect of
switching noise. The filtered error signal is compared with the
internal oscillator sawtooth waveform to generate the duty
cycle waveform. As the control current increases, the duty
cycle decreases. A clock signal from the oscillator sets a latch
which turns on the output MOSFET. The pulse width modulator
resets the latch, turning off the output MOSFET. The maximum
duty cycle is set by the symmetry of the internal oscillator. The
modulator has a minimum ON-time to keep the current
consumption of the TOPSwitch independent of the error signal.
Note that a minimum current must be driven into the CONTROL
pin before the duty cycle begins to change.
Gate Driver
The gate driver is designed to turn the output MOSFET on at a
controlled rate to minimize common-mode EMI. The gate drive
current is trimmed for improved accuracy.
Error Amplifier
The shunt regulator can also perform the function of an error
amplifier in primary feedback applications. The shunt regulator
voltage is accurately derived from the temperature compensated
bandgap reference. The gain of the error amplifier is set by the
CONTROL pin dynamic impedance. The CONTROL pin
clamps external circuit signals to the VC voltage level. The
CONTROL pin current in excess of the supply current is
separated by the shunt regulator and flows through RE as the
error signal.
Cycle-By-Cycle Current Limit
The cycle by cycle peak drain current limit circuit uses the
output MOSFET ON-resistance as a sense resistor. A current
limit comparator compares the output MOSFET ON-state drainsource voltage, VDS(ON), with a threshold voltage. High drain
current causes VDS(ON) to exceed the threshold voltage and turns
the output MOSFET off until the start of the next clock cycle.
The current limit comparator threshold voltage is temperature
compensated to minimize variation of the effective peak current
limit due to temperature related changes in output MOSFET
RDS(ON).
The leading edge blanking circuit inhibits the current limit
comparator for a short time after the output MOSFET is turned
on. The leading edge blanking time has been set so that current
spikes caused by primary-side capacitances and secondary-side
rectifier reverse recovery time will not cause premature
termination of the switching pulse.
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TOP209/210
VIN
VIN
DRAIN
0
VOUT
0
IOUT
0
1
2
8
1
2
•••
VC
8
1
8
1
•••
0
1
IC
2
8
1
•••
0
1
2
•••
2
1
PI-1742-011796
Figure 6. Typical Waveforms for (1) Normal Operation, (2) Auto-restart.
Shutdown/Auto-restart
To minimize TOPSwitch power dissipation, the shutdown/
auto-restart circuit turns the power supply on and off at a duty
cycle of typically 5% if an out of regulation condition persists.
Loss of regulation interrupts the external current into the
CONTROL pin. VC regulation changes from shunt mode to the
hysteretic auto-restart mode described above. When the fault
condition is removed, the power supply output becomes
regulated, VC regulation returns to shunt mode, and normal
operation of the power supply resumes.
Hysteretic Overtemperature Protection
Temperature protection is provided by a precision analog
circuit that turns the output MOSFET off when the junction
temperature exceeds the thermal shutdown temperature
(typically 145 °C). When the junction temperature cools past
the hysteresis temperature, normal operation resumes. VC is
regulated in hysteretic mode while the power supply is turned
off.
High-voltage Bias Current Source
This current source biases TOPSwitch from the DRAIN pin and
charges the CONTROL pin external capacitance (CT) during
start-up or hysteretic operation. The current source is switched
on and off with an effective duty cycle of approximately 35%.
This duty cycle is determined by the ratio of CONTROL pin
charge (IC) and discharge currents (ICD1 and ICD2). This current
source is turned off during normal operation when the output
MOSFET is switching.
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5
TOP209/210
General Circuit Description
Figure 7 shows a low-cost, DC input, flyback switching power
supply using the TOP210 integrated circuit. This 5 V, 4 W
power supply operates from a DC voltage derived from rectified
and filtered AC mains voltage of 85 to 265 VAC. The 5 V
output is indirectly sensed via the primary bias winding. The
output voltage is determined by the TOPSwitch CONTROL pin
shunt regulator voltage (VC), the voltage drops of rectifiers D2
and D3, and the turns ratio between the bias winding and output
winding of T1. Other output voltages are also possible by
adjusting the transformer turns ratios.
The high voltage DC bus is applied to the primary winding of
T1. Capacitor C1 filters the high voltage supply, and is only
necessary if the connections between the high voltage DC
supply and the TOP210 are long. The other side of the
transformer primary is driven by the integrated high-voltage
MOSFET within the TOP210. D1 and VR1 clamp the voltage
spike caused by transformer leakage inductance to a safe value
and reduce ringing at the DRAIN of U1. The power secondary
winding is rectified and filtered by D2, C2, L1, and C3 to create
the 5V output voltage. The bias winding is rectified and filtered
by D3, R1 and C5 to create a bias voltage to the TOP210. C5
also filters internal MOSFET gate drive charge current spikes
on the CONTROL pin, determines the auto-restart frequency,
and together with R1, compensates the control loop.
D2
1N5822
1
L1
3.3 µH
+5 V
8
+
VR1
BZY97C120
120 V
C2
330 µF
10 V
C3
100 µF
10 V
5
D1
UF4005
D3
1N4148
2
DC
INPUT
4
C1
10 nF
400 V
3
T1
D
TOPSwitch
S
R1
15 Ω
TRD1
CONTROL
2
RTN
U1
TOP210
C
C5
47 µF
10 V
-
CIRCUIT PERFORMANCE:
Line Regulation - –1.5%
(104-370 VDC)
Load Regulation - –5%
(10-100%)
Ripple Voltage –25 mV
PI-2045-041798
Figure 7. Schematic Diagram of a Minimum Parts Count 5 V, 4 W Bias Supply Using the TOP210.
6
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TOP209/210
1
+
BR1
DFO6M
C1
10 µF
200 V
RA
470 kΩ
-
T1
T1RD2
VR1
BZY97-C200
JP1*
JUMPER
D2
MBR360
8
D1
UF4005
L2
12 mH min.
0.2A
F1
2A
C9
10 µF
200 V
D
TOPSwitch
CONTROL
S
C
U1
TOP210
C2
330 µF
16 V
R1
6.8 Ω
3
D3
1N4148
C5
47 µF
10 V
C6
47nF
250VAC
X2
4
L
N
J1
* JPI INSTALLED FOR 110 VAC INPUT
JPI OPEN FOR 220 VAC INPUT
12 V
3 µH
2
RB
470 kΩ
L1
C3
120 µF
16 V
R2
330
1W
5
RTN
CIRCUIT PERFORMANCE:
Line Regulation - –1%
(85-132 VAC) or
(170-265 VAC)
Load Regulation - –5%
(10-100%)
Ripple Voltage – 50 mV
Meets CISPR-22 Class B
C7
1nF
250 VAC
Y1
PI-2046-052397
Figure 8. Schematic Diagram of a 12 V, 8 W 110/220 VAC Input Power Supply Using the TOP210.
The circuit shown in Figure 8 produces a 12 V, 8 W power
supply that operates from 85 to 132 VAC or 170 to 264 VAC
input voltage. The 12 V output voltage is determined by the
TOPSwitch CONTROL pin shunt regulator voltage, the voltage
drops of D2 and D3, and the turns ratio between the bias and
output windings of T1. Other output voltages are also possible
by adjusting the transformer turns ratios. R1 and C5 provide
filtering of the bias winding to improve line and load regulation.
AC power is rectified and filtered by BR1, C1 and C9 to create
the high voltage DC bus applied to the primary winding of T1.
The other side of the transformer primary is driven by the
integrated high-voltage MOSFET within the TOP210. JP1 is a
jumper used to select 110 VAC or 220 VAC operation. Installing
JP1 selects 110 VAC operation. Leaving JP1 open selects
220 VAC operation. RA and RB, which equalize voltage across
C1 and C9, are necessary only when JP1 is not installed. D1 and
VR1 clamp the leading-edge voltage spike caused by transformer
leakage inductance to a safe value and reduce ringing. The
power secondary winding is rectified and filtered by D2, C2,
L1, and C3 to create the 12 V output voltage. R2 provides a preload on the 12 V output to improve load regulation at light loads.
The bias winding is rectified and filtered by D3, R1, and C5 to
create a bias voltage to the TOP210. L2 and Y1-capacitor C7
attenuate common-mode emission currents caused by highvoltage switching waveforms on the DRAIN side of the primary
winding and the primary to secondary capacitance. L2 and C6
attenuate differential-mode emission currents caused by the
fundamental and harmonics of the trapezoidal primary current
waveform. C5 filters internal MOSFET gate drive charge
current spikes on the CONTROL pin, determines the autorestart frequency, and together with R1, compensates the control
loop.
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7
TOP209/210
Key Application Considerations
Use a Kelvin connection to the SOURCE pin for the CONTROL
pin bypass capacitor as shown in Figure 9.
Minimize peak voltage and ringing on the DRAIN voltage at
turn-off. Use a Zener or TVS Zener diode to clamp the DRAIN
voltage.
Under some conditions, externally provided bias or supply
current driven into the CONTROL pin can hold the TOPSwitch
in one of the 8 auto-restart cycles indefinitely and prevent
starting. Shorting the CONTROL pin to the SOURCE pin will
reset the TOPSwitch. To avoid this problem when doing bench
evaluations, it is recommended that the VC power supply be
turned on before the DRAIN voltage is applied.
CONTROL pin currents during auto-restart operation are much
lower at low input voltages (< 20 V) which increases the autorestart cycle period (see the IC vs. Drain Voltage Characteristic
curve).
Short interruptions of AC power may cause TOPSwitch to enter
the 8-count auto-restart cycle before starting again. This is
because the input energy storage capacitors are not completely
discharged and the CONTROL pin capacitance has not
discharged below the internal power-up reset voltage (VC(RESET)).
In some cases, minimum loading may be necessary to keep a
lightly loaded or unloaded output voltage within the desired
range due to the minimum ON-time.
For additional applications information regarding the TOPSwitch
family, refer to AN-14 in the 1996-97 Data Book and Design
Guide or on our Web site.
SOURCE
TOP210 PFI
High Voltage
Return
SOURCE
Bias/Feedback
Return
Bias/Feedback
Input
CONTROL
DRAIN
Bypass
Capacitor
TOP VIEW
PI-1744-011796
Figure 9. Recommended PC Layout for the TOP209/210.
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TOP209/210
ABSOLUTE MAXIMUM RATINGS(1)
DRAIN Voltage ........................................... - 0.3 to 700 V
CONTROL Voltage ..................................... - 0.3 V to 9 V
CONTROL Current ............................................... 100 mA
Storage Temperature ..................................... -65 to 150 °C
Operating Junction Temperature(2) ................ -40 to 150 °C
Lead Temperature(3) ................................................ 260 °C
Thermal Impedance (θJA) ................................... 100 °C/W
Thermal Impedance (θJC) ..................................... 40 °C/W
1. Unless noted, all voltages referenced to SOURCE,
TA = 25 °C.
2. Normally limited by internal circuitry.
3. 1/16" from case for 5 seconds.
Conditions
Parameter
Symbol
(Unless Otherwise Specified)
See Figure 12
SOURCE = 0 V
TJ = -40 to 125 °C
Min
Typ
Max
TOP209
55
70
85
TOP210
90
100
110
64
67
70
Units
CONTROL FUNCTIONS
Output
Frequency
fOSC
Maximum
Duty Cycle
DMAX
Minimum
Duty Cycle
DMIN
IC = 4 mA, TJ = 25 °C
IC = ICD1+ 0.5 mA, See Figure 10
IC = 10 mA
TOP209
0.5
1.5
2.5
See Figure 10
TOP210
1.0
1.8
3.0
-11
-16
-21
IC = 4 mA, TJ = 25 °C
PWM
Gain
See Figure 4
PWM Gain
Temperature Drift
See Note A
External
Bias Current
IB
Dynamic
Impedance
ZC
IC = 4 mA, TJ = 25 °C
See Figure 11
%
%
%/mA
%/mA/°C
-0.05
See Figure 4
kHz
1.5
2.5
4
mA
10
15
22
Ω
Dynamic Impedance
%/°C
0.18
Temperature Drift
SHUTDOWN/AUTO-RESTART
CONTROL Pin
Charging Current
IC
Charging Current
Temperature Drift
Auto-restart
Threshold Voltage
VC(AR)
TJ = 25 °C
VC = 0 V
-2.4
-1.9
-1.2
VC = 5 V
-2
-1.5
-0.8
mA
See Note A
0.4
%/°C
S1 open
5.7
V
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9
TOP209/210
Conditions
Parameter
Symbol
(Unless Otherwise Specified)
See Figure 12
SOURCE = 0 V
TJ = -40 to 125 °C
Min
Typ
Max
Units
5.0
V
SHUTDOWN/AUTO-RESTART (cont.)
UV Lockout
Threshold Voltage
S1 open
4.4
4.7
Auto-restart
Hysteresis Voltage
S1 open
0.6
1.0
Auto-restart
Duty Cycle
S1 open
5
Auto-restart
Frequency
S1 open
1.2
V
9
%
Hz
CIRCUIT PROTECTION
TOP209
0.150
0.230
TOP210
0.230
0.300
Self-protection
Current Limit
ILIMIT
Leading Edge
Blanking Time
tLEB
IC = 4 mA
150
ns
Current Limit
Delay
tILD
IC = 4 mA
100
ns
145
°C
30
°C
Thermal Shutdown
Temperature
di/dt = 40 mA/µs, TJ = 25 °C
IC = 4 mA
125
Thermal Shutdown
Hysteresis
Power-up Reset
Threshold Voltage
10
VC(RESET)
S2 open
2.0
3.3
4.2
A
V
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TOP209/210
Conditions
Parameter
Symbol
(Unless Otherwise Specified)
See Figure 12
SOURCE = 0 V
TJ = -40 to 125 °C
Min
Typ
Max
TJ = 25 °C
31.2
36.0
TJ = 100 °C
51.4
59.4
Units
OUTPUT
ON-State
Resistance
RDS(ON)
ID = 25 mA
See Note B
VDS = 560 V, TA = 125 °C
Ω
OFF-State
Current
IDSS
Breakdown
Voltage
BVDSS
See Note B, ID = 100 µA, TA = 25 °C
tR
Measured
100
ns
in a Typical
Flyback Converter Application
50
ns
Rise
Time
Fall
Time
tF
DRAIN Supply
Voltage
See Note C
250
µA
V
700
V
36
SUPPLY
Shunt Regulator
Voltage
VC(SHUNT)
IC = 4 mA
5.5
Shunt Regulator
Temperature Drift
CONTROL Supply/
Discharge Current
5.8
6.1
±50
ICD1
Output MOSFET Enabled
0.6
1.2
V
ppm/°C
1.6
mA
ICD2
Output MOSFET Disabled
0.5
0.8
1.1
NOTES:
A. For specifications with negative values, a negative temperature coefficient corresponds to an increase in magnitude
with increasing temperature, and a positive temperature coefficient corresponds to a decrease in magnitude with
increasing temperature.
B. The breakdown & leakage measurements can be accomplished by using the TOPSwitch auto-restart feature. The
divide-by-8 counter in the auto-restart circuitry disables the output MOSFET from switching in 7 out of 8 cycles. To
place the TOPSwitch in one of these cycles, the following procedure can be carried out using the modified circuit of
Figure 12:
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11
TOP209/210
NOTES: (continued)
i. The 470 Ω 5 W load resistor at the DRAIN pin should be shorted. S1 & S2 should stay closed.
ii. The 40 V output supply should be replaced with a curve tracer capable of forcing 700 V.
iii. The curve tracer should initially be set at 0 V. The 0-50 V variable supply should be adjusted through a voltage
sequence of 0 V, 6.5 V, 4.2 V, and 6.5 V.
iv. The breakdown and the leakage measurements can now be taken with the curve tracer. The maximum
voltage from the curve tracer must be limited to 700 V under all conditions.
C. It is possible to start up and operate TOPSwitch at DRAIN voltages well below 36 V. However, the CONTROL pin
charging current is reduced, which affects start-up time and auto-restart frequency and duty cycle. Refer to the
characteristic graph on CONTROL pin charge current (IC) vs. DRAIN voltage for low voltage operation characteristics.
TYPICAL CONTROL PIN I-V CHARACTERISTIC
t2
t1
HV
90%
90%
DRAIN
VOLTAGE
t
D= 1
t2
10%
0V
PI-1745-011796
CONTROL Pin Current (mA)
120
100
80
60
40
Dynamic
1
=
Impedance Slope
20
0
0
PI-2048-050798
Figure 10. TOPSwitch Duty Cycle Measurement.
2
6
8
10
CONTROL Pin Voltage (V)
Figure 11. TOPSwitch CONTROL Pin I-V Characteristic.
470 Ω
5W
D
4
S2
470 Ω
C
S1
S
S
0.1 µF
40 V
47 µF
0-50 V
NOTE: This test circuit is not applicable for current limit or output characteristic measurements.
PI-1733-122095
Figure 12. TOPSwitch General Test Circuit.
12
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TOP209/210
BENCH TEST PRECAUTIONS FOR EVALUATION OF ELECTRICAL CHARACTERISTICS
The following precautions should be followed when testing
TOPSwitch by itself outside a power supply. The schematic
shown in Figure 12 is suggested for laboratory testing of
TOPSwitch.
When the DRAIN supply is turned on, the part will be in the
auto-restart mode. The CONTROL pin voltage will be
oscillating at a low frequency from 4.7 to 5.7 V and the DRAIN
is turned on every eighth cycle of the CONTROL pin oscillation.
If the CONTROL pin power supply is turned on while in this
auto-restart mode, there is only a 12.5% chance that the
CONTROL pin oscillation will be in the correct state (DRAIN
active state) so that the continuous DRAIN voltage waveform
may be observed. It is recommended that the VC power supply
be turned on first and the DRAIN power supply second if
continuous DRAIN voltage waveforms are to be observed.
The 12.5% chance of being in the correct state is due to the 8:1
counter.
Typical Performance Characteristics
BREAKDOWN vs. TEMPERATURE
FREQUENCY vs. TEMPERATURE
PI-176B-051391
1.0
PI-1123A-060794
1.2
Output Frequency
(Normalized to 25 °C)
Breakdown Voltage (V)
(Normalized to 25 °C)
1.1
1.0
0.8
0.6
0.4
0.2
0.9
-50 -25
0
25
50
0
75 100 125 150
-50 -25
Junction Temperature (°C)
0
25
50
75 100 125 150
Junction Temperature (°C)
CURRENT LIMIT vs. TEMPERATURE
0.8
0.6
0.4
0.2
PI-2074-070897
1.0
IC vs. DRAIN VOLTAGE
2
CONTROL Pin
Charging Current (mA)
PI-1125-041494
Current Limit
(Normalized to 25 °C)
1.2
VC = 5 V
1.6
1.2
0.8
0.4
0
0
-50 -25
0
25
50
75 100 125 150
Junction Temperature (°C)
0
20
40
60
80
100
DRAIN Voltage (V)
B
8/16
www.power.com
13
TOP209/210
Typical Performance Characteristics (cont.)
COSS vs. DRAIN VOLTAGE
OUTPUT CHARACTERISTIC
200
150
100
50
0
0
2
4
6
8
PI-1730-121995
Drain Current (mA)
DRAIN Capacitance (pF)
TCASE=25 °C
TCASE=100 °C
250
100
PI-1734-011596
300
10
1
10
200
0
DRAIN Voltage (V)
400
600
DRAIN Voltage (V)
DRAIN CAPACITANCE POWER
PI-1731-121995
50
Power (mW)
40
30
20
10
0
0
200
400
600
DRAIN Voltage (V)
14
B
8/16
www.power.com
TOP209/210
PDIP-8 (P Package)
D S .004 (.
DIM
Inches
mm
A
B
C
G
H
J1
J2
K
L
M
N
P
Q
0.356-0.387
0.240-0.260
0.125-0.145
0.015-0.040
0.118-0.140
0.057-0.068
0.014-0.022
0.008-0.015
0.100 BSC
0.030 (MIN)
0.300-0.320
0.300-0.390
0.300 BSC
9.05-9.83
6.10-6.60
3.18-3.68
0.38-1.02
3.00-3.56
1.45-1.73
0.36-0.56
0.20-0.38
2.54 BSC
0.76 (MIN)
7.62-8.13
7.62-9.91
7.62 BSC
8
5
-E-
B
1
4
-D-
A
M
J1
Notes:
1. Package dimensions conform to JED
specification MS-001-AB for standard dual in-line
(DIP) package .300 inch row spacing (PLASTIC)
8 leads (issue B, 7/85).
2. Con olling dimensions are inches.
3. Dimensions shown do not include mold flas
or other protrusions. Mold flash or protrusions
G
shall not exceed .006 (.15) on any side.
4. D, E and F are reference datums on the molded
body.
L
N
C
-FH
K
Q
J2
P08A
P
PI-2076-081716
SMD-8 (G Package)
D S .004 (.
-E-
8
5
1
.420
.046 .060
.060 .046
.080
Pin 1
4
L
.086
.186
-D-
A
M
E S .010 (.
P
B
Inches
mm
A
B
C
G
H
J1
J2
J3
J4
K
L
M
P
α
0.356-0.387
0.240-0.260
0.125-0.145
0.004-0.012
0.036-0.044
0.057-0.068
0.048-0.053
0.032-0.037
0.007-0.011
0.010-0.012
0.100 BSC
0.030 (MIN)
0.372-0.388
0-8°
9.05-9.83
6.10-6.60
3.18-3.68
0.10-0.30
0.91-1.12
1.45-1.73
1.22-1.35
0.81-0.94
0.18-0.28
0.25-0.30
2.54 BSC
0.76 (MIN)
9.45-9.86
0-8°
.286
Solder Pad Dimensions
J1
C
K
-FJ3
G08A
DIM
J4
J2
.010 (.25) M A S
.004 (.10)
α
G
H
Notes:
1. Package dimensions conform to JED
specification MS-001-AB (issue B, 7/85)
except for lead shape and size.
2. Con olling dimensions are inches.
3. Dimensions shown do not include mold
flash or other protrusions. Mold flash or
protrusions shall not exceed .006 (.15) on
any side.
4. D, E and F are reference datums on the
molded body.
PI-2077-081716
B
8/16
www.power.com
15
Revision
Notes
Date
A
Release data sheet.
08/97
B
Updated PDIP-8 (P Package) and SMD-8 (G Package) per PCN-16232.
08/16
For the latest updates, visit our website: www.power.com
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power
Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS
MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD
PARTY RIGHTS.
Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be
covered by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power
Integrations. A complete list of Power Integrations patents may be found at www.power.com. Power Integrations grants its customers
a license under certain patent rights as set forth at http://www.power.com/ip.htm.
Life Support Policy
POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:
1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii)
whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in
significant injury or death to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its safety or effectiveness.
The PI logo, TOPSwitch, TinySwitch, SENZero, SCALE-iDriver, Qspeed, PeakSwitch, LYTSwitch, LinkZero, LinkSwitch, InnoSwitch,
HiperTFS, HiperPFS, HiperLCS, DPA-Switch, CAPZero, Clampless, EcoSmart, E-Shield, Filterfuse, FluxLink, StakFET, PI Expert and
PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©2016, Power
Integrations, Inc.
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