PCS3P625Z0xyG-08-TR

May 2008 rev 0.1 PCS3P625Z05B/C PCS3P625Z09B/C High Frequency Timing-Safe™ Peak EMI reduction IC General Features • • • High Frequency Clock distribution with TimingSafe™ Peak EMI Reduction Input frequency range: 100MHz - 175MHz Multiple low skew Timing-safe™ Outputs: PCS3P625Z05: 5 Outputs PCS3P625Z09: 9 Outputs • • • • External Input-Output Delay Control option Supply Voltage: 3.3V±0.3V Commercial and Industrial temperature range Packaging Information: ASM3P625Z05: 8 pin SOIC, and TSSOP ASM3P625Z09:16 pin SOIC, and TSSOP • True Drop-in Solution for Zero Delay Buffer, ASM5P2305A / 09A with Peak EMI reduction. PCS3P625Z05 is an eight-pin version, accepts one reference input and drives out five low-skew Timing-Safe™ clocks. PCS3P625Z09 accepts one reference input and drives out nine low-skew TimingSafe™clocks. PCS3P625Z05/09 has a DLY_CTRL for adjusting the Input-Output clock delay, depending upon the value of capacitor connected at this pin to GND. PCS3P625Z05/09 operates from a 3.3V supply and is available in two different packages, as shown in the ordering information table, over commercial and Industrial temperature range. Application PCS3P625Z05/09 is targeted for use in Displays and Functional Description PCS3P625Z05/09 is a versatile, 3.3V Zero-delay buffer designed to distribute high frequency Timing-Safe™ clocks memory interface systems. General Block Diagram PLL CLKIN DLY_CTRL CLKOUT1 CLKOUT2 CLKOUT3 CLKIN PLL MUX DLY_CTRL CLKOUTA1 CLKOUTA2 CLKOUTA3 CLKOUTA4 PCS3P625Z05B/C CLKOUT4 S2 S1 Select Input Decoding CLKOUTB1 CLKOUTB2 CLKOUTB3 PCS3P625Z05B/C CLKOUTB4 PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. May 2008 rev 0.1 Spread Spectrum Frequency Generation The clocks in digital systems are typically square waves with a 50% duty cycle and as frequencies increase the edge rates also get faster. Analysis shows that a square wave is composed of fundamental frequency and harmonics. The fundamental frequency and harmonics generate the energy peaks that become the source of EMI. Regulatory agencies test electronic equipment by measuring the amount of peak energy radiated from the equipment. In fact, the peak level allowed decreases as the frequency increases. The standard methods of reducing EMI are to use shielding, filtering, multi-layer PCS3P625Z05B/C PCS3P625Z09B/C PCBs etc. These methods are expensive. Spread spectrum clocking reduces the peak energy by reducing the Q factor of the clock. This is done by slowly modulating the clock frequency. The PCS3P625Z05/09 uses the center modulation spread spectrum technique in which the modulated output frequency varies above and below the reference frequency with a specified modulation rate. With center modulation, the average frequency is the same as the unmodulated frequency and there is no performance degradation Zero Delay and Skew Control All outputs should be uniformly loaded to achieve Zero Delay between input and output. Since the DLY_CTRL pin is the internal feedback to the PLL, its relative loading can adjust the input-output delay. For applications requiring zero input-output delay, all outputs, including DLY_CTRL, must be equally loaded. Even if DLY_CTRL is not used, it must have a capacitive load equal to that on other outputs, for obtaining zeroinput-output delay. Timing-Safe™ technology Timing-Safe™ technology is the ability to modulate a clock source with Spread Spectrum technology and maintain synchronization with any associated data path. High Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 2 of 15 May 2008 rev 0.1 Pin Configuration for PCS3P625Z05B/C PCS3P625Z05B/C PCS3P625Z09B/C CLKIN 1 CLKOUT1 2 PCS3P625Z05B/C CLKOUT2 3 GND 4 8 DLY_CTRL CLKOUT4 VDD CLKOUT3 7 6 5 Pin Description for PCS3P625Z05B/C Pin # 1 2 3 4 5 6 7 8 Pin Name CLKIN 1 2 Type I O O P O P O O Buffered clock output4 Buffered clock output4 Ground Buffered clock output4 3.3V supply Buffered clock output4 Description External reference Clock input, 5V tolerant input CLKOUT1 GND CLKOUT22 CLKOUT3 VDD CLKOUT4 2 2 DLY_CTRL External Input-Output Delay control. This pin can be used as clock output4 High Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 3 of 15 May 2008 rev 0.1 Pin Configuration for PCS3P625Z09B/C PCS3P625Z05B/C PCS3P625Z09B/C CLKIN 1 CLKOUTA1 2 CLKOUTA2 3 VDD 4 GND PCS3P625Z09B/C 5 16 15 14 13 12 11 10 9 DLY_CTRL CLKOUTA4 CLKOUTA3 VDD GND CLKOUTB4 CLKOUTB3 S1 CLKOUTB1 6 CLKOUTB2 7 S2 8 Pin Description for PCS3P625Z09B/C Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name CLKIN 1 2 Pin Type I O O P P Buffered clock Bank A output4 Buffered clock Bank A output4 3.3V supply Ground Buffered clock Bank B output4 Buffered clock Bank B output4 Description External reference Clock input, 5V tolerant input CLKOUTA1 VDD GND CLKOUTB1 S23 S1 3 CLKOUTA22 2 O O I I CLKOUTB22 Select input, bit 2.See Select Input Decoding table for PCS3P625Z09 for more details Select input, bit 1.See Select Input Decoding table for PCS3P625Z09 for more details Buffered clock Bank B output4 Buffered clock Bank B output4 Ground 3.3V supply Buffered clock Bank A output4 Buffered clock Bank A output4 CLKOUTB3 GND VDD CLKOUTA3 2 O O P P CLKOUTB42 2 O O O CLKOUTA42 DLY_CTRL2 External Input-Output Delay control. This pin can be used as clock output Notes: 1. Weak pull down 2. Weak pull-down on all outputs 3. Weak pull-up on these Inputs 4. Buffered clock output is Timing-Safe™ High Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 4 of 15 May 2008 rev 0.1 Select Input Decoding table for PCS3P625Z09 PCS3P625Z05B/C PCS3P625Z09B/C S2 0 0 1 1 S1 0 1 0 1 CLKOUT A1 - A4 CLKOUT B1 - B4 DLY_CTRL1 Output Source Three-state Driven Driven Driven Three-state Three-state Driven Driven Driven Driven Driven Driven PLL PLL Reference PLL PLL Shut-Down N N Y N Notes: This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and the Output. Spread Spectrum Control and Input-Output Skew Table Frequency (MHz) 140 Device PCS3P625Z05B / 09B PCS3P625Z05C / 09C Deviation (±%) 0.25 0.5 Input-Output Skew (±TSKEW) 0.0625 0.125 Note: TSKEW is measured in units of the Clock Period Absolute Maximum Ratings Symbol VDD VIN TSTG Ts TJ TDV DC Input Voltage (CLKIN) Storage temperature Max. Soldering Temperature (10 sec) Junction Temperature Static Discharge Voltage (As per JEDEC STD22- A114-B) Parameter Supply Voltage to Ground Potential Rating -0.5 to +4.6 -0.5 to +7 -65 to +125 260 150 2 Unit V °C °C °C KV Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. Operating Conditions Parameter VDD TA CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance Input Capacitance Description Min 3.0 -40 Max 3.6 +85 10 7 Unit V °C pF pF High Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 5 of 15 May 2008 rev 0.1 Electrical Characteristics Parameter VIL VIH IIL IIH VOL VOH IDD Zo PCS3P625Z05B/C PCS3P625Z09B/C Description Input LOW Voltage Input LOW Current Input HIGH Current Output LOW Voltage 6 6 5 5 Test Conditions Min 2.0 Typ Max 0.8 Unit V V µA µA V V mA Ω Input HIGH Voltage VIN = 0V VIN = VDD IOL = 8mA IOH = -8mA Unloaded outputs 23 2.4 50 100 0.4 65 Output HIGH Voltage Output Impedance Dynamic Supply Current Note: 5. CLKIN input has a threshold voltage of VDD/2 6. Parameter is guaranteed by design and characterization. Not 100% tested in production Switching Characteristics Parameter Input Frequency Output Frequency Duty Cycle 7,8 Test Conditions 10pF load Measured at VDD/2 Measured between 0.8V and 2.0V Measured between 2.0V and 0.8V 7, 8 Min 100 100 40 Typ Max 175 175 Unit MHz MHz % nS nS pS pS pS pS mS = (t2 / t1) * 100 7, 8 7, 8 50 60 2.5 2.5 250 ±350 700 ±200 1.0 Output Rise Time Output Fall Time Output-to-output skew CLKOUT Rising Edge All outputs equally loaded Measured at VDD /2 Measured at VDD/2 on the CLKOUT pins of the device Loaded outputs Stable power supply, valid clock presented on CLKIN pin Delay, CLKIN Rising Edge to 8 Device-to-Device Skew 8 Cycle-to-Cycle Jitter 7, 8 PLL Lock Time 8 Note: 7. All parameters specified with 10pF loaded outputs. 8. Parameter is guaranteed by design and characterization. Not 100% tested in production High Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 6 of 15 May 2008 rev 0.1 Switching Waveforms Duty Cycle Timing PCS3P625Z05B/C PCS3P625Z09B/C t1 t2 VDD/2 OUTPUT VDD/2 VDD/2 All Outputs Rise/Fall Time 2V 0.8V 2V 0.8V 3.3V OUTPUT t3 t4 0V Output - Output Skew VDD/2 OUTPUT VDD/2 OUTPUT t5 Input - Output Propagation Delay VDD/2 INPUT VDD/2 OUTPUT t6 High Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 7 of 15 May 2008 rev 0.1 Device - Device Skew PCS3P625Z05B/C PCS3P625Z09B/C VDD/2 CLKOUT, Device 1 VDD/2 CLKOUT, Device 2 t7 Input-Output Skew Test Circuit +3.3V Input Timing-Safe™ Output 0.1uF +3.3V TSKEW TSKEW+ VDD 0.1uF One clock cycle N=1 when spread spectrum is ON For example, TSKEW = ± 0.125 for an Input clock12MHz, translates in to (1/12MHz) * 0.125=10.41nS VDD OUTPUT CLKOUT LOAD GND TSKEW represents input-output skew A Typical example of Timing-Safe™ waveform Input Input CLKOUT with SSOFF Timing-Safe™ CLKOUT High Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 8 of 15 May 2008 rev 0.1 Package Information PCS3P625Z05B/C PCS3P625Z09B/C 8-lead (150-mil) SOIC Package E H D A2 A θ e B A 1 C L D Dimensions Symbol Min A1 A A2 B C D E e H L θ Inches Max 0.010 0.069 0.059 0.020 0.010 0.004 0.053 0.049 0.012 0.007 Millimeters Min Max 0.10 1.35 1.25 0.31 0.18 4.90 BSC 3.91 BSC 1.27 BSC 6.00 BSC 0.41 0° 1.27 8° 0.25 1.75 1.50 0.51 0.25 0.193 BSC 0.154 BSC 0.050 BSC 0.236 BSC 0.016 0° 0.050 8° High Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 9 of 15 May 2008 rev 0.1 8-lead TSSOP (4.40-MM Body) PCS3P625Z05B/C PCS3P625Z09B/C H E D A2 A θ e B A1 L C Dimensions Symbol Min A A1 A2 B c D E e H L θ 0.020 0° 0.002 0.033 0.008 0.004 0.114 0.169 0.026 BSC 0.252 BSC 0.028 8° 0.50 0° Inches Max 0.043 0.006 0.037 0.012 0.008 0.122 0.177 0.05 0.85 0.19 0.09 2.90 4.30 Millimeters Min Max 1.10 0.15 0.95 0.30 0.20 3.10 4.50 0.65 BSC 6.40 BSC 0.70 8° High Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 10 of 15 May 2008 rev 0.1 16-lead (150 Mil) Molded SOIC Package PCS3P625Z05B/C PCS3P625Z09B/C 8 1 PIN 1 ID E H 9 D 16 Seating Plane A e B h A2 D 0.004 θ L C A1 Dimensions Symbol Min A A1 A2 B C D E e H h L θ 0.228 0.010 0.016 0° 0.053 0.004 0.049 0.013 0.008 0.386 0.150 0.050 BSC 0.244 0.016 0.035 8° 5.80 0.25 0.40 0° Inches Max 0.069 0.010 0.059 0.022 0.012 0.394 0.157 Millimeters Min 1.35 0.10 1.25 0.33 0.19 9.80 3.80 1.27 BSC 6.20 0.41 0.89 8° Max 1.75 0.25 1.50 0.53 0.27 10.01 4.00 High Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 11 of 15 May 2008 rev 0.1 PCS3P625Z05B/C PCS3P625Z09B/C 16-lead TSSOP (4.40-MM Body) 8 1 PIN 1 ID E H 9 16 A Seating Plane θ L C e D A2 B A1 D Dimensions Symbol Min A A1 A2 B C D E e H L θ 0.020 0° 0.002 0.031 0.007 0.004 0.193 0.169 0.026 BSC 0.252 BSC 0.030 8° 0.50 0° Inches Max 0.043 0.006 0.041 0.012 0.008 0.201 0.177 0.05 0.80 0.19 0.09 4.90 4.30 Millimeters Min Max 1.20 0.15 1.05 0.30 0.20 5.10 4.50 0.65 BSC 6.40 BSC 0.75 8° High Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 12 of 15 May 2008 rev 0.1 Ordering Code Ordering Code PCS3P625Z0xyG-08-ST PCS3I625Z0xyG-08-ST PCS3P625Z0xyG-08-SR PCS3I625Z0xyG -08-SR PCS3P625Z0xyG-08-TT PCS3I625Z00xyG -08-TT PCS3P625Z0xyG-08-TR PCS3I625Z0xyG -08-TR PCS3P625Z0xyG -16-ST PCS3I625Z0xyG -16-ST PCS3P625Z0xyG -16-SR PCS3I625Z0xyG -16-SR PCS3P625Z0xyG -16-TT PCS3I625Z0xyG -16-TT PCS3P625Z0xyG -16-TR PCS3I625Z0xyG -16-TR Note: x=5 / 9; y=B / C PCS3P625Z05B/C PCS3P625Z09B/C Marking 3P625Z0xyG 3I625Z0xyG 3P625Z0xyG 3I625Z0xyG 3P625Z0xyG 3I625Z0xyG 3P625Z0xyG 3I625Z0xyG 3P625Z0xyG 3I625Z0xyG 3P625Z0xyG 3I625Z0xyG 3P625Z0xyG 3I625Z0xyG 3P625Z0xyG 3I625Z0xyG Package Type 8-pin 150-mil SOIC-TUBE, Green 8-pin 150-mil SOIC-TUBE, Green 8-pin 150-mil SOIC-TAPE & REEL, Green 8-pin 150-mil SOIC-TAPE & REEL, Green 8-pin 4.4-mm TSSOP - TUBE, Green 8-pin 4.4-mm TSSOP - TUBE, Green 8-pin 4.4-mm TSSOP - TAPE & REEL, Green 8-pin 4.4-mm TSSOP - TAPE & REEL, Green 16-pin 150-mil SOIC-TUBE, Green 16-pin 150-mil SOIC-TUBE, Green 16-pin 150-mil SOIC-TAPE & REEL, Green 16-pin 150-mil SOIC-TAPE & REEL, Green 16-pin 4.4-mm TSSOP - TUBE, Green 16-pin 4.4-mm TSSOP - TUBE, Green 16-pin 4.4-mm TSSOP - TAPE & REEL, Green 16-pin 4.4-mm TSSOP - TAPE & REEL, Green Temperature Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial High Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 13 of 15 May 2008 rev 0.1 Device Ordering Information PCS3P625Z05B/C PCS3P625Z09B/C PCS3P625Z0xyG-08-TR R = Tape & Reel, T = Tube or Tray O = TSOT23 S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 J=TSOT26 C=TDFN (2X2) COL DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Clock Generator 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved PulseCore Semiconductor Mixed Signal Product Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. High Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 14 of 15 May 2008 rev 0.1 PCS3P625Z05B/C PCS3P625Z09B/C PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright © PulseCore Semiconductor All Rights Reserved Part Number: PCS3P625Z05B/C PCS3P625Z09B/C Document Version: 0.1 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 Many PulseCore Semiconductor products are protected by issued patents or by applications for patent © Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use. High Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 15 of 15