P1753-40PGMB

PACE1753 SINGLE CHIP, 40MHz CMOS MMU/COMBO FEATURES Implements the MIL-STD-1750A Instruction Set Architecture for Memory Management and Protection of up to 1 Megaword. All mapping memory (10,240 bits) for both the MMU and BPU functions are included on the chip. Designed to interface memory to the PACE1750A/AE 16-bit, 40 MHz processor. Systems can be designed where no WAIT states are required up to 40 MHz clock rates when using these PACE products. System performance and device count are optimized when used with the PACE1754 Processor Interface Circuit (PIC). Provides the following additional functions: — EDAC, Error Detection and Correction—or parity generation and detection — Correct data register—for diagnostics — First memory failing address register — Illegal address error detection— programmable — Multi-Master arbitration 8-bit extended address latches and drivers on chip Information bus and EDAC transceivers on chip 20, 30 and 40 MHz operation over the Military Temperature Range Single 5V ± 10% Power Supply Power Dissipation over Military Temperature Range (PD Outputs Open) < 0.20 watts at 20 MHz < 0.30 watts at 30 MHz < 0.40 watts at 40 MHz Available in: — 64-Pin DIP or Gull Wing (50 Mil Pin centers) — 68-Pin Pin Grid Array (PGA) (100 Mil centers) — 68-Lead Quad Pack (Leaded Chip Carrier) MEMORY MANAGEMENT UNIT AND BLOCK PROTECT UNIT “COMBO” — FUNCTIONAL DESCRIPTION The PACE1753 (COMBO) is a support chip for the PACE1750A/AE microprocessor family. It provides the following supporting functions to the system: 1. Memory management and access protection for up to 1M words. 2 Physical memory write protection for up to 1M words memory in pages of 1K words each. Separate protection is provided for the CPU and for DMA in systems which include DMA. 3. Detection of illegal l/O accesses (as defined by MILSTD-1750A) or access to an unimplemented block of memory. In each case an error flag is generated to the processor. 4 Detection of double errors on the data bus and correction of single errors. An error signal is generated to the processor when a multiple error is detected. 5. RDYA generation. Up to three wait states can be inserted in the address phase of the bus by generating a not-ready, RDYA low signal. The number of wait states required can be programmed in an internal register in the COMBO. 6. Bus arbitration for up to 4 masters. Arbitration is done on a fixed priority basis (i.e. by interconnection of hardware). (In 68 pin package only). Document # MICRO-4 REV D Revised November 2005 PACE1753 ABSOLUTE MAXIMUM RATINGS1 Supply Voltage Range Input Voltage Range Storage Temperature Range Input Current Range Current applied to any output3 Maximum Power Dissipation2 Lead Temperature Range (soldering 10 seconds) Thermal resistance Cases X and T Cases Y and U Case Z (θJC):4 8°C/W 5°C/W 6°C/W 0.5V to +7.0V 0.5V to VCC + 0.5V –65°C to +150°C –30mA to +5mA 150mA 1.5W 300°C RECOMMENDED OPERATING CONDITIONS Supply Voltage Range Case Operating Temperature Range Operating Maximum Power Dissipation (Outputs Open) Device Type 20MHz Device Type 30MHz Device Type 40MHz 4.5V to +5.5V –55°C to +125°C 0.20W 0.30W 0.40W Notes 1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2. Must withstand the added power dissipation due to short circuit test e.g., IOS. 3. Duration 1 second or less. 4. Device Type Definitions from 5962-89505 SMD: Case X: Dual In-Line Case T: Dual In-Line with Gull-Wing Leads Case Y: Leaded Chip Carrier with Gull-Wing Leads Case U: Leaded Chip Carrier with Unformed Leads Case Z: Pin Grid Array Document # MICRO-4 REV D Page 2 of 21 PACE1753 DC ELECTRICAL SPECIFICATIONS (Over recommended operating conditions) Symbol VIH VIL VCD VOH VOL VOL IIH Input LOW Parameter Input HIGH Voltage Voltage2 Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage, except EXT ADR0 – EXT ADR7 Output LOW Voltage, EXT ADR0 – EXT ADR7 Input HIGH Current, except IB0 – IB15, EDC0 – EDC5, EXT ADR0 – EXT ADR7 Input HIGH Current, IB0 – IB15, EDC0 – EDC5, EXT ADR0 – EXT ADR7 Input LOW Current, except IB0 – IB15, EDC0 – EDC5, EXT ADR0 – EXT ADR7 Input LOW Current, IB0 – IB15, EDC0 – EDC5, EXT ADR0 – EXT ADR7 Output Three-State Current Output Three-State Current Quiescent Power Supply Current (CMOS Input Levels, Active) Quiescent Power Supply Current (TTL Input Levels, Active) Dynamic Power Supply ICCD IOS CIN COUT Current Output Short Circuit Input Capacitance Output/Bi-directional Capacitance Current3 –25 10 15 2.4 VCC – 0.2 0.5 0.2 0.5 0.2 10 Min 2.0 –0.5 Max VCC + 0.5 0.8 –1.2 Unit V V V V V V V V V µA VCC = 4.5V, IIN = –18mA VCC = 4.5V, VIN = 0.8V, 2.0V VCC = 4.5V, VIN = 0.8V, 2.0V VCC = 4.5V, VIN = 0.8V, 2.0V VIN = VCC, VCC = 5.5V VIN = VCC, VCC = 5.5V IOH = –8.0mA IOH = –300µA IOL = 8.0mA IOL = 300µA IOL = 20.0mA IOL = 300µA Conditions1 IIH 50 µA IIL –10 µA VIN = GND, VCC = 5.5V VIN = GND, VCC = 5.5V VOUT = 2.4V, VCC = 5.5V VOUT = 0.5V, VCC = 5.5V VIN < 0.2V or < VCC – 0.2V f = 0MHz, Outputs Open, VCC = 5.5V VIN = 3.4V, f = 0MHz, All Inputs, Outputs Open, VCC = 5.5V VCC = 0V to VCC, tr = tf = 2.5 ns, Outputs Open, VCC = 5.5V IIL IOZH IOZL ICCQC –50 50 –50 60 µA µA µA mA ICCQT 110 40 50 60 mA mA mA mA mA pF pF F = 20MHz F = 30MHz F = 40MHz VOUT = GND, VCC = 5.5V Inputs Only Outputs Only (Including I/O Buffers) Notes 1. 4.5V ≤ VCC ≤ 5.5V, –55°C ≤ TC ≤ +125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions. 2. VIL = –3.0V for pulse widths less than or equal to 20ns. 3. Duration of the short should not exceed one second; only one output may be shorted at a time. Document # MICRO-4 REV D Page 3 of 21 PACE1753 AC ELECTRICAL CHARACTERISTICS (VCC = 4.5V) 20 MHz Symbol TD/I (EXT ADR)V Parameter MMU Cache Hit Min Max 25 25 25 35 25 30 25 25 25 25 35 35 35 35 30 30 34 50 25 25 25 50 40 45 25 32 30MHz Min Max 23 20 20 30 20 25 20 20 22 20 25 25 25 25 25 28 30 45 20 22 22 45 35 35 20 30 40 MHz Min Max 23 16 19 25 12 23 12 12 18 16 18 18 18 18 17 25 25 40 16 18 18 40 30 30 20 23 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TSTRBD (EXT ADR ERR)L External Address Error TC (IBD CORR) IBDV (SING ERR)H TC (SING ERR)L TIBDV (EDC GEN)V TSTRBD (EX RDY)L TC (EX RDY)H TC (WR PROT)L TSTRBDH (WR PROT)H TC (GNT1)H TC (GNT0)L TC (GNT0)H TC (GNT1)L TC (RDYA) TFC (IB OUT)V TIBDIN (MEM PAR ERR) TC (MEM PRT ERR) TSTRBD (WR PROT) TC (WR PROT)L TSTRBDH (WR PROT)H TD/I (PROT FLAG) TD/I (PROT FLAG) TC (PROT FLAG) TC (PROT FLAG) TC (EXT ADR) Error Correction Read Cycle Error Correction Read Cycle Error Correction Read Cycle EDAC or Parity Write Cycle MMU Cache Miss MMU Cache Miss MMU Cache Miss MMU Cache Miss Arbiter LOW to HIGH Priority Arbiter LOW to HIGH Priority Arbiter HIGH to LOW Priority Arbiter HIGH to LOW Priority Address Ready Clock to IB Out Valid (I/O Read) Parity Mode Memory Protect Error Write Protect Cache Hit Write Protect Cache Miss Write Protect Cache Miss Cache Hit (BPU Protection Error) Cache Hit (MMU Key-Lock Error) Cache Miss (BPU Protection Error) Cache Hit (MMU Key-Lock Error) Clock to EXT ADR Valid (Miss) Notes: 1. 4.5V ≤ VCC ≤ 5.5V, –55°C ≤ TC ≤ +125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions. 2. VIL = –3.0V for pulse widths less than or equal to 20ns. 3. Duration of the short should not exceed one second; only one output may be shorted at a time. 4. Pulse width of WR PROT/PROT FLAG shall be ≥ 80% of STRBD pulse width. Document # MICRO-4 REV D Page 4 of 21 PACE1753 TERMINAL CONNECTIONS Case Outlines: Dual-In-Line (Case X) and Dual-In-Line with Gull-Wing Leads (Case T) Terminal Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Terminal Symbol GND EDC0 EDC1 EDC2 RESET EDC3 EDC4 EDC5 IB0 IB1 IB2 IB3 IB4 IB5 IB6 IB7 IB8 IB9 VCC IB10 IB11 IB12 Terminal Number 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Terminal Symbol IB13 IB14 IB15 MEM PRT ER MEM PAR ER EXT ADR ER RAM DIS SING ERR DMA ACK GND EXT ADR0 EXT ADR1 EXT ADR2 EXT ADR3 EXT ADR4 EXT ADR5 EXT ADR6 EXT ADR7 VCC AS3 AS2 Terminal Number 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Terminal Symbol AS1 AS0 GND AK3 AK2 AK1 AK0 CLK STRBA STRBD GND EX RDY WR PROT/PROT FLAG R/W D/I M/IO RDYA NC NC NC VCC Document # MICRO-4 REV D Page 5 of 21 PACE1753 TERMINAL CONNECTIONS Case Outlines: Leaded Chip Carrier with unformed leads (Case U) and Leaded Chip Carrier with GullWing Leads (Case Y) Terminal Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Terminal Symbol GND EDC0 EDC1 EDC2 RESET EDC3 EDC4 EDC5 BUS GNT 2 IB0 IB1 IB2 IB3 IB4 IB5 IB6 IB7 BUS REQ 3 IB8 IB9 BUS GNT 3 IB10 IB11 Terminal Number 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Terminal Symbol IB12 IB13 IB14 IB15 MEM PRT ERR MEM PAR ERR EXT ADR ERR RAM DIS SING ERR DMA ACK GND VCC EXT ADR0 EXT ADR1 EXT ADR2 EXT ADR3 EXT ADR4 EXT ADR5 EXT ADR6 EXT ADR7 GND AS3 AS2 Terminal Number 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Terminal Symbol AS1 AS0 BUS REQ 2 AK3 AK2 BUS GNT 1 AK1 AK0 CLK STRBA STRBD BUS REQ 0 EX RDY WR PROT/PROT FLAG R/W D/I M/IO RDYA BUS GNT 0 BUS LOCK BUS REQ 1 VCC Document # MICRO-4 REV D Page 6 of 21 PACE1753 TERMINAL CONNECTIONS Case Outline: Pin Grid Array (Case Z) Terminal Number B1 B2 C1 C2 D1 D2 E1 E2 F1 F2 G1 G2 H1 H2 J1 J2 K1 L2 K2 L3 K3 L4 K4 Terminal Symbol IB14 IB13 IB12 IB11 IB10 BUS GNT 3 IB9 IB8 BUS REQ 3 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 BUS GNT 2 EDC5 EDC4 EDC3 RESET EDC2 Terminal Number L5 K5 L6 K6 L7 K7 L8 K8 L9 K9 L10 K11 K10 J11 J10 H11 H10 G11 G10 F11 F10 E11 E10 Terminal Symbol EDC1 EDC0 GND VCC BUS REQ 1 BUS LOCK BUS GNT 0 RDYA M/IO D/I R/W WR PROT/PROT FLAG Terminal Number D11 D10 C11 C10 B11 A10 B10 A9 B9 A8 B8 A7 B7 A6 B6 A5 B5 A4 B4 A3 B3 A2 Terminal Symbol AS0 AS1 AS2 AS3 VCC GND EXT ADR7 EXT ADR6 EXT ADR5 EXT ADR4 EXT ADR3 EXT ADR2 EXT ADR1 EXT ADR0 GND DMA ACK SING ERR RAM DIS EXT ADR ERR MEM PAR ERR MEM PRT ERR IB15 EX RDY BUS REQ 0 STRBD STRBA CLK AK0 AK1 BUS GNT 1 AK2 AK3 BUS REQ 2 Document # MICRO-4 REV D Page 7 of 21 PACE1753 MMU Cache Hit External Address Error Note: All time measurements on active signals relate to 1.5V levels. Document # MICRO-4 REV D Page 8 of 21 PACE1753 Error Correction (Write Cycle) Memory Protect Error Error Correction (Read Cycle) Ready Address Memory Parity Error Note: All time measurements on active signals relate to 1.5V levels. Document # MICRO-4 REV D Page 9 of 21 PACE1753 MMU Cache Miss Cycle (WA = 0) MMU Cache Miss Cycle (WA > 0) * The WR PROT/PROT FLAG signal is programmed as WR PROT or PROT FLAG. (See BPU Description), T = 1 Clock Period. Note: All time measurements on active signals relate to 1.5V levels. Document # MICRO-4 REV D Page 10 of 21 PACE1753 Low Priority to High Priority Transition B0 CLK B1 B2 B3 B0 B0 B1 REQ1 TC (GNT1)H GNT1 REQ0 LOCK GNT0 TC (GNT0)L Bus Arbitrator High Priority to Low Priority Transition Note: All time measurements on active signals relate to 1.5V levels. Document # MICRO-4 REV D Page 11 of 21 PACE1753 SWITCHING WAVEFORMS AND TEST CIRCUIT (Continued) IB Bus Output (0:15) Standard Output (Non Three-State) Three-State Note: All time measurements on active signals relate to 1.5V levels. Parameter TPLZ TPHZ TPXL TPXH VO ≥ 3V 0V VCC/2 VCC/2 VMEA 0.5V VCC – 0.5V 1.5V 1.5V Document # MICRO-4 REV D Page 12 of 21 PACE1753 PIN FUNCTIONS Symbol BUS REQ0 BUS REQ3 Name Bus Request1 Description Active LOW inputs that indicate a requirement for the bus from 4 masters on the bus. The master assigned to pin BUS-REQ0 has highest priority; the master assigned to pin BUS-REQ3 has lowest priority. An active LOW input that indicates that the one master assigned the bus is using the bus. A new master will receive a bus grant only after this signal becomes inactive. Active LOW outputs indicating which master was granted the bus. It remains active during BUS LOCK unless a higher master request occurs, which resets it. However, the higher master will be granted the bus only after the present master’s BUS LOCK releases the bus. An input signal that indicates whether the current bus cycle is a memory (HIGH) or l/O (LOW) cycle. An input signal that indicates whether the current bus cycle access is for data (HIGH) or instruction (LOW). An input signal that indicates the direction of data flow on the bus. A HIGH indicates a memory read or input operation into the master and a LOW indicates a memory write or output operation from the master. An active HIGH input used to latch the address at the HIGH-toLOW transition of the strobe. An active LOW input used to strobe data in memory and I/O cycles. A single-phase input clock signal (0-40MHz, 40% to 60% duty cycle.) An active LOW input that initializes the device. Active HIGH inputs used to match the access lock in the MMU page for memory accesses. A mismatch will cause the MEM PRT ERR signal to become active. Active HIGH inputs that select the page register group in the MMU. In the DMA physical demultiplexed mode, AS(0:1) will receive the 9th and 10th most significant bits of the physical address for use in the BPU function. BUS LOCK Bus Lock1 BUS GNT0 BUS GNT3 Bus Grant1 M/IO D/I R/W Memory or I/O Data or Instruction Read or Write STRBA STRBD CPU-CLK RESET AK0 - AK3 Address Strobe Data Strobe CPU Clock Reset Access Key AS0 - AS3 Address State EXT ADR0 EXT ADR7 Extended Addresses Bus A bi-directional active HIGH bus. In CPU cycles, it is an output bus which is used to select one of 256 pages, 4K words each, expanding the direct addressing space to 1M word. In DMA cycles, indicated by DMA-ACK being active, it is also an output bus except when programmed for the physical demultiplexed DMA mode. In this case it becomes an input to receive the 8 most significant bits of the DMA physical address for use in the BPU function. Information Bus Detection/Correction Bus An active HIGH bi-directional time multiplexed address/data bus. IB0 is the most significant bit. An active HIGH bi-directional bus used for detection of errors on the data bus (IB0 - IB15) and correction of single errors. When working in parity mode EDC0 is the parity bit. EDC0 - EDC5 are undefined in this case. IB0 - IB15 EDC0 - EDC5 Document # MICRO-4 REV D Page 13 of 21 PACE1753 PIN FUNCTIONS (Continued) Symbol MEM PRT ERR Name Memory Protect Error Description An active LOW output generated by the MMU or BPU blocks to signal to the CPU a protected memory violation. The error is generated in one of the following conditions: a mismatch in the access keys in the MMU page, an access to an execution protected page during instruction cycles, an access to a write-protected page during data cycles, or an access to a page write-protected by the BPU. An active LOW output which signals to the CPU an error on the data bus during a memory cycle. Two detection modes can be selected by programming the control register: EDAC mode (6 Hamming code parity bits) or single bit parity mode (even or odd parity). The signal is inactive when none of the above modes are selected (default after Reset). An active LOW output which signals to the CPU an unimplemented memory or illegal I/O access. An active HIGH output to signal detection of a single error on the data bus in memory cycles. It is high impedance when the EDAC function is disabled by the program (default state after Reset). An active HIGH input from the P1754 device which enables the corrected data on the data bus when the EDAC function is enabled. An internal one clock delay is generated before the data is output on the bus to allow external memory to disconnect itself from the bus. An active HIGH output that indicates that no wait states are requested. It becomes inactive for one clock (inserting one wait state) whenever a memory page different than the current one is accessed (causing a miss). An active HIGH output that indicates that no wait states are requested when STRBA is active. Wait states are inserted when this signal becomes inactive during STRBA. Up to three wait states can be inserted by programming an internal register. Three wait states are inserted after Reset (default). Either an active LOW output (following STRBD timing) during legal memory write cycles, when no protection error occurs, or an active HIGH level indicating a protection error in a write cycle. Each mode can be selected by programming the control register. Default mode after Reset is write-protected. An active HIGH input from the DMA controller which indicates a DMA cycle. Used to select the DMA table in the BPU memory for protection. For example, this could allow the DMA channel to update the program which could be write-protected from the processor. In the physical DMA mode, it will cause the Extended Address Lines (EXT ADR0-7) to become inputs, providing BPU protection of the DMA transfers. MEM PAR ERR Memory Parity Error EXT ADR ERR SING ERR External Address Error Single Error RAM DIS RAM-Disable EX RDY Data Ready RDYA Address Ready WR PROT/ PROT FLAG Write Protected/ Protection Flag DMA ACK DMA Acknowledge Note: 1. Used for Bus Arbitration; only available on 68-lead devices. Document # MICRO-4 REV D Page 14 of 21 PACE1753 Standardized Military Drawing PIN 5962-8950501UX 5962-8950501YX 5962-8950501ZX 5962-8950502UX 5962-8950502YX 5962-8950502ZX 5962-8950503UX 5962-8950503YX 5962-8950503ZX 5962-8950504TX 5962-8950504XX 5962-8950505TX 5962-8950505XX 5962-8950506TX 5962-8950506XX Vendor CAGE Number 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 Vendor similar PIN P1753-20QLMB P1753-20QGMB P1753-20PGMB P1753-30QLMB P1753-30QGMB P1753-30PGMB P1753-40QLMB P1753-40QGMB P1753-40PGMB P1753-20GMB P1753-20CMB P1753-30GMB P1753-30CMB P1753-40GMB P1753-40CMB ORDERING INFORMATION Document # MICRO-4 REV D Page 15 of 21 PACE1753 CASE OUTLINE X: 64 Lead Top Brazed DIP Package, Straight Lead Version (Ordering Code C) Inches .002 .005 .008 .010 .015 .016 .018 .025 .040 .050 .185 .265 .470 .530 .590 .620 .645 1.550 1.563 mm 0.05 0.12 0.20 0.25 0.38 0.40 0.45 0.63 1.01 1.27 4.70 6.73 11.93 13.46 14.98 15.74 16.38 39.37 39.70 NOTES: 1) Dimensions are in inches. 2) Metric equivalents are given for general information only. 3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. Document # MICRO-4 REV D Page 16 of 21 PACE1753 CASE OUTLINE T: 64 Lead Top Brazed DIP Package, Gullwing Lead Version (Ordering Code G) Inches .001 .003 .005 .008 .010 .015 .016 .022 .030 .040 .050 .150 .470 .530 .590 .620 .868 1.663 mm 0.03 0.08 0.12 0.20 0.25 0.38 0.41 0.55 0.76 1.01 1.27 3.81 11.93 13.46 14.98 15.74 22.04 42.24 NOTES: 1) Dimensions are in inches. 2) Metric equivalents are given for general information only. 3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. 4) Case T is derived from Case X by forming the leads to the shown gullwing configuration. Document # MICRO-4 REV D Page 17 of 21 PACE1753 CASE OUTLINE U: 68 Lead Quad Pack with Straight Leads (Ordering Code QL) Inches .002 .004 .006 .010 .012 .020 .050 .100 .116 .250 .560 .570 .800 .955 1.090 mm 0.05 0.10 0.15 0.25 0.30 0.51 1.27 2.54 2.95 6.40 14.22 14.48 20.32 24.25 27.69 NOTES: 1) Dimensions are in inches. 2) Metric equivalents are given for general information only. 3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. 4) Pin 1 indicator can be either rectangle, dot, or triangle at specified location or referenced to the uniquely beveled corner. 5) Corners indicated as notched may be either notched or square. Document # MICRO-4 REV D Page 18 of 21 PACE1753 CASE OUTLINE Y: 68 Lead Quad Pack with Gullwing Leads (Ordering Code QG) Inches .004 .005 .008 .010 .012 .015 .016 .020 .024 .040 .050 .100 .115 .570 .800 .955 1.010 1.090 mm 0.10 0.12 0.20 0.25 0.30 0.38 0.41 0.50 0.60 1.02 1.27 2.54 2.92 14.48 20.32 24.25 25.65 27.68 NOTES: 1) Dimensions are in inches. 2) Metric equivalents are given for general information only. 3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. 4) Pin 1 indicator can either be rectangle, dot, or triangle at specified location or referenced to the uniquely beveled corner. 5) Corners indicated as notched my be either notched or square (with radius). 6) Case Y is derived from Case U by forming the leads to the shown gullwing configuration. Document # MICRO-4 REV D Page 19 of 21 PACE1753 CASE OUTLINE Z: 68-Pin Pin Grid Array (PGA) (Ordering Code PG) Inches .016 .020 .040 .050 .059 .060 .098 .100 .120 .150 .170 1.010 1.089 1.160 mm 0.41 0.50 1.01 1.27 1.49 1.52 2.49 2.54 3.04 3.81 4.32 25.65 27.66 29.46 NOTES: 1) Dimensions are in inches. 2) Metric equivalents are given for general information only. 3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. 4) Corners except pin number 1 (ref.) can be either rounded or square. 5) All pins must be on the .100" grid. Document # MICRO-4 REV D Page 20 of 21 PACE1753 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: REV. ORIG A B C D ISSUE DATE May-89 Jul-04 Aug-05 Oct-05 11/15/05 MICRO-4 PACE1753 CMOS MMU/COMBO ORIG. OF CHANGE RKK JDB JDB JDB JDB DESCRIPTION OF CHANGE New Data Sheet Added Pyramid logo Re-created electronic version Altered case outline drawing for case X and case T Removed Commercial Temp Document # MICRO-4 REV D Page 21 of 21