P1754-20QGMB

PACE1754 SINGLE CHIP, 40MHz CMOS PROCESSOR INTERFACE CIRCUIT (PIC) FEATURES The PACE1754 (PIC) is a support chip for the PACE1750A/AE Processor. It eliminates the SSI/ MSI Logic and external system functions required in typical 1750A implementations. Provides a significant savings in part-count and power dissipation enhancing reliability and overall system speed performance. Provides an optimal interface when used with the PACE1753 MMU/COMBO in a full 1750A implementation. Provides the following additional important system functions: — Programmable READY for memory and I/O — Automatic READY during self-test and internal I/O instructions — 100KHz timer clock output provided — Programmable system watchdog—ranges from 1 µs to 1 minute — Programmable Bus time-out function — Memory Parity generation/detection — Error detection of unimplemented memory and/or I/O space addressing — First failing memory address register for diagnostics — High drive three-state address latches — Built-in system test program—automatically tests the PACE1750A/AE CPU, PACE1753 MMU/COMBO, PACE1754 PIC and system address lines as well as memory and I/O strobes — System configuration decoding and buffering — Interrupt acknowledge decoder and strobe — Start up ROM support per MIL-STD-1750A — Memory or I/O READ/WRITE three-state strobes with external three-state control for DMA applications 20, 30 and 40 MHz operation over full Military Temperature Range Single 5V ± 10% Power Supply Power Dissipation over Military Temperature Range < 0.25 watts at 20 MHz < 0.30 watts at 30 MHz < 0.35 watts at 40 MHz Available in: — 64-Pin DIP or Gull Wing (50 Mil Pin centers) — 68-Pin Pin Grid Array (PGA) (100 Mil centers) — 68-Lead Quad Pack PACE1754 PROCESSOR INTERFACE CIRCUIT DESCRIPTION The PACE1754 Processor Interface Circuit (PIC) is a single chip implementation of many special system functions that are often required when using the PACE1750A/AE, single chip, 40MHz CMOS Microprocessor. The PIC allows a system designer to design a higher performance, more effecient microprocessor system which uses less power and takes up less board space than was previously possible. In addition to providing significant savings in part count and power dissipation the PIC uses only a 5V ±10%, single supply and operates at 20, 30 and 40 MHz over the fully Military Temperature Range. The PIC provides many important system functions. These functions are governed by respective bit positions in a programmable Control Register which is incorporated in the PIC. The individual bits of the control register are set to select the various features and are set to a specified default value upon Reset. Document # MICRO-5 REV C Revised November 2005 PACE1754 ABSOLUTE MAXIMUM RATINGS1 Supply Voltage Range Input Voltage Range Storage Temperature Range Input Current Range Current applied to any output3 Maximum Power Dissipation2 Lead Temperature Range (soldering 10 seconds) Thermal resistance (θJC Cases X and T Cases Y and U Case Z ):4 8°C/W 5°C/W 6°C/W 0.5V to +7.0V 0.5V to VCC + 0.5V –65°C to +150°C –30mA to +5mA 150mA 1.5W 300°C RECOMMENDED OPERATING CONDITIONS Case Temperature –55°C to +125°C GND 0 VCC 4.5V to +5.5V Notes: 1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2. Must withstand the added power dissipation due to short circuit test e.g., IOS. 3. Duration 1 second or less. 4. Device Type Definitions from 5962-88642 SMD: Case X: Dual In-Line Case T: Dual In-Line with Gull-Wing Leads Case Y: Leaded Chip Carrier with Gull-Wing Leads Case U: Leaded Chip Carrier with Unformed Leads Case Z: Pin Grid Array Document # MICRO-5 REV C Page 2 of 20 PACE1754 DC ELECTRICAL SPECIFICATIONS (Over recommended operating conditions) Symbol VIH VIL VCD VOH VOL VOL IIH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage, except A0 – A15 Output LOW Voltage, A0 – A15 Input HIGH Current, except IB0 – IB15, parity/IB16, SING ERR, A0/EXT AD0, A1/EXT AD1, STRBA Input HIGH Current, IB0 – IB15, parity/IB16, A0/EXT AD0, A1/EXT AD1 Input HIGH Current, STRBA, SING ERR Input LOW Current, except IB0 – IB15, parity/IB16, SING ERR, A0/EXT AD0, A1/EXT AD1, STRBD, TEST ON Input LOW Current, IB0 – IB15, parity/IB16, SING ERR, A0/EXT AD0, A1/EXT AD1 Input LOW Current, STRBD, TEST ON Output Three-State Current Output Three-State Current Quiescent Power Supply Current (CMOS Input Levels) Quiescent Power Supply Current (TTL Input Levels) Dynamic Power ICCD IOS CIN COUT Supply Current Output Short Circuit Input Capacitance Output/Bi-directional Capacitance f = 20MHz f = 30MHz f = 40MHz Current2 –25 10 15 2.4 VCC – 0.2 0.5 0.2 0.5 0.2 10 Min 2.0 –0.5 Max VCC + 0.5 0.8 –1.2 Unit V V V V V V V V V µA VCC = 4.5V, IIN = –18mA VCC = 4.5V, VIN = 0.8V, 2.0V VCC = 4.5V, VIN = 0.8V, 2.0V VCC = 4.5V, VIN = 0.8V, 2.0V VIN = VCC, VCC = 5.5V VIN = VCC, VCC = 5.5V VIN = VCC, VCC = 5.5V VIN = GND, VCC = 5.5V VIN = GND, VCC = 5.5V VIN = GND, VCC = 5.5V VOUT = 2.4V, VCC = 5.5V VOUT = 0.5V, VCC = 5.5V VIN < 0.2V or > VCC – 0.2V f = 0MHz, Outputs Open, VCC = 5.5V VIN = 3.4V, f = 0MHz, All Inputs, Outputs Open, VCC = 5.5V VIN = 0V to VCC, tr = tf = 2.5 ns typ., Outputs Open, VCC = 5.5V VOUT = GND, VCC = 5.5V Inputs Only Outputs Only (Including I/O Buffers) IOH = –8.0mA IOH = –300µA IOL = 8.0mA IOL = 300µA IOL = 20.0mA IOL = 300µA Conditions1 IIH IIH IIL 50 µA 500 –10 µA µA IIL IIL IOZH IOZL ICCQC –50 –500 50 –50 10 µA µA µA µA mA ICCQT 50 40 50 60 mA mA mA mA mA pF pF Notes: 1. 4.5V ≤ VCC ≤ 5.5V, –55°C ≤ TC ≤ +125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions. 2. Duration of the short should not exceed one second; only one output may be shorted at a time. Document # MICRO-5 REV C Page 3 of 20 PACE1754 AC ELECTRICAL CHARACTERISTICS1, 2 (VCC = 5V ± 10% Over Recommended Operating Conditions) 20 MHz Symbol tEX RDY (RDYD)V tC (RDYD)V tSTRBAH (A)V tIBAV (A)V tFC (R)L tSTRBDH (R)H tSTRBDL (W)L tSTRBDH (W)H tIBDIN (ME PA ER)L tIBAIN (EX AD ER) tSTRBDL – (STRT ROM)V tFC (IB OUT)V tC (TIMER CLK) tIB INV (IB16) tEXT AD (CLKB3) tEX RDY1 (RDYD)V tFC (SCR EN) tSTRBDH (SCR EN) Parameter Time from External Ready to Ready Data Valid Time from Clock Read to Ready Data Valid Time from Strobe Address HIGH to Address Bus Valid Time from Information Bus Address to Address Bus Valid Time from Falling Clock to Read LOW Time from Strobe Data HIGH to Read HIGH Time from Strobe Data LOW to Write LOW Time from Strobe Data HIGH to Write HIGH Time from Information Bus Data into Memory Parity Error LOW Time from Information Bus Address into External Address Error Time from Strobe Data LOW to Start-up ROM Valid Time from Falling Clock to Information Bus Valid Time from Rising Edge of Clock to Timer Clock Time from Information Bus Data to Parity Valid Extended Address Setup Time Time from External Ready Data to Ready Data Valid Time from Falling Clock to SCR Enable; Case Types T and X only Time from STRBD HIGH to SCR Enable; Case Types T and X only 10 28 30 30 Min Max 16 28 29 31 24 24 26 26 22 30 26 30 30 25 10 24 24 24 30MHz Min Max 14 22 21 22 18 18 20 20 17 25 20 25 25 20 10 21 24 24 40 MHz Min Max 12 16 19 20 12 12 15 15 12 20 15 25 20 18 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. 4.5V ≤ VCC ≤ 5.5V, –55°C ≤ TC ≤ +125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions. 2. All measurements of delay times on active signals are related to the 1.5V levels. Document # MICRO-5 REV C Page 4 of 20 PACE1754 TERMINAL CONNECTIONS Case Outlines: Dual-In-Line (Case X) and Dual-In-Line with Gull-Wing Leads (Case T) Terminal Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Terminal Symbol GND SCR EN TEST ON VCC RESET TEST END TIMER CLK EX RDY 1 IB0 IB1 IB2 IB3 IB4 IB5 IB6 IB7 IB8 IB9 GND IB10 IB11 IB12 Terminal Number 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Terminal Symbol IB13 IB14 IB15 IB16 ME PA ER/RAM DIS EX AD ER/SING ERR INTA STRT ROM VCC GND A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 Terminal Number 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Terminal Symbol A3 GND A2 A1/EXT AD1 A0/EXT AD0 TC CPU CLK STRBA STRBD STRB EN EX RDY RDYD R/W GND M/IO MEMW MEMR IOW IOR VCC Document # MICRO-5 REV C Page 5 of 20 PACE1754 TERMINAL CONNECTIONS Case Outlines: Leaded Chip Carrier with unformed leads (Case U) and Leaded Chip Carrier with GullWing Leads (Case Y) Terminal Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Terminal Symbol GND SC0 SC1 TEST ON RESET TEST END TIMER CLK SC2 VCC IB0 IB1 IB2 IB3 IB4 IB5 IB6 IB7 EX RDY 1 IB8 IB9 GND IB10 IB11 Terminal Number 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Terminal Symbol IB12 IB13 IB14 IB15 PARITY/IB16 ME PA ER/RAM DIS EX AD ER/SING ERR INTA STRT ROM VCC GND A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 Terminal Number 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Terminal Symbol A3 GND A2 A1/EXT AD1 A0/EXT AD0 SC4 SC3 TC CPU CLK STRBA STRBD STRB EN EX RDY RDYD R/W GND M/IO MEMW MEMR IOW IOR VCC Document # MICRO-5 REV C Page 6 of 20 PACE1754 TERMINAL CONNECTIONS Case Outline: Pin Grid Array (Case Z) Terminal Number B1 B2 C1 C2 D1 D2 E1 E2 F1 F2 G1 G2 H1 H2 J1 J2 K1 L2 K2 L3 K3 L4 K4 Terminal Symbol VCC IB14 IB13 IB12 IB11 IB10 IB9 IB8 EX RDY 1 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 GND SC2 TIMER CLK TEST END RESET TEST ON Terminal Number L5 K5 L6 K6 L7 K7 L8 K8 L9 K9 L10 K11 K10 J11 J10 H11 H10 G11 G10 F11 F10 E11 E10 Terminal Symbol SC1 SC0 VCC IOR IOW MEMR MEMW M/IO GND R/W RDYD EX RDY STRB EN STRBD STRBA CPU CLK TC SC3 SC4 A0/EXT AD0 A1/EXT AD1 A2 GND Terminal Number D11 D10 C11 C10 B11 A10 B10 A9 B9 A8 B8 A7 B7 A6 B6 A5 B5 A4 B4 A3 B3 A2 Terminal Symbol A3 A4 A5 A6 A7 GND A8 A9 A10 A11 A12 A13 A14 A15 GND VCC STRT ROM INTA EX AD ER ME PA ER PARITY/IB16 IB15 Document # MICRO-5 REV C Page 7 of 20 PACE1754 STRT ROM Timer Clk IB Bus Output (0:15) EX AD ER Extended Addresses (0:1) Note: All time measurements on active signals relate to 1.5V levels. Document # MICRO-5 REV C Page 8 of 20 PACE1754 RDYD Timing TEST END Timing1 Notes: 1. The last two instructions executed during system test are: XIO RA, 1F44, 0 and JC 7, 0000 hex, 0. After execution of the IOW bus cycle, the XIO proceeds by filling the instruction pipe with two memory read bus cycles where the opcode 7070 hex and 0000 hex are entered to the processor. As from the end of STRBD in the second cycle, TEST END is asserted. At this point, the execution of IC starts by first issuing two fetch cycles from the "old PC" (from addresses XXXX & XXXX+1). The data will be taken from system memory (because TEST END is asserted) but both the address and data are irrelevent. Following that, IC will start filling the pipe from address 0000 hex and 0001 hex, now from the system memory to start user's program execution. 2. All time measurements on active signals relate to 1.5V levels. Document # MICRO-5 REV C Page 9 of 20 PACE1754 Address Bus and Strobes Note: All time measurements on active signals relate to 1.5V levels. Document # MICRO-5 REV C Page 10 of 20 PACE1754 TEST CIRCUITS Standard Output (Non Three-State) Three-State Note: All time measurements on active signals relate to 1.5V levels. Parameter TPLZ TPHZ TPXL TPXH VO ≥ 3V 0V VCC/2 VCC/2 VMEA 0.5V VCC – 0.5V 1.5V 1.5V Document # MICRO-5 REV C Page 11 of 20 PACE1754 PIN FUNCTIONS Symbol CPU CLK STRBA STRBD Name CPU Clock Strobe Address Strobe Data Description A single-phase input clock signal (0-40MHz, 40% to 60% duty cycle.) An active HIGH input which latches the contents of IB(0:15) into the address latches. An active LOW input which is used for writing or reading data to or from the device and also to produce the external memory and I/O strobes. A 100KHz output (fixed frequency) based on the programmed operating frequency of the CPU clock. An active LOW output produced in memory write cycles. An active LOW output produced in memory read cycles. An active LOW output produced in output write cycles. An active LOW output produced in input read cycles. An active LOW output produced after any interrupt, corresponding to an output write to address 1000 (hex). An active LOW output (in 64 pin only) produced any time an input read from address 8410 (hex), read system configuration is executed. An active LOW input, enabling the active state of the address outputs and the MEMR, MEMQ, IOR, and IOW outputs. When at a logic "1" (if enabled by bits EST, EAD of the control register) it will correspondingly enable the three-state state of the above signals. A bi-directional time multiplexed bus. It is an input during the address phase of any bus cycle and also during the data phase when writing. It is an output during the data phase when reading from the device. A bi-directional line. It is an output during write cycles and an input during read cycles. It is used to implement the parity function at the system level. An active HIGH output bus. Contains the address of the current bus cycle as latched by the end of STRBA. In system configurations including the MMU function, the only active lines during memory are A(4:15). In this case, A(2:3) are high impedance (don't care) and A(0:1) turn into inputs called Extended Addresses, EXT ADR (0:1). In this case, these two lines supplied by the MMU, will be used to operate the programmable ready generation during bus cycles. An input qualifier indicating the nature of the current bus cycle. TIMER CLK MEMW MEMR IOW IOR INTA SCR EN Timer Clock Memory Write Strobe Memory Read Strobe I/O Write Strobe I/O Read Strobe Interrupt Acknowledge Strobe System Configuration STRB EN Strobe Enable IB0 - IB15 Information Bus (0:15) IB16 Information Bus (16) A(0:1)/ EX AD(0:1), A(2:15) Address Bus (0:15) M/IO Memory I/O Document # MICRO-5 REV C Page 12 of 20 PACE1754 PIN FUNCTIONS (Continued) Symbol R/W RESET TEST ON Name Read or Write External Reset System Test Enable Description An input qualifier indicating the nature of the current bus cycle, either Read (1) or Write (0). An active LOW input used to initialize the device's hardware. An active LOW input used to enable the execution of the System Test built into the device, immediately after completion of the P1754 initialization and before fetching any instruction from the user program. An active HIGH output indicating whether the system test in the device has been completed. Whenever the system test is disabled by the TEST ON signal, the TEST END output will be at a logical "1" immediately after RESET is removed. An output following the execution of the ESUR and DSUR, I/O commands as defined in MIL-STD-1750A. It will be at the logical "1" level after executing ESUR and at the logical "0" level after executing DSUR. Initially, it defaults to a logical "1". An active HIGH output to be connected to the P1750A/AE CPU input to control the bus cycle termination. An active HIGH input which at logical "0" overrides the internal RDYD generation and forces it to a logical "0". An active LOW input which at logical "1" overrides the internal RDYD generation and forces it to a logical "0". An active LOW output indicating a parity error when reading from memory. It becomes an active HIGH output called RAM DISABLE for handshaking with the P1753 MMU when the device is programmed to support EDAC. An active LOW output indicating an illegal address error when referencing memory or I/O. It becomes an active HIGH output called SINGLE ERROR for handshaking with the P1753 MMU when the device is programmed to support EDAC. An active HIGH output indicating a Bus time out or a watchdog trigger. Inputs (for case outlines U, Y, and Z only) which are buffered onto IB0–IB4 when executing an I/O read from I/O address 8410 (hex), system configuration. 0 volts system ground. 5 volts ± 10% power supply. TEST END System Test End STRT ROM Start Up ROM RDYD EX RDY EX RDY1 ME PA ER/ RAM DIS Ready Data External Ready Data External Ready Data Memory Parity Error EX AD ER/ SING ERR Illegal Address Error TC SC0–SC4 Terminal Count System Configuration GND VCC Ground Power Supply Case U: Leaded Chip Carrier with Unformed Leads Case Y: Leaded Chip Carrier with Gull-Wing Leads Case Z: Pin Grid Array Document # MICRO-5 REV C Page 13 of 20 PACE1754 Standardized Military Drawing PIN 5962-8864201UX 5962-8864201YX 5962-8864201ZX 5962-8864202UX 5962-8864202YX 5962-8864202ZX 5962-8864203UX 5962-8864203YX 5962-8864203ZX 5962-8864204TX 5962-8864204XX 5962-8864205TX 5962-8864205XX 5962-8864206TX 5962-8864206XX Vendor CAGE Number 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 Vendor similar PIN P1754-20QLMB P1754-20QGMB P1754-20PGMB P1754-30QLMB P1754-30QGMB P1754-30PGMB P1754-40QLMB P1754-40QGMB P1754-40PGMB P1754-20GMB P1754-20CMB P1754-30GMB P1754-30CMB P1754-40GMB P1754-40CMB ORDERING INFORMATION Document # MICRO-5 REV C Page 14 of 20 PACE1754 CASE OUTLINE X: 64 Lead Top Brazed DIP Package, Straight Lead Version (Ordering Code C) Inches .002 .005 .008 .010 .015 .016 .018 .025 .040 .050 .185 .265 .470 .530 .590 .620 .645 1.550 1.563 mm 0.05 0.12 0.20 0.25 0.38 0.40 0.45 0.63 1.01 1.27 4.70 6.73 11.93 13.46 14.98 15.74 16.38 39.37 39.70 NOTES: 1) Dimensions are in inches. 2) Metric equivalents are given for general information only. 3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. Document # MICRO-5 REV C Page 15 of 20 PACE1754 CASE OUTLINE T: 64 Lead Top Brazed DIP Package, Gullwing Lead Version (Ordering Code G) Inches .001 .003 .005 .008 .010 .015 .016 .022 .030 .040 .050 .150 .470 .530 .590 .620 .868 1.663 mm 0.03 0.08 0.12 0.20 0.25 0.38 0.41 0.55 0.76 1.01 1.27 3.81 11.93 13.46 14.98 15.74 22.04 42.24 NOTES: 1) Dimensions are in inches. 2) Metric equivalents are given for general information only. 3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. 4) Case T is derived from Case X by forming the leads to the shown gullwing configuration. Document # MICRO-5 REV C Page 16 of 20 PACE1754 CASE OUTLINE U: 68 Lead Quad Pack with Straight Leads (Ordering Code QL) Inches .002 .004 .006 .010 .012 .020 .050 .100 .116 .250 .560 .570 .800 .955 1.090 mm 0.05 0.10 0.15 0.25 0.30 0.51 1.27 2.54 2.95 6.40 14.22 14.48 20.32 24.25 27.69 NOTES: 1) 2) 3) 4) 5) Dimensions are in inches. Metric equivalents are given for general information only. Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. Pin 1 indicator can be either rectangle, dot, or triangle at specified location or referenced to the uniquely beveled corner. Corners indicated as notched may be either notched or square. Document # MICRO-5 REV C Page 17 of 20 PACE1754 CASE OUTLINE Y: 68 Lead Quad Pack with Gullwing Leads (Ordering Code QG) Inches .004 .005 .008 .010 .012 .015 .016 .020 .024 .040 .050 .100 .115 .570 .800 .955 1.010 1.090 mm 0.10 0.12 0.20 0.25 0.30 0.38 0.41 0.50 0.60 1.02 1.27 2.54 2.92 14.48 20.32 24.25 25.65 27.68 NOTES: 1) 2) 3) 4) 5) 6) Dimensions are in inches. Metric equivalents are given for general information only. Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. Pin 1 indicator can either be rectangle, dot, or triangle at specified location or referenced to the uniquely beveled corner. Corners indicated as notched my be either notched or square (with radius). Case Y is derived from Case U by forming the leads to the shown gullwing configuration. Document # MICRO-5 REV C Page 18 of 20 PACE1754 CASE OUTLINE Z: 68-Pin Pin Grid Array (PGA) (Ordering Code PG) Inches .016 .020 .040 .050 .059 .060 .098 .100 .120 .150 .170 1.010 1.089 1.160 mm 0.41 0.50 1.01 1.27 1.49 1.52 2.49 2.54 3.04 3.81 4.32 25.65 27.66 29.46 NOTES: 1) Dimensions are in inches. 2) Metric equivalents are given for general information only. 3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. 4) Corners except pin number 1 (ref.) can be either rounded or square. 5) All pins must be on the .100" grid. Document # MICRO-5 REV C Page 19 of 20 PACE1754 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: REV. ORIG A B C ISSUE DATE May-89 Jul-04 Aug-05 11/15/05 MICRO-5 PACE1754 PIC BULK CMOS ORIG. OF CHANGE RKK JDB JDB JDB DESCRIPTION OF CHANGE New Data Sheet Added Pyramid logo Re-created electronic version Removed Commercial Temperature Range Document # MICRO-5 REV C Page 20 of 20