P4C163-35FM

P4C163/P4C163L ULTRA HIGH SPEED 8K x 9 STATIC CMOS RAMS FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) – 25/35ns (Commercial) – 25/35/45ns (Military) Low Power Operation (Commercial/Military) Output Enable and Dual Chip Enable Control Functions Single 5V±10% Power Supply Data Retention with 2.0V Supply, 10 µA Typical Current (P4C163L Military) Common I/O Fully TTL Compatible Inputs and Outputs Standard Pinout (JEDEC Approved) – 28-Pin 300 mil DIP, SOJ – 28-Pin 350 x 550 mil LCC – 28-Pin CERPACK DESCRIPTION The P4C163 and P4C163L are 73,728-bit ultra high-speed static RAMs organized as 8K x 9. The CMOS memories require no clocks or refreshing and have equal access and cycle times. Inputs are fully TTL-compatible. The RAMs operate from a single 5V±10% tolerance power supply. With battery backup, data integrity is maintained for supply voltages down to 2.0V. Current drain is 10 µA from a 2.0V supply. Access times as fast as 25 nanoseconds are available, permitting greatly enhanced system operating speeds. CMOS is used to reduce power consumption in both active and standby modes. The P4C163 and P4C163L are available in 28-pin 300 mil DIP and SOJ, 28-pin 350 x 550 mil LCC, and 28-pin CERPACK packages providing excellent board level densities. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS DIP (P5, C5), SOJ (J5) CERPACK (F4) SIMILAR LCC (L5) Document # SRAM120 REV C 1 Revised August 2006 P4C163/163L MAXIMUM RATINGS(1) Symbol VCC VTERM TA Parameter Power Supply Pin with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Temperature Value –0.5 to +7 –0.5 to VCC +0.5 –55 to +125 Unit V Symbol TBIAS TSTG PT IOUT Parameter Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value –55 to +125 –65 to +150 1.0 50 Unit °C °C W mA V °C RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade(2) Military Ambient Temperature –55 to +125°C GND 0V VCC 5.0V ± 10% Grade(2) Commercial Ambient Temperature 0°C to +70°C GND 0V VCC 5.0V ± 10% DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Symbol VIH VIL VHC VLC VCD VOL VOLC VOH VOHC ILI ILO Parameter Input High Voltage Input Low Voltage CMOS Input High Voltage CMOS Input Low Voltage Input Clamp Diode Voltage Output Low Voltage (TTL Load) Output Low Voltage (CMOS Load) Output High Voltage (TTL Load) Output High Voltage (CMOS Load) Input Leakage Current Output Leakage Current Test Conditions P4C163 Min 2.2 –0.5(3) –0.5 (3) P4C163L Min 2.2 –0.5(3) –0.5 (3) Max VCC+0.5 0.8 0.2 –1.2 0.4 0.2 Max VCC+0.5 0.8 0.2 –1.2 0.4 0.2 Unit V V V V V V V V V VCC–0.2 VCC+0.5 VCC = Min., IIN = –18 mA IOL = +8 mA, VCC = Min. IOLC = +100 µA, VCC = Min. IOH = –4 mA, VCC = Min. IOHC = –100 µA, VCC = Min. VCC = Max. VIN = GND to VCC VCC = Max., CE = VIH, VOUT= GND to VCC Mil. Com’l. Mil. Com’l. 2.4 VCC–0.2 –10 –5 –10 –5 +10 +5 +10 +5 VCC–0.2 VCC+0.5 2.4 VCC–0.2 –5 N/A –5 N/A +5 N/A +5 N/A µA µA CAPACITANCES(4) (VCC = 5.0V, TA = 25°C, f = 1.0MHz) Symbol CIN Parameter Input Capacitance Conditions Typ. Unit VIN = 0V 5 pF Symbol COUT Parameter Output Capacitance Conditions Typ. Unit VOUT = 0V 7 pF Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. Document # SRAM120 REV C Page 2 of 12 P4C163/163L POWER DISSIPATION CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Symbol ICC ICC ISB Parameter Dynamic Operating Current – 25 Dynamic Operating Current – 35, 45 Test Conditions VCC = Max., f = Max., Outputs Open VCC = Max., f = Max., Outputs Open Mil. Com’l. Mil. Com’l. Mil. Com’l. Mil. Com’l. P4C163 Min — — — — — — — — Max 145 125 120 95 40 35 20 18 P4C163L Min — — — — — — — — Max 145 N/A 120 N/A 40 N/A 1 N/A Unit mA mA mA Standby Power Supply CE1 ≥ VIH or Current (TTL Input Levels) CE2 ≤ VIL, VCC = Max., f = Max., Outputs Open Standby Power Supply Current (CMOS Input Levels) CE1 ≥ VHC or CE2 ≤ VLC, VCC = Max., f = 0, Outputs Open, VIN ≤ VLC or VIN ≥ VHC ISB1 mA n/a = Not Applicable DATA RETENTION CHARACTERISTICS (P4C163L, Military Temperature Only) Symbol VDR ICCDR tCDR tR† Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time CE1 ≥ VCC – 0.2V or CE2 ≤ 0.2V, VIN ≥ VCC – 0.2V or VIN ≤ 0.2V Test Condition Min 2.0 10 0 tRC§ 15 200 300 Typ.* VCC= 2.0V 3.0V Max VCC= 2.0V 3.0V Unit V µA ns ns *TA = +25°C § tRC = Read Cycle Time † This parameter is guaranteed but not tested. DATA RETENTION WAVEFORM Document # SRAM120 REV C Page 3 of 12 P4C163/163L AC ELECTRICAL CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Symbol tRC tAA tAC tOH tLZ tHZ tOE tOLZ tOHZ tPU tPD Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable Low to Data Valid Output Enable Low to Low Z Output Enable High to High Z Chip Enable to Power Up Time Chip Disable to Power Down Time -25 25 25 25 3 3 10 13 3 12 0 20 0 3 3 3 35 -35 45 35 35 3 3 15 18 3 15 0 20 -45 Min Max Min Max Min Max 45 45 Unit ns ns ns ns ns 20 20 ns ns ns 20 ns ns 25 ns READ CYCLE NO. 1 (OE CONTROLLED)(5) Notes: 5. WE is HIGH for READ cycle. 6. CE1 is LOW, CE2 is HIGH and OE is LOW for READ cycle. 7. ADDRESS must be valid prior to, or coincident with CE1 transition LOW and CE2 transition HIGH. 8. Transition is measured ± 200mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. Document # SRAM120 REV C Page 4 of 12 P4C163/163L READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6) READ CYCLE NO. 3 (CE1, CE2 CONTROLLED)(5,7,10) Notes: 9. READ Cycle Time is measured from the last valid address to the first transitioning address. 10. Transitions caused by a chip enable control have similar delays irrespective of whether CE1 or CE2 causes them. Document # SRAM120 REV C Page 5 of 12 P4C163/163L AC CHARACTERISTICS—WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) -25 Symbol tWC tCW tAW tAS tWP tAH tDW tDH tWZ tOW Parameter Write Cycle Time Chip Enable Time to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Address Hold Time Data Valid to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write 3 25 18 18 0 18 0 13 0 10 5 35 25 25 0 20 0 15 0 -35 45 33 33 0 25 0 20 0 14 5 -45 Unit ns ns ns ns ns ns ns ns 18 ns ns Min Max Min Max Min Max WRITE CYCLE NO. 1 (WE CONTROLLED)(11) Notes: 11. CE1 and WE must be LOW, and CE2 HIGH for WRITE cycle. 12. OE is LOW for this WRITE cycle to show tWZ and tOW. 13. If CE1 goes HIGH, or CE2 goes LOW, simultaneously with WE HIGH, the output remains in a low impedance state. 14. Write Cycle Time is measured from the last valid address to the first transitioning address. Document # SRAM120 REV C Page 6 of 12 P4C163/163L TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(11) AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Reference Level Output Load GND to 3.0V 3ns 1.5V 1.5V See Figures 1 and 2 TRUTH TABLE Mode Standby Standby DOUT Disabled Read Write CE1 H X L L L CE2 X L H H H OE X X H L X WE X X H H L I/O High Z High Z High Z DOUT DIN Power Standby Standby Active Active Active 1527 10 Figure 1. Output Load * including scope and test fixture. Note: Because of the ultra-high speed of the P4C163/L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency Figure 2. Thevenin Equivalent capacitor is also required between VCC and ground. To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). Document # SRAM120 REV C Page 7 of 12 P4C163/163L ORDERING INFORMATION SELECTION GUIDE The P4C163/L is available in the following temperature, speed and package options. The P4C163L is only available over the military temperature range. Temperature Range Commercial Miliitary Temperature Military Processed* Package Plastic DIP Plastic SOJ Side Brazed DIP LCC CERPACK Side Brazed DIP LCC CERPACK Speed 25 -25PC -25JC -25CM -25LM -25FM -25CMB -25LMB -25FMB 35 -35PC -35JC -35CM -35LM -35FM -35CMB -35LMB -35FMB 45 N/A N/A -45CM -45LM -45FM -45CMB -45LMB -45FMB * Military temperature range with MIL-STD-883, Class B processing. N/A = Not available Document # SRAM120 REV C Page 8 of 12 P4C163/163L Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2 C5 28 (300 mil) Min Max 0.225 0.014 0.026 0.045 0.065 0.008 0.018 1.485 0.240 0.310 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.070 0.005 0.005 - SIDE BRAZED DUAL IN-LINE PACKAGE Pkg # # Pins Symbol A b c D E e k L Q S S1 F4 28 Min Max 0.060 0.090 0.015 0.022 0.004 0.009 0.730 0.330 0.380 0.050 BSC 0.005 0.018 0.250 0.370 0.026 0.045 0.085 0.005 - CERPACK CERAMIC FLAT PACKAGE Document # SRAM120 REV C Page 9 of 12 P4C163/163L Pkg # # Pins Symbol A A1 b C D e E E1 E2 Q J5 28 (300 mil) Min Max 0.120 0.148 0.078 0.014 0.020 0.007 0.011 0.700 0.730 0.050 BSC 0.335 BSC 0.292 0.300 0.267 BSC 0.025 - SOJ SMALL OUTLINE IC PACKAGE Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L2 ND NE L5 28 Min Max 0.060 0.075 0.050 0.065 0.022 0.028 0.342 0.358 0.200 BSC 0.100 BSC 0.358 0.540 0.560 0.400 BSC 0.200 BSC 0.558 0.050 BSC 0.040 REF 0.020 REF 0.045 0.055 0.045 0.055 0.075 0.095 5 9 RECTANGULAR LEADLESS CHIP CARRIER Document # SRAM120 REV C Page 10 of 12 P4C163/163L Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L α P5 28 (300 mil) Min Max 0.210 0.014 0.023 0.045 0.070 0.008 0.014 1.345 1.400 0.270 0.300 0.300 0.380 0.100 BSC 0.430 0.115 0.150 0° 15° PLASTIC DUAL IN-LINE PACKAGE Document # SRAM120 REV C Page 11 of 12 P4C163/163L REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: REV. OR A B C ISSUE DATE 1997 Oct-05 Jul-06 Aug-06 SRAM120 P4C164 / P4C163L ULTRA HIGH SPEED 8K x 9 STATIC CMOS RAMS ORIG. OF CHANGE DAB JDB JDB JDB DESCRIPTION OF CHANGE New Data Sheet Change logo to Pyramid Added Lead-Free Designation Updated SOJ package information Document # SRAM120 REV C Page 12 of 12