P4C170-70DC

P4C168, P4C169, P4C170 ULTRA HIGH SPEED 4K x 4 STATIC CMOS RAMS FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) – 12/15/20/25/35ns (Commercial) – 20/25/35/45/55/70ns (P4C168 Military) Low Power Operation (Commercial) – 715 mW Active – 193 mW Standby (TTL Input) P4C168 – 83 mW Standby (CMOS Input) P4C168 Single 5V±10% Power Supply Fully TTL Compatible, Common I/O Ports Three Options – P4C168 Low Power Standby Mode – P4C169 Fast Chip Select Control – P4C170 Fast Chip Select, Output Enable Controls Standard Pinout (JEDEC Approved) – P4C168: 20-pin DIP, SOJ, LCC, SOIC, CERPACK, and Flat Pack – P4C169: 20-pin DIP and SOIC – P4C170: 22-pin DIP DESCRIPTION The P4C168, P4C169 and P4C170 are a family of 16,384-bit ultra high-speed static RAMs organized as 4K x 4. All three devices have common input/output ports.The P4C168 enters the standby mode when the chip enable (CE) control goes HIGH; with CMOS input levels, power consumption is only 83mW in this mode. Both the P4C169 and the P4C170 offer a fast chip select access time that is only 67% of the address access time. In addition, the P4C170 includes an output enable (OE) control to eliminate data bus contention. The RAMs operate from a single 5V ± 10% tolerance power supply. Access times as fast as 12 nanoseconds are available, permitting greatly enhanced system operating speeds. CMOS is used to reduce power consumption to a low 715 mW active, 193 mW standby. The P4C168 and P4C169 are available in 20-pin (P4C170 in 22-pin) 300 mil DIP packages providing excellent board level densities. The P4C168 is also available in 20pin 300 mil SOIC, SOJ, CERPACK, and Flat Pack packages. The P4C169 is also available in a 20-pin 300 mil SOIC package. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS P4C168 P4C169 DIP (P2, C6, D2) DIP (P2) SOIC (S2) SOIC (S2) SOJ (J2) CERPACK (F2) SOLDER SEAL FLAT PACK (FS-2) P4C170 DIP (P3) Document # SRAM107 REV A 1 Revised October 2005 P4C168, P4C169, P4C170 MAXIMUM RATINGS(1) Symbol VCC Parameter Power Supply Pin with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Temperature Value – 0.5 to +7 – 0.5 to VCC + 0.5 –55 to +125 Unit V Symbol TBIAS TSTG PT IOUT Parameter Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value – 55 to +125 – 65 to +150 1.0 50 Unit °C °C W mA VTERM TA V °C RECOMMENDED OPERATING CONDITIONS Grade(2) Commercial Military Ambient Temp 0°C to 70°C –55°C to +125°C Gnd 0V 0V VCC 5.0V ± 10% 5.0V ± 10% CAPACITANCES(4) (VCC = 5.0V, TA = 25°C, f = 1.0MHz) Symbol CIN COUT Parameter Input Capacitance Conditions Typ. Unit VIN = 0V 5 7 pF pF Output Capacitance VOUT= 0V DC ELECTRICAL CHARACTERISTICS Symbol VIH VIL VHC VLC VCD VOL VOLC VOH VOHC ILI ILO ICC ISB Parameter Input High Voltage Input Low Voltage CMOS Input High Voltage CMOS Input Low Voltage Input Clamp Diode Voltage Output Low Voltage (TTL Load) Output Low Voltage (CMOS Load) Output High Voltage (TTL Load) Output High Voltage (CMOS Load) Input Leakage Current Output Leakage Current Dynamic Operating Current Standby Power Supply Current (TTL Input Levels) P4C168 only Standby Power Supply Current (CMOS Input Levels) P4C168 only VCC = Min., IIN = –18 mA IOL = +8 mA, VCC = Min. IOLC = +100 µA, VCC = Min. IOH = –4 mA, VCC = Min. IOHC = –100 µA, VCC = Min. VCC = Max., VIN = GND to VCC VCC = Max., CS = VIH, VOUT = GND to VCC Mil. Comm’l Mil. Comm’l 2.4 VCC –0.2 –10 –5 –10 –5 ___ ___ Test Conditions P4C168/169/170 Min 2.2 –0.5(3) VCC –0.2 –0.5(3) Max VCC +0.5 0.8 VCC +0.5 0.2 –1.2 0.4 0.2 Unit V V V V V V V V V +10 +5 +10 +5 130 35 µA µA mA mA VCC = Max., f = Max., Outputs Open CE ≥ VIH, VCC = Max., f = Max., Outputs Open CE ≥ VHC, VCC = Max., f = 0, Outputs Open VIN ≤ VLC or VIN ≥ VHC ISB1 ___ 15 mA Document # SRAM107 REV A Page 2 of 15 P4C168, P4C169, P4C170 AC CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym tRC tAA tAC § tAC ‡ Parameter Read Cycle Time Address Access Time Chip Enable Access Time Chip Select Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable to Data Valid Output Enable to Output in Low Z Output Disable to Output in High Z Read Command Setup Time Read Command Hold Time Chip Enable to Power Up Time Chip Disable to Power Down Time -12 -15 -20 -25 -35 Min Max Min Max Min Max Min Max Min Max 12 12 12 8 2 2 7 8 0 6 0 0 0 12 0 0 0 15 0 7 0 0 0 20 2 2 8 10 0 9 0 0 0 25 15 15 15 9 2 2 9 12 0 11 0 0 0 35 20 20 20 12 2 2 10 15 0 15 25 25 25 15 2 2 15 15 35 35 35 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns tOH tLZ ‡ tHZ † tOE † tOLZ † tOHZ tRCS tRCH tPU § tPD § † AC CHARACTERISTICS—READ CYCLE (CONTINUED) (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym t RC t AA t AC § t OH t LZ ‡ t HZ † Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z Read Command Setup Time Read Command Hold Time Chip Enable to Power Up Time Chip Disable to Power Down Time -45 -55 -70 Min Max Min Max Min Max 45 45 45 2 2 25 0 0 0 45 0 0 0 55 2 2 25 0 0 0 70 55 55 55 2 2 30 70 70 70 Unit ns ns ns ns ns ns ns ns ns ns t RCS t RCH t PU § t PD § § P4C168 only † P4C170 only ‡ Chip Select/Deselect for P4C169 and P4C170 Document # SRAM107 REV A Page 3 of 15 P4C168, P4C169, P4C170 TIMING WAVEFORM OF READ CYCLE NO. 1 (ADDRESS CONTROLLED)(5,6) Notes: 5. WE is HIGH for READ cycle. 6. CE/CS and OE are LOW for READ cycle. TIMING WAVEFORM OF READ CYCLE NO. 2 (CE/CS CONTROLLED)(5,7) TIMING WAVEFORM OF READ CYCLE NO. 3—P4C170 ONLY (OE CONTROLLED)(5) Notes: 7. ADDRESS must be valid prior to, or coincident with CE/CS transition low. For Fast CS, tAA must still be met. 8. Transition is measured ±200mV from steady state voltage prior to change, with loading as specified in Figure 1. 9. Read Cycle Time is measured from the last valid address to the first transitioning address. Document # SRAM107 REV A Page 4 of 15 P4C168, P4C169, P4C170 AC ELECTRICAL CHARACTERISTICS - WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym tWC tcw tAW tAS tWP tAH tDW tDH tWZ tOW Write Cycle Time Chip Enable Time to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Address Hold Time Data Valid to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write 0 Parameter -12 -15 -20 -25 -35 Min Max Min Max Min Max Min Max Min Max 12 12 12 0 12 0 7 0 4 0 15 15 15 0 15 0 8 0 5 0 18 18 18 0 18 0 10 0 6 0 20 20 20 0 20 0 10 0 7 0 30 30 30 0 30 0 15 0 13 Unit ns ns ns ns ns ns ns ns ns ns AC ELECTRICAL CHARACTERISTICS - WRITE CYCLE (CONTINUED) (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym tWC tcw tAW tAS tWP tAH tDW tDH tWZ tOW Write Cycle Time Chip Enable Time to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Address Hold Time Data Valid to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write 0 Parameter -45 -55 -70 Min Max Min Max Min Max 45 40 40 0 40 0 20 3 20 0 55 50 50 0 50 0 20 3 25 0 70 60 60 0 60 0 25 3 30 Unit ns ns ns ns ns ns ns ns ns ns Document # SRAM107 REV A Page 5 of 15 P4C168, P4C169, P4C170 TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(10) Notes: 10. CE/CS and WE must be LOW for WRITE cycle. 11. If CE/CS goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state. 12. Write Cycle Time is measured from the last valid address to the first transitioning address. TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE/CS CONTROLLED)(10) TRUTH TABLES P4C168 (P4C169) Mode Standby (Deselect) Read Write CE (CS) H L L WE X H L Output High Z DOUT High Z P4C170 Mode Deselect Read Output Inhibit Write CE H L L L WE X H H L OE X L H X Output High Z DOUT High Z High Z Document # SRAM107 REV A Page 6 of 15 P4C168, P4C169, P4C170 AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Reference Level Output Load GND to 3.0V 3ns 1.5V 1.5V See Figures 1 and 2 Figure 1. Output Load * including scope and test fixture. Note: Because of the ultra-high speed of the P4C168, P4C169 AND P4C170 care must be taken when testing these devices; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long highinductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A high frequency capacitor of 0.01 µF is also required between VCC and ground. Figure 2. Thevenin Equivalent To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). LCC PIN CONFIGURATION LCC (L9) Document # SRAM107 REV A Page 7 of 15 P4C168, P4C169, P4C170 ORDERING INFORMATION SELECTION GUIDE The P4C168, P4C169 and P4C170 are available in the following temperature, speed and package options. Temperature Range Commercial Temperature Package Plastic DIP Plastic SOIC† Plastic SOJ†† LCC Military Temperature (P4C168 only) Speed 12 -12PC -12SC -12JC N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 15 -15PC -15SC -15JC -15LM -15DM -15CM -15FM -15FSM -15LMB -15DMB -15CMB -15FMB -15FSMB 20 -20PC -20SC -20JC -20LM -20DM -20CM -20FM -20FSM -20LMB -20DMB -20CMB -20FMB -20FSMB 25 -25PC -25SC -25JC -25LM -25DM -25CM -25FM -25FSM -25LMB -25DMB -25CMB -25FMB -25FSMB 35 N/A N/A N/A -35LM -35DM -35CM -35FM -35FSM -35LMB -35DMB -35CMB -35FMB -35FSMB CERDIP Side Brazed DIP CERPACK Solder Seal Flat Pack LCC Military Processed* (P4C168 only) CERDIP Side Brazed DIP CERPACK Solder Seal Flat Pack † P4C168 and P4C169 only. †† P4C168 * Military temperature range with MIL-STD-883, Class B processing. N/A = Not available Document # SRAM107 REV A Page 8 of 15 P4C168, P4C169, P4C170 SELECTION GUIDE (CONTINUED) Temperature Range LCC Military Temperature (P4C168 only) Package Speed 45 -45LM -45DM -45CM -45FM -45FSM -45LMB -45DMB -45CMB -45FMB -55FSMB 55 -55LM -55DM -55CM -55FM -55FSM -55LMB -55DMB -55CMB -55FMB -55FSMB 70 -70LM -70DM -70CM -70FM -70FSM -70LMB -70DMB -70CMB -70FMB -70FSMB CERDIP Side Brazed DIP CERPACK Solder Seal Flat Pack LCC Military Processed* (P4C168 only) CERDIP Side Brazed DIP CERPACK Solder Seal Flat Pack * Military temperature range with MIL-STD-883, Class B processing. Document # SRAM107 REV A Page 9 of 15 P4C168, P4C169, P4C170 Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2 C6 20 (300 mil) Min Max 0.200 0.014 0.026 0.045 0.065 0.008 0.018 1.060 0.220 0.310 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.070 0.005 0.005 - SIDE BRAZED DUAL IN-LINE PACKAGE Pkg # # Pins Symbol A b c D E e k L Q S S1 F2 20 Min Max 0.060 0.090 0.015 0.022 0.004 0.009 0.530 0.305 0.355 0.050 BSC 0.005 0.018 0.250 0.370 0.026 0.045 0.085 0.005 - CERPACK CERAMIC FLAT PACKAGE Document # SRAM107 REV A Page 10 of 15 P4C168, P4C169, P4C170 Pkg # # Pins Symbol A b b1 c c1 D E E1 E2 E3 e k L Q S1 M N FS-2 20 Min Max 0.045 0.115 0.015 0.022 0.015 0.019 0.004 0.009 0.004 0.006 0.540 0.245 0.300 0.330 0.130 0.030 0.050 BSC 0.008 0.015 0.250 0.370 0.026 0.045 0.000 0.0015 20 SOLDER SEAL FLAT PACKAGE Pkg # # Pins Symbol A A1 b C D e E E1 E2 Q J2 20 (300 mil) Min Max 0.120 0.140 0.080 0.014 0.020 0.008 0.013 0.496 0.512 0.050 BSC 0.335 0.347 0.292 0.300 0.267 BSC 0.025 - SOJ SMALL OUTLINE IC PACKAGE Document # SRAM107 REV A Page 11 of 15 P4C168, P4C169, P4C170 Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L2 ND NE L9 20 Min Max 0.060 0.075 0.050 0.066 0.022 0.028 0.280 0.305 0.150 BSC 0.075 BSC 0.305 0.420 0.440 0.250 BSC 0.125 BSC 0.440 0.050 BSC 0.020 REF 0.010 REF 0.045 0.055 0.045 0.055 0.075 0.098 4 6 RECTANGULAR LEADLESS CHIP CARRIER Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L P2 20 (300 mil) Min Max 0.210 0.015 0.014 0.022 0.045 0.070 0.008 0.014 0.980 1.060 0.240 0.280 0.300 0.325 0.100 BSC 0.430 0.115 0.150 0° 15° PLASTIC DUAL IN-LINE PACKAGE (P4C168, P4C169) α Document # SRAM107 REV A Page 12 of 15 P4C168, P4C169, P4C170 Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L P3 22 (300 Mil) Min Max 0.210 0.015 0.014 0.022 0.045 0.070 0.008 0.014 1.145 1.165 0.240 0.280 0.300 0.325 0.100 BSC 0.430 0.115 0.150 0° 15° PLASTIC DUAL IN-LINE PACKAGE (P4C170) α Pkg # # Pins Symbol A A1 b2 C D e E H h L S2 20 (300 mil) Min Max 0.093 0.104 0.004 0.012 0.013 0.020 0.009 0.012 0.496 0.511 0.050 BSC 0.291 0.299 0.394 0.419 0.010 0.029 0.016 0.050 0° 8° SOIC/SOP SMALL OUTLINE IC PACKAGE α Document # SRAM107 REV A Page 13 of 15 P4C168, P4C169, P4C170 Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 D2 20 (300 mil) Min Max 0.200 0.014 0.026 0.045 0.065 0.008 0.018 1.060 0.220 0.310 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.070 0.005 0° 15° CERDIP DUAL IN-LINE PACKAGE α Document # SRAM107 REV A Page 14 of 15 P4C168, P4C169, P4C170 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: REV. OR A ISSUE DATE 1997 Oct-05 SRAM107 P4C168, P4C169, P4C170 ULTRA HIGH SPEED 4K x 4 STATIC CMOS RAMS ORIG. OF CHANGE DAB JDB DESCRIPTION OF CHANGE New Data Sheet Change logo to Pyramid Document # SRAM107 REV A Page 15 of 15