P4C198-15JMB

P4C198/P4C198L, P4C198A/P4C198AL ULTRA HIGH SPEED 16K x 4 STATIC CMOS RAMS FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) – 10/12/15/20/25 ns (Commercial) – 12/15/20/25/35 ns (Industrial) – 15/20/25/35/45 ns (Military) Low Power Operation (Commercial/Military) 5V ± 10% Power Supply Data Retention, 10 µA Typical Current from 2.0V P4C198L/198AL (Military) Output Enable & Chip Enable Control Functions – Single Chip Enable P4C198 – Dual Chip Enable P4C198A Common Inputs and Outputs Fully TTL Compatible Inputs and Outputs Standard Pinout (JEDEC Approved) – 24-Pin 300 mil DIP – 24-Pin 300 mil SOJ – 28-Pin 350 x 550 mil LCC DESCRIPTION The P4C198/L and P4C198A/L are 65,536-bit ultra highspeed static RAMs organized as 16K x 4. Each device features an active low Output Enable control to eliminate data bus contention. The P4C198/L also have an active low Chip Enable (the P4C198A/L have two Chip Enables, both active low) for easy system expansion. The CMOS memories require no clocks or refreshing and have equal access and cycle times. Inputs are fully TTL-compatible. The RAMs operate from a single 5V ± 10% tolerance power supply. Data integrity is maintained with supply voltages down to 2.0V. Current drain is typically 10 µA from a 2.0V supply. Access times as fast as 12 nanoseconds are available, permitting greatly enhanced system operating speeds. CMOS is used to reduce power consumption to a low 715 mW active, 193 mW standby. The P4C198/L and P4C198A/L are available in 24-pin 300 mil DIP and SOJ, and 28-pin 350 x 550 mil LCC packages providing excellent board level densities. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS DIP (P4, C4, D4), SOJ (J4) P4C198 (P4C198A) LCC (L5) P4C198 (P4C198A) Document # SRAM113 REV A 1 Revised October 2005 P4C198/198L, P4C198A/198AL MAXIMUM RATINGS(1) Symbol VCC Parameter Power Supply Pin with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Temperature Value –0.5 to +7 –0.5 to VCC +0.5 –55 to +125 Unit V Symbol TBIAS TSTG PT IOUT Parameter Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value –55 to +125 –65 to +150 1.0 50 Unit °C °C W mA VTERM TA V °C RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade(2) Military Ambient Temperature GND 0V 0V 0V VCC 5.0V ± 10% 5.0V ± 10% 5.0V ± 10% CAPACITANCES(4) VCC = 5.0V, TA = 25°C, f = 1.0MHz Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions Typ. Unit VIN = 0V VOUT = 0V 5 7 pF pF –55°C to +125°C 0°C to +70°C Commercial –40°C to +85°C Industrial DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Symbol VIH VIL V HC VLC V CD VOL VOH ILI ILO ISB Parameter Input High Voltage Input Low Voltage CMOS Input High Voltage CMOS Input Low Voltage Input Clamp Diode Voltage Output Low Voltage (TTL Load) Output High Voltage (TTL Load) Input Leakage Current Output Leakage Current VCC = Min., IIN = –18 mA IOL = +10 mA, VCC = Min. IOL = +8 mA, VCC = Min. IOH = –4 mA, VCC = Min. VCC = Max. VIN = GND to VCC VOUT = GND to VCC VCC = Max., CE = VIH, Mil. Ind./Com’l. Mil. Ind./Com’l. Test Conditions P4C198 / 198A Min Max 2.2 –0.5(3) –0.5 (3) P4C198L / 198AL Unit Min Max VCC +0.5 2.2 VCC +0.5 V 0.8 0.2 –1.2 –0.5(3) –0.5 (3) 0.8 0.2 –1.2 V V V V V V V VCC –0.2 VCC +0.5 VCC –0.2 VCC +0.5 0.5 0.4 2.4 –10 –5 –10 –5 ___ ___ ___ ___ +10 +5 +10 +5 40 35 20 15 0.5 0.4 2.4 –5 n/a –5 n/a ___ ___ ___ ___ +5 n/a +5 n/a 40 n/a 1.5 n/a µA µA mA CE1, CE2 ≥ VIH Mil. Standby Power Supply VCC = Max ., Ind./Com’l. Current (TTL Input Levels) f = Max., Outputs Open Standby Power Supply Current (CMOS Input Levels) CE1, CE2 ≥ VIH Mil. VCC = Max., Ind./Com’l. f = 0, Outputs Open VIN ≤ VLC or VIN ≥ VHC mA ISB1 n/a = Not Applicable Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM ratingconditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. Document # SRAM113 REV A Page 2 of 13 P4C198/198L, P4C198A/198AL POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol Parameter Temperature Range Commercial Industrial Military 198: CE = VIL, OE = VIH 198A: CE1 = VIL, CE2 = VIL. OE = VIH –10 180 N/A N/A –12 170 180 N/A –15 160 170 170 –20 155 160 160 –25 150 155 155 –35 N/A 150 150 –45 N/A N/A 145 Unit mA mA mA ICC Dynamic Operating Current* *VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. DATA RETENTION CHARACTERISTICS (P4C198L/P4C198AL Military Temperature Only) Symbol VDR ICCDR tCDR tR† *TA = +25°C § † Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Test Condition Min 2.0 Typ.* VCC= 2.0V 3.0V 10 15 Max VCC= 2.0V 3.0V 600 900 Unit V µA ns ns CE ≥VCC – 0.2V, VIN ≥ VCC – 0.2V or VIN ≤ 0.2V 0 tRC§ tRC = Read Cycle Time This parameter is guaranteed but not tested. DATA RETENTION WAVEFORM Document # SRAM113 REV A Page 3 of 13 P4C198/198L, P4C198A/198AL AC CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) -10 Sym. tRC tAA tAC tOH tLZ tHZ tOE tOLZ Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable Low to Data Valid Output Enable to Output in Low Z 2 6 0 10 0 2 2 6 6 2 10 10 10 2 2 12 -12 -15 15 12 12 2 2 7 7 2 7 0 12 15 9 0 8 9 2 15 15 2 2 20 -20 25 20 20 2 2 10 12 2 9 0 20 -25 35 25 25 2 2 10 15 2 10 0 25 -35 45 35 35 2 2 14 25 2 14 0 35 -45 ns 45 45 ns ns ns ns 15 30 ns ns ns 15 ns ns 45 ns Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit tOHZ Output Disable to Output in High Z tPU tPD Chip Enable to Power Up Time Chip Disable to Power Down Time READ CYCLE NO.1 (OE controlled)(5) Notes: 5. WE is HIGH for READ cycle. Document # SRAM113 REV A Page 4 of 13 P4C198/198L, P4C198A/198AL READ CYCLE NO. 2 (ADDRESS Controlled)(5,6) READ CYCLE NO. 3 (CE(12) Controlled)(5,7,8) Notes: 6. CE (CE1 CE2 for P4C198A/L) and OE are LOW READ cycle. 7. OE is LOW for the cycle. 8. ADDRESS must be valid prior to, or coincident with CE (CE1 and CE2 for P4C198A/L) transition LOW. 9. Transition is measured ± 200mV from steady state voltage prior to change, with loading as specified in Figure 1. 10. Read Cycle Time is measured from the last valid address to the first transitioning address. 11. Transitions caused by a chip enable control have similar delays irrespective of whether CE1 or CE2 causes them (P4C198A/L). 12. CE1, CE2 for P4C198A/L. Document # SRAM113 REV A Page 5 of 13 P4C198/198L, P4C198A/198AL AC CHARACTERISTICS—WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. tWC tCW tAW tAS tWP tAH Parameter Write Cycle Time Chip Enable Time to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Address Hold Time from End of Write Data Valid to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write 3 10 7 8 0 8 0 -10 12 8 8 0 9 0 -12 -15 13 10 10 0 10 0 15 15 15 0 12 0 -20 20 20 20 0 20 0 -25 30 30 25 0 25 0 -35 40 35 35 0 35 0 -45 Unit ns ns ns ns ns ns Min Max Min Max Min Max Min Max Min Max Min Max Min Max tDW tDH tWZ tOW 7 0 7 6 0 6 3 7 0 7 3 10 0 8 3 13 0 10 3 15 0 10 3 20 0 15 3 ns ns ns ns WRITE CYCLE NO. 1 (With OE high) OE Document # SRAM113 REV A Page 6 of 13 P4C198/198L, P4C198A/198AL WRITE CYCLE NO. 2 (WE CONTROLLED)(13,14) 1520 08 WRITE CYCLE NO. 3 (CE(12) CONTROLLED)(13,14) Notes: 13. CE (CE1, CE2 for P4C198A/L) and WE must be LOW for WRITE cycle. 14. OE is LOW for this WRITE cycle. 15. If CE (CE1 or CE2 for P4C198A/L) goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state. 16. Write Cycle Time is measured from the last valid address to the first transitioning address. Document # SRAM113 REV A Page 7 of 13 P4C198/198L, P4C198A/198AL TRUTH TABLES P4C198/L CE H L L L WE X H H L OE X H L X Mode Standby Output Inhibit READ WRITE Output High Z High Z DOUT DIN P4C198A/L CE1 H X L L L CE2 X H L L L WE X X H H L OE X X H L X Mode Standby Standby Output Inhibit READ WRITE Output High Z High Z High Z DOUT DIN AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Reference Level Output Load GND to 3.0V 3ns 1.5V 1.5V See Figures 1 and 2 Figure 1. Output Load * including scope and test fixture. Note: Because of the ultra-high speed of the P4C198/L and P4C198A/L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high Figure 2. Thevenin Equivalent frequency capacitor is also required between VCC and ground. To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). Document # SRAM113 REV A Page 8 of 13 P4C198/198L, P4C198A/198AL ORDERING INFORMATION SELECTION GUIDE The P4C198 and P4C198A are available in the following temperature, speed and package options. Temperature Range Commercial Industrial Military Temperature Military Processed* Package Plastic DIP Plastic SOJ Plastic DIP Plastic SOJ Side Brazed DIP CERDIP LCC Side Brazed DIP CERDIP LCC Speed (ns) 10 -10PC -10JC N/A N/A N/A N/A N/A N/A N/A N/A 12 -12PC -12JC -12PI -12JI N/A N/A N/A N/A N/A N/A 15 -15PC -15JC -15PI -15JI -15CM -15DM -15LM -15CMB -15DMB -15LMB 20 -20PC -20JC -20PI -20JI -20CM -20DM -20LM -20CMB -20DMB -20LMB 25 -25PC -25JC -25PI -25JI -25CM -25DM -25LM -25CMB -25DMB -25LMB 35 N/A N/A -35PI -35JI -35CM -35DM -35LM -35CMB -35DMB -35LMB 45 N/A N/A N/A N/A -45CM -45DM -45LM -45CMB -45DMB -45LMB * Military temperature range with MIL-STD-883, Class B processing. N/A = Not available Document # SRAM113 REV A Page 9 of 13 P4C198/198L, P4C198A/198AL Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2 C4 24 (300 mil) Min Max 0.200 0.014 0.026 0.045 0.065 0.008 0.018 1.280 0.220 0.310 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.060 0.005 0.005 - SIDE BRAZED DUAL IN-LINE PACKAGE Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 D4 24 (300 mil) Min Max 0.200 0.014 0.026 0.045 0.065 0.008 0.018 1.280 0.220 0.310 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.060 0.005 0° 15° CERDIP DUAL IN-LINE PACKAGE α Document # SRAM113 REV A Page 10 of 13 P4C198/198L, P4C198A/198AL Pkg # # Pins Symbol A A1 b C D e E E1 E2 Q J4 24 (300 mil) Min Max 0.128 0.148 0.082 0.016 0.020 0.007 0.010 0.620 0.630 0.050 BSC 0.335 BSC 0.292 0.300 0.267 BSC 0.025 - SOJ SMALL OUTLINE IC PACKAGE Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L2 ND NE L5 28 Min Max 0.060 0.075 0.050 0.065 0.022 0.028 0.342 0.358 0.200 BSC 0.100 BSC 0.358 0.540 0.560 0.400 BSC 0.200 BSC 0.558 0.050 BSC 0.040 REF 0.020 REF 0.045 0.055 0.045 0.055 0.075 0.095 5 9 RECTANGULAR LEADLESS CHIP CARRIER Document # SRAM113 REV A Page 11 of 13 P4C198/198L, P4C198A/198AL Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L P4 24 (300 Mil) Min Max 0.210 0.015 0.014 0.022 0.045 0.070 0.008 0.014 1.230 1.280 0.240 0.280 0.300 0.325 0.100 BSC 0.430 0.115 0.150 0° 15° PLASTIC DUAL IN-LINE PACKAGE α Document # SRAM113 REV A Page 12 of 13 P4C198/198L, P4C198A/198AL REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: ISSUE DATE 1997 Oct-05 SRAM113 P4C198 / P4C198L, P4C198A / P4C198AL ULTRA HIGH SPEED 16K x 4 STATIC CMOS RAMS REV. OR A ORIG. OF CHANGE DAB JDB DESCRIPTION OF CHANGE New Data Sheet Change logo to Pyramid Document # SRAM113 REV A Page 13 of 13