December 2007
HY[B/I]25D512400C[C/E/F/T](L)
HY[B/I]25D512800C[C/E/F/T](L)
HY[B/I]25D512160C[C/E/F/T](L)
5 1 2 - M b i t D o u b l e - D a t a - R a t e SD R A M
DDR SDRAM
Internet Data Sheet
Rev. 1.41
Date: 2007-12-13
Internet Data Sheet
HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
Revision History: Rev. 1.41, 2007-12
Adapted internet edition
Added IDD values
Previous Revision: Rev. 1.40, 2007-12
Added HYI25D512800CE-5 and HYI25D512800CF-5,Added HYI25D512800CT-6, HYI25D512800CE-6,
HYI25D512800CT-5,HYI25D512800CC-6, HYI25D512800CF-6 and HYI25D512800CC-5
Package Outline Figures updated
Previous Revision: Rev. 1.31, 2006-09
Qimonda update
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Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
techdoc@qimonda.com
qag_techdoc_rev411 / 3.31 QAG / 2007-01-22
03292006-3TFJ-HNV3
2
Date: 2007-12-13
Internet Data Sheet
HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
1
Overview
This chapter gives an overview of the 512-Mbit Double-Data-Rate SDRAM product family and describes its main
characteristics.
1.1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Features
Double data rate architecture: two data transfers per clock cycle
Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
DQS is edge-aligned with data for reads and is center-aligned with data for writes
Differential clock inputs (CK and CK)
Four internal banks for concurrent operation
Data mask (DM) for write data
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
Programmable CAS latency: 2, 2.5, 3
Programmable burst lengths: 2, 4, or 8
Auto Precharge option for each burst access
Auto Refresh and Self Refresh Modes
RAS-lockout supported tRAP = tRCD
7.8 μs Maximum Average Periodic Refresh Interval
2.5 V (SSTL_2 compatible) I/O
VDD = 2.5 V ± 0.2 V
VDDQ = 2.5 V ± 0.2 V
Packages: PG-TSOPII-66, PG-TFBGA-60, P-TSOPII-66, P-TFBGA-60
RoHS Compliant Products
TABLE 1
Performance
Part Number Speed Code
Speed Grade
Component
Max. Clock Frequency
@CL3
@CL2.5
@CL2
Rev. 1.41, 2007-12
03292006-3TFJ-HNV3
fCK3
fCK2.5
fCK2
–5
–6
Unit
DDR400B
DDR333B
—
200
166
MHz
166
166
MHz
133
133
MHz
3
Date: 2007-12-13
Internet Data Sheet
HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
1.2
Description
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write
command. The address bits registered coincident with the
Active command are used to select the bank and row to be
accessed. The address bits registered coincident with the
Read or Write command are used to select the bank and the
starting column location for the burst access.
The DDR SDRAM provides for programmable Read or Write
burst lengths of 2, 4 or 8 locations. An Auto Precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst access. As
with standard SDRAMs, the pipelined, multibank architecture
of DDR SDRAMs allows for concurrent operation, thereby
providing high effective bandwidth by hiding row precharge
and activation time.
An auto refresh mode is provided along with a power-saving
power-down mode. All inputs are compatible with the Industry
Standard for SSTL_2. All outputs are SSTL_2, Class II
compatible.
Note: The functionality described and the timing
specifications included in this data sheet are for the
DLL Enabled mode of operation.
The 512-Mbit is a high-speed CMOS, dynamic randomaccess memory containing 536, 870, 912 bits. It is internally
configured as a quad-bank DRAM.
The 512-Mbit Double-Data-Rate SDRAM uses a doubledata-rate architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n prefetch
architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access for the 512-Mbit Double-Data-Rate SDRAM
effectively consists of a single 2n-bit wide, one clock cycle
data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers
at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads and
by the memory controller during Writes. DQS is edge-aligned
with data for Reads and center-aligned with data for Writes.
The 512-Mbit Double-Data-Rate SDRAM operates from a
differential clock (CK and CK; the crossing of CK going HIGH
and CK going LOW is referred to as the positive edge of CK).
Commands (address and control signals) are registered at
every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
Rev. 1.41, 2007-12
03292006-3TFJ-HNV3
4
Date: 2007-12-13
Internet Data Sheet
HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type1)
Org. Speed
CAS-RCD-RP
Latencies2)3)4)
Clock (MHz) Package
Note5)
Standard Temperature Range (0 °C - +85 °C)
DDR400B( 3-3-3)
HYB25D512160CF-5
×16
DDR400B
3-3-3
200
PG-TFBGA-60
HYB25D512160CFL-5
×16
DDR400B
3-3-3
200
PG-TFBGA-60
HYB25D512400CE-5
×4
DDR400B
3-3-3
200
PG-TSOPII-66
HYB25D512400CFL-5
×4
DDR400B
3-3-3
200
PG-TFBGA-60
HYB25D512800CFL-5
×8
DDR400B
3-3-3
200
PG-TFBGA-60
HYB25D512800CEL-5
×8
DDR400B
3-3-3
200
PG-TSOPII-66
HYB25D512160CE-5
×16
DDR400B
3-3-3
200
PG-TSOPII-66
HYB25D512400CF-5
×4
DDR400B
3-3-3
200
PG-TFBGA-60
HYB25D512800CE-5
×8
DDR400B
3-3-3
200
PG-TSOPII-66
HYB25D512800CF-5
×8
DDR400B
3-3-3
200
PG-TFBGA-60
HYB25D512160CEL-6
×16
DDR333B
2.5-3-3
166
PG-TSOPII-66
HYB25D512160CF-6
×16
DDR333B
2.5-3-3
166
PG-TFBGA-60
HYB25D512160CFL-6
×16
DDR333B
2.5-3-3
166
PG-TFBGA-60
HYB25D512400CE-6
×4
DDR333B
2.5-3-3
166
PG-TSOPII-66
HYB25D512400CFL-6
×4
DDR333B
2.5-3-3
166
PG-TFBGA-60
HYB25D512800CEL-6
×8
DDR333B
2.5-3-3
166
PG-TSOPII-66
HYB25D512800CFL-6
×8
DDR333B
2.5-3-3
166
PG-TFBGA-60
HYB25D512405CF-6
×4
DDR333B
2.5-3-3
166
PG-TFBGA-60
HYB25D512160CE-6
×16
DDR333B
2.5-3-3
166
PG-TSOPII-66
HYB25D512400CF-6
×4
DDR333B
2.5-3-3
166
PG-TFBGA-60
HYB25D512800CE-6
×8
DDR333B
2.5-3-3
166
PG-TSOPII-66
HYB25D512800CF-6
×8
DDR333B
2.5-3-3
166
PG-TFBGA-60
3-3-3
200
PG-TSOPII-66
DDR333B( 2.5-3-3)
Industrial Temperature Range (–40 °C - +85 °C)
DDR400B( 3-3-3)
HYI25D512160CE-5
×16
HYI25D512160CF-5
×16
DDR400B
3-3-3
200
PG-TFBGA-60
HYI25D512800CE-5
×8
DDR400B
3-3-3
200
PG-TSOPII-66
HYI25D512800CF-5
×8
DDR400B
3-3-3
200
PG-TFBGA-60
HYI25D512160CE-6
×16
DDR333B
2.5-3-3
166
PG-TSOPII-66
HYI25D512160CF-6
×16
DDR333B
2.5-3-3
166
PG-TFBGA-60
HYI25D512800CE-6
×8
DDR333B
2.5-3-3
166
PG-TSOPII-66
HYI25D512800CF-6
×8
DDR333B
2.5-3-3
166
PG-TFBGA-60
DDR400B
DDR333B( 2.5-3-3)
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Nomenclature" of this datasheet.
2) CAS: Column Address Strobe
Rev. 1.41, 2007-12
03292006-3TFJ-HNV3
5
Date: 2007-12-13
Internet Data Sheet
HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
3) RCD: Row Column Delay
4) RP: Row Precharge
5) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
TABLE 3
Ordering Information for non RoHS Compliant Products
Product Type1)
Org.
Speed
CAS-RCD-RP
Latencies2)3)4)
Clock (MHz)
Package
Standard Temperature Range (0 °C - +85 °C)
DDR400B( 3-3-3)
HYB25D512160CT-5
×16
DDR400B
3-3-3
200
P-TSOPII-66
HYB25D512400CC-5
×4
DDR400B
3-3-3
200
P-TFBGA-60
HYB25D512400CT-5
×4
DDR400B
3-3-3
200
P-TSOPII-66
HYB25D512800CC-5
×8
DDR400B
3-3-3
200
P-TFBGA-60
HYB25D512800CT-5
×8
DDR400B
3-3-3
200
P-TSOPII-66
HYB25D512160CC-5
×16
DDR400B
3-3-3
200
P-TFBGA-60
HYB25D512160CC-6
×16
DDR333B
2.5-3-3
166
P-TFBGA-60
HYB25D512160CT-6
×16
DDR333B
2.5-3-3
166
P-TSOPII-66
HYB25D512400CC-6
×4
DDR333B
2.5-3-3
166
P-TFBGA-60
HYB25D512400CT-6
×4
DDR333B
2.5-3-3
166
P-TSOPII-66
HYB25D512800CC-6
×8
DDR333B
2.5-3-3
166
P-TFBGA-60
HYB25D512800CT-6
×8
DDR333B
2.5-3-3
166
P-TSOPII-66
3-3-3
200
P-TFBGA-60
DDR333B( 2.5-3-3)
Industrial Temperature Range (–40 °C - +85 °C)
DDR400B( 3-3-3)
HYI25D512160CC-5
×16
HYI25D512160CT-5
×16
DDR400B
3-3-3
200
P-TSOPII-66
HYI25D512800CC-5
×8
DDR400B
3-3-3
200
P-TFBGA-60
HYI25D512800CT-5
×8
DDR400B
3-3-3
200
P-TSOPII-66
HYI25D512160CC-6
×16
DDR333B
2.5-3-3
166
P-TFBGA-60
HYI25D512160CT-6
×16
DDR333B
2.5-3-3
166
P-TSOPII-66
HYI25D512800CC-6
×8
DDR333B
2.5-3-3
166
P-TFBGA-60
HYI25D512800CT-6
×8
DDR333B
2.5-3-3
166
P-TSOPII-66
DDR400B
DDR333B( 2.5-3-3)
1)
2)
3)
4)
For detailed information regarding Product Type of Qimonda please see chapter "Product Nomenclature" of this datasheet.
CAS: Column Address Strobe
RCD: Row Column Delay
RP: Row Precharge
Rev. 1.41, 2007-12
03292006-3TFJ-HNV3
6
Date: 2007-12-13
Internet Data Sheet
HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
2
Configuration
This chapter contains the chip configuration and block diagrams.
2.1
Configuration for TSOPII-66
The pin configuration of a DDR SDRAM is listed by function in Table 4. The abbreviations used in the Pin#/Buffer Type column
are explained in Table 5 and Table 6 respectively.
TABLE 4
Configuration
Pin#
Name
Pin
Type
Buffer
Type
Function
Clock Signals
45
CK
I
SSTL
Clock Signal
46
CK
I
SSTL
Complementary Clock Signal
44
CKE
I
SSTL
Clock Enable
23
RAS
I
SSTL
Row Address Strobe
22
CAS
I
SSTL
Column Address Strobe
21
WE
I
SSTL
Write Enable
24
CS
I
SSTL
Chip Select
Bank Address Bus
Control Signals
Address Signals
26
BA0
I
SSTL
27
BA1
I
SSTL
29
A0
I
SSTL
30
A1
I
SSTL
31
A2
I
SSTL
32
A3
I
SSTL
35
A4
I
SSTL
36
A5
I
SSTL
37
A6
I
SSTL
38
A7
I
SSTL
39
A8
I
SSTL
40
A9
I
SSTL
28
A10
I
SSTL
AP
I
SSTL
41
A11
I
SSTL
42
A12
I
SSTL
Rev. 1.41, 2007-12
03292006-3TFJ-HNV3
Address Bus
7
Date: 2007-12-13
Internet Data Sheet
HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
Pin#
Name
Pin
Type
Buffer
Type
Function
Data Signal Bus 3:0
Data Signals ×4 Organization
5
DQ0
I/O
SSTL
11
DQ1
I/O
SSTL
56
DQ2
I/O
SSTL
62
DQ3
I/O
SSTL
Data Strobe ×4 Organization
51
DQS
I/O
SSTL
Data Strobe
I
SSTL
Data Mask
Data Signal Bus 7:0
Data Mask ×4 Organization
47
DM
Data Signals × 8 Organization
2
DQ0
I/O
SSTL
5
DQ1
I/O
SSTL
8
DQ2
I/O
SSTL
11
DQ3
I/O
SSTL
56
DQ4
I/O
SSTL
59
DQ5
I/O
SSTL
62
DQ6
I/O
SSTL
65
DQ7
I/O
SSTL
Data Strobe × 8 Organization
51
DQS
I/O
SSTL
Data Strobe
SSTL
Data Mask
Data Signal 15:0
Data Mask × 8 Organization
47
DM
I
Data Signals ×16 Organization
2
DQ0
I/O
SSTL
4
DQ1
I/O
SSTL
5
DQ2
I/O
SSTL
7
DQ3
I/O
SSTL
8
DQ4
I/O
SSTL
10
DQ5
I/O
SSTL
11
DQ6
I/O
SSTL
13
DQ7
I/O
SSTL
54
DQ8
I/O
SSTL
56
DQ9
I/O
SSTL
57
DQ10
I/O
SSTL
59
DQ11
I/O
SSTL
60
DQ12
I/O
SSTL
62
DQ13
I/O
SSTL
63
DQ14
I/O
SSTL
65
DQ15
I/O
SSTL
Rev. 1.41, 2007-12
03292006-3TFJ-HNV3
8
Date: 2007-12-13
Internet Data Sheet
HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
Pin#
Name
Pin
Type
Buffer
Type
Function
Data Strobe ×16 Organization
51
UDQS
I/O
SSTL
Data Strobe Upper Byte
16
LDQS
I/O
SSTL
Data Strobe Lower Byte
Data Mask ×16 Organization
47
UDM
I
SSTL
Data Mask Upper Byte
20
LDM
I
SSTL
Data Mask Lower Byte
VREF
Power Supplies
49
AI
—
I/O Reference Voltage
3, 9, 15, 55, 61 VDDQ
PWR
—
I/O Driver Power Supply
1, 18, 33
VDD
PWR
—
Power Supply
6, 12, 52, 58, 64 VSSQ
PWR
—
Power Supply
34,48, 66
PWR
—
Power Supply
—
Not Connected
VSS
Not Connected ×4 Organization
2, 4, 7, 8, 10,
13, 14, 16, 17,
19, 20, 25, 43,
50, 53, 54, 57,
59, 60, 63, 65
NC
NC
Not Connected × 8 Organization
4, 7, 10, 13, 14, NC
16, 17, 19, 20,
25, 43, 50, 53,
54, 57, 60, 63
NC
—
Not Connected ×16 Organization
14, 17, 19, 25,
43, 50, 53
NC
Rev. 1.41, 2007-12
03292006-3TFJ-HNV3
NC
—
9
Date: 2007-12-13
Internet Data Sheet
HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
TABLE 5
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels
O
Output. Digital levels
I/O
I/O is a bidirectional input/output signal
AI
Input. Analog levels
PWR
Power
GND
Ground
NC
Not Connected
TABLE 6
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminalted Logic (SSTL2)
LV-CMOS
Low Voltage CMOS
CMOS
CMOS Levels
OD
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR
Rev. 1.41, 2007-12
03292006-3TFJ-HNV3
10
Date: 2007-12-13
Internet Data Sheet
HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
FIGURE 1
Pin Configuration TSOPII-66
[
[
[
9''
9''
9''
966
966
966
1&
'4
'4
'4
'4
1&
9''4
9''4
9''4
9664
9664
9664
1&
1&
'4
'4
1&
1&
'4
'4
'4
'4
'4
'4
9664
9664
9664
9''4
9''4
9''4
1&
1&
'4
'4
1&
1&
1&
'4
'4
'4
'4
1&
9''4
9''4
9''4
9664
9664
9664
1&
1&
'4
'4
1&
1&
'4
'4
'4
'4
'4
'4
9664
9664
9664
9''4
9''4
9''4
1&
1&
'4
'4
1&
1&
1&
1&
1&
1&
1&
1&
9''4
9''4
9''4
9664
9664
9664
1&
1&
/'46
8'46
'46
'46
1&
1&
1&
1&$ 1&$ 1&$
9''
9''
9''
95()
95()
95()
1&
1&
1&
966
966
966
1&
1&
/'0
8'0
'0
'0
:(
:(
:(
&.
&.
&.
&$6
&$6
&$6
&.
&.
&.
5$6
5$6
5$6
&.(
&.(
&.(
&6
&6
&6
1&
%$
1&
%$
1&
$
1&
1&
1&
$
$
$
$
$
%$
%$
%$
%$
$
$
$
$$3
$$3
$$3
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
9''
9''
9''
966
966
966
033'
Rev. 1.41, 2007-12
03292006-3TFJ-HNV3
11
Date: 2007-12-13
Internet Data Sheet
HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
2.2
Configuration for TFBGA-60
The ball configuration of a DDR SDRAM is listed by function in Table 7. The abbreviations used in the Ball#/Buffer Type column
are explained in Table 8 and Table 9 respectively.
TABLE 7
Configuration
Ball#
Name
Pin
Type
Buffer
Type
Function
G2
CK1
I
SSTL
Clock Signal
G3
CK1
I
SSTL
Complementary Clock Signal
H3
CKE
I
SSTL
Clock Enable
RAS
I
SSTL
Row Address Strobe
G8
CAS
I
SSTL
Column Address Strobe
G7
WE
I
SSTL
Write Enable
H8
CS
I
SSTL
Chip Select
Bank Address Bus
Clock Signals
Control Signals
H7
Address Signals
J8
BA0
I
SSTL
J7
BA1
I
SSTL
K7
A0
I
SSTL
L8
A1
I
SSTL
L7
A2
I
SSTL
M8
A3
I
SSTL
M2
A4
I
SSTL
L3
A5
I
SSTL
L2
A6
I
SSTL
K3
A7
I
SSTL
K2
A8
I
SSTL
J3
A9
I
SSTL
K8
A10
I
SSTL
AP
I
SSTL
J2
A11
I
SSTL
H2
A12
I
SSTL
Address Bus
Data Signals ×4 Organization
B7
DQ0
I/O
SSTL
D7
DQ1
I/O
SSTL
D3
DQ2
I/O
SSTL
B3
DQ3
I/O
SSTL
Data Signal Bus 3:0
Data Strobe ×4 Organization
E3
DQS
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I/O
SSTL
Data Strobe
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HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
Ball#
Name
Pin
Type
Buffer
Type
Function
I
SSTL
Data Mask
SSTL
Data Signal Bus 7:0
Data Mask ×4 Organization
F3
DM
Data Signals × 8 Organization
A8
DQ0
I/O
B7
DQ1
I/O
SSTL
C7
DQ2
I/O
SSTL
D7
DQ3
I/O
SSTL
D3
DQ4
I/O
SSTL
C3
DQ5
I/O
SSTL
B3
DQ6
I/O
SSTL
A2
DQ7
I/O
SSTL
Data Strobe × 8 Organization
E3
DQS
I/O
SSTL
Data Strobe
SSTL
Data Mask
Data Signal 15:0
Data Mask × 8 Organization
F3
DM
I
Data Signals ×16 Organization
A8
DQ0
I/O
SSTL
B9
DQ1
I/O
SSTL
B7
DQ2
I/O
SSTL
C9
DQ3
I/O
SSTL
C7
DQ4
I/O
SSTL
D9
DQ5
I/O
SSTL
D7
DQ6
I/O
SSTL
E9
DQ7
I/O
SSTL
E1
DQ8
I/O
SSTL
D3
DQ9
I/O
SSTL
D1
DQ10
I/O
SSTL
C3
DQ11
I/O
SSTL
C1
DQ12
I/O
SSTL
B3
DQ13
I/O
SSTL
B1
DQ14
I/O
SSTL
A2
DQ15
I/O
SSTL
Data Strobe ×16 Organization
E3
UDQS
I/O
SSTL
Data Strobe Upper Byte
E7
LDQS
I/O
SSTL
Data Strobe Lower Byte
Data Mask ×16 Organization
F3
UDM
I
SSTL
Data Mask Upper Byte
F7
LDM
I
SSTL
Data Mask Lower Byte
VREF
AI
—
I/O Reference Voltage
Power Supplies
F1
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HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
Ball#
Name
Pin
Type
Buffer
Type
Function
A9, B2, C8, D2, VDDQ
E8
PWR
—
I/O Driver Power Supply
A7, F8, M7
VDD
PWR
—
Power Supply
A1, B8, C2, D8, VSSQ
E2
PWR
—
Power Supply
A3, F2, M3
PWR
—
Power Supply
—
Not Connected
—
Not Connected
—
Not Connected
VSS
Not Connected ×4 Organization
A2, A8, B1, B9, NC
C1, C3, C7, C9,
D1, D9, E1, E7,
E9, F7, F9
NC
Not Connected ×8 Organization
B1, B9, C1, C9, NC
D1, D9, E1, E7,
E9, F7, F9
NC
Not Connected ×16 Organization
F9
NC
NC
TABLE 8
Abbreviations for Ball Type
Abbreviation
Description
I
Standard input-only pin. Digital levels
O
Output. Digital levels
I/O
I/O is a bidirectional input/output signal
AI
Input. Analog levels
PWR
Power
GND
Ground
NC
Not Connected
TABLE 9
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminalted Logic (SSTL2)
LV-CMOS
Low Voltage CMOS
CMOS
CMOS Levels
OD
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR
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Internet Data Sheet
HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
FIGURE 2
Configuration for x4 Organization, TFBGA-60, Top View
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033'
Internet Data Sheet
HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
FIGURE 3
Configuration for x8 Organization, TFBGA-60, Top View
9664
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966
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9''4
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$
9''
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9''4
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Rev. 1.41, 2007-12
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Internet Data Sheet
HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
FIGURE 4
Configuration for x16 Organization, TFBGA-60, Top View
$
9''
'4
9''4
'4
%
'4
9664
'4
9664
'4
&
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Rev. 1.41, 2007-12
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033'
Internet Data Sheet
HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
3
Functional Description
The 512-Mbit Double-Data-Rate SDRAM uses a double-data-rate architecture to achieve high-speed operation.
3.1
Mode Register Definition
The Mode Register is used to define the specific mode of operation of the DDR SDRAM.
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$
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WLQ
J0
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Z
Z
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Z
UHJD
GGU
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TABLE 10
Mode Register Definition
Field
Bits
Type1)
Description
BL
[2:0]
W
Burst Length
Note: All other bit combinations are RESERVED.
001B 2
010B 4
011B 8
BT
3
Burst Type
0 Sequential
1 Interleaved
CL
[6:4]
CAS Latency
Note: All other bit combinations are RESERVED.
010B 2
110B 2.5
011B 3
MODE [12:7]
Operating Mode
Note: All other bit combinations are RESERVED.
000000 Normal Operation without DLL Reset
000010 Normal Operation with DLL Reset
1) W = write only register bit
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HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
3.1.1
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type
and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the
starting column address, as shown in Table 11.
TABLE 11
Burst Definition
Burst Length
Starting Column Address
A2
A1
2
A0
Type = Sequential
Type = Interleaved
0
0-1
0-1
1
1-0
1-0
0
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
4
8
Order of Accesses Within a Burst
Notes
1.
2.
3.
4.
For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block.
For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the block.
For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access within the block.
Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
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HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
3.2
Extended Mode Register
The Extended Mode Register controls functions beyond those controlled by the Mode Register.
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TABLE 12
Extended Mode Register
1)
Field
Bits
Type
Description
DLL
0
w
DLL Status
Enabled
0B
1B
Disabled
DS
1
Drive Strength
0B
Normal
1B
Weak
MODE
[12:2]
Operating Mode
00000000000B Normal Operation
Notes
1. A2 must be 0 to provide compatibility with early DDR devices.
2. All other bit combinations are RESERVED.
1) w = write only register bit
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512-Mbit Double-Data-Rate SDRAM
4
Truth Tables
The truth tables in this chapter summarize the commands and there signal coding to control a standard Double-Data-Rate
SDRAM.
TABLE 13
Truth Table 1: Commands
Name (Function)
CS
RAS
CAS
WE
Address
MNE
Note
Deselect (NOP)
H
X
X
X
X
NOP
1)2)
No Operation (NOP)
L
H
H
H
X
NOP
1)2)
Active (Select Bank And Activate Row)
L
L
H
H
Bank/Row
ACT
1)3)
Read (Select Bank And Column, And Start Read Burst)
L
H
L
H
Bank/Col
Read
1)4)
Write (Select Bank And Column, And Start Write Burst)
L
H
L
L
Bank/Col
Write
1)4)
Burst Terminate
L
H
H
L
X
BST
1)5)
Precharge (Deactivate Row In Bank Or Banks)
L
L
H
L
Code
PRE
1)6)
Auto Refresh Or Self Refresh (Enter Self Refresh Mode)
L
L
L
H
X
AR/SR
1)7)8)
Mode Register Set
L
L
L
L
Op-Code
MRS
1)9)
1)
2)
3)
4)
5)
6)
7)
8)
9)
CKE is HIGH for all commands shown exceptSelf Refresh.VREF must be maintained during Self Refresh operation.
Deselect and NOP are functionally interchangeable.
BA0, BA1 provide bank address and A0 - Ai provide row address.
BA0, BA1 provide bank address; A0 - Ai provide column address ; A10 HIGH enables the Auto Precharge feature (nonpersistent), A10
LOW disables the Auto Precharge feature.
Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto
Precharge enabled or for write bursts.
A10 LOW: BA0, BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care”.
This command is AUTO REFRESH if CKE is HIGH; Self Refresh if CKE is LOW
Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects
Extended Mode Register; other combinations of BA0-BA1 are reserved; A0 - Ai provide the op-code to be written to the selected Mode
Register.
TABLE 14
Truth Table 2: DM Operation
Name (Function)
DM
DQs
Note
1)
Write Enable
L
Valid
Write Inhibit
H
X
1) Used to mask write data; provided coincident with the corresponding data.
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512-Mbit Double-Data-Rate SDRAM
TABLE 15
Truth Table 3: Clock Enable (CKE)
Current State
CKE n-1
CKEn
Command n
Action n
Notes
Previous
Cycle
Current
Cycle
Self Refresh
L
L
X
Maintain Self-Refresh
1)
Self Refresh
L
H
Deselect or NOP
Exit Self-Refresh
2)
Power Down
L
L
X
Maintain Power-Down
–
Power Down
L
H
Deselect or NOP
Exit Power-Down
–
All Banks Idle
H
L
Deselect or NOP
Precharge Power-Down Entry
–
All Banks Idle
H
L
AUTO REFRESH
Self Refresh Entry
–
Bank(s) Active
H
L
Deselect or NOP
Active Power-Down Entry
–
H
H
See Table 16
–
–
1) VREF must be maintained during Self Refresh operation
2) Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (tXSNR) period. A minimum of 200
clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
1.
2.
3.
4.
CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
Current state is the state of the DDR SDRAM immediately prior to clock edge n.
COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n.
All states and sequences not shown are illegal or reserved.
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512-Mbit Double-Data-Rate SDRAM
TABLE 16
Truth Table 4: Current State Bank n - Command to Bank n (same bank)
Current State CS
RAS CAS WE Command
Action
Notes
H
X
X
X
Deselect
NOP. Continue previous operation.
1)2)3)4)5)6)
L
H
H
H
No Operation
NOP. Continue previous operation.
1)2)3)4)5)6)
L
L
H
H
Active
Select and activate row
1)2)3)4)5)6)
L
L
L
H
AUTO REFRESH
–
1)2)3)4)5)6)7)
L
L
L
L
MODE REGISTER SET –
1)2)3)4)5)6)7)
L
H
L
H
Read
Select column and start Read burst
1)2)3)4)5)6)8)
L
H
L
L
Write
Select column and start Write burst
1)2)3)4)5)6)8)
L
L
H
L
Precharge
Deactivate row in bank(s)
1)2)3)4)5)6)9)
Read (Auto
Precharge
Disabled)
L
H
L
H
Read
Select column and start new Read burst
1)2)3)4)5)6)8)
L
L
H
L
Precharge
Truncate Read burst, start Precharge
1)2)3)4)5)6)9)
L
H
H
L
BURST TERMINATE
BURST TERMINATE
1)2)3)4)5)6)10)
Write (Auto
Precharge
Disabled)
L
H
L
H
Read
Select column and start Read burst
1)2)3)4)5)6)8)11)
L
H
L
L
Write
Select column and start Write burst
1)2)3)4)5)6)8)
L
L
H
L
Precharge
Truncate Write burst, start Precharge
1)2)3)4)5)6)9)11)
Any
Idle
Row Active
1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 15 and after tXSNR/tXSRD has been met (if the previous state
was self refresh).
2) This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed
to be issued to that bank when in that state. Exceptions are covered in the notes below.
3) Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated,
and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with
Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge
disabled, and has not yet terminated or been terminated.
4) The following states must not be interrupted by a command issued to the same bank. Precharging: Starts with registration of a Precharge
command and ends when tRP is met. Once tRP is met, the bank is in the idle state. Row Activating: Starts with registration of an Active
command and ends when tRCD is met. Once tRCD is met, the bank is in the “row active” state. Read w/Auto Precharge Enabled: Starts with
registration of a Read command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle
state. Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when tRP has
been met. Once tRP is met, the bank is in the idle state. Deselect or NOP commands, or allowable commands to the other bank should be
issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and
according to Table 17.
5) The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive
clock edge during these states. Refreshing: Starts with registration of an Auto Refresh command and ends when tRFC is met. Once tRFC is
met, the DDR SDRAM is in the “all banks idle” state. Accessing Mode Register: Starts with registration of a Mode Register Set command
and ends when tMRD has been met. Once tMRD is met, the DDR SDRAM is in the “all banks idle” state. Precharging All: Starts with
registration of a Precharge All command and ends when tRP is met. Once tRP is met, all banks is in the idle state.
6) All states and sequences not shown are illegal or reserved.
7) Not bank-specific; requires that all banks are idle.
8) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
Auto Precharge disabled.
9) May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging.
10) Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank.
11) Requires appropriate DM masking.
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Internet Data Sheet
HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
TABLE 17
Truth Table 5: Current State Bank n - Command to Bank m (different bank)
Current State
CS
RAS
CAS
WE
Command
Action
Notes
H
X
X
X
Deselect
NOP. Continue previous operation.
1)2)3)4)5)6)
L
H
H
H
No Operation
NOP. Continue previous operation.
1)2)3)4)5)6)
Idle
X
X
X
X
Any Command
Otherwise Allowed to
Bank m
–
1)2)3)4)5)6)
Row
Activating,
Active, or
Precharging
L
L
H
H
Active
Select and activate row
1)2)3)4)5)6)
L
H
L
H
Read
Select column and start Read burst
1)2)3)4)5)6)7)
L
H
L
L
Write
Select column and start Write burst
1)2)3)4)5)6)7)
L
L
H
L
Precharge
–
1)2)3)4)5)6)
Read (Auto
Precharge
Disabled)
L
L
H
H
Active
Select and activate row
1)2)3)4)5)6)
L
H
L
H
Read
Select column and start new Read burst
1)2)3)4)5)6)7)
L
L
H
L
Precharge
–
1)2)3)4)5)6)
Write (Auto
Precharge
Disabled)
L
L
H
H
Active
Select and activate row
1)2)3)4)5)6)
L
H
L
H
Read
Select column and start Read burst
1)2)3)4)5)6)7)8)
L
H
L
L
Write
Select column and start new Write burst
1)2)3)4)5)6)7)
L
L
H
L
Precharge
–
1)2)3)4)5)6)
L
L
H
H
Active
Select and activate row
1)2)3)4)5)6)
L
H
L
H
Read
Select column and start new Read burst
1)2)3)4)5)6)7)9)
L
H
L
L
Write
Select column and start Write burst
1)2)3)4)5)6)7)9)10)
L
L
H
L
Precharge
–
1)2)3)4)5)6)
L
L
H
H
Active
Select and activate row
1)2)3)4)5)6)
L
H
L
H
Read
Select column and start Read burst
1)2)3)4)5)6)7)9)
L
H
L
L
Write
Select column and start new Write burst
1)2)3)4)5)6)7)9)
L
L
H
L
Precharge
–
1)2)3)4)5)6)
Any
Read (With
Auto
Precharge)
Write (With
Auto
Precharge)
1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 15: Clock Enable (CKE) and after tXSNR/tXSRD has been met,
if the previous state was self refresh)
2) This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those
allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in
the notes below.
3) Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated,
and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with
Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge
disabled, and has not yet terminated or been terminated.
4) AUTO REFRESH and Mode Register Set commands may only be issued when all banks are idle.
5) A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.
6) All states and sequences not shown are illegal or reserved.
7) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
Auto Precharge disabled.
8) Requires appropriate DM masking.
9) Concurrent Auto Precharge:This device supports “Concurrent Auto Precharge”. When a read with auto precharge or a write with auto
precharge is enabled any command may follow to the other banks as long as that command does not interrupt the read or write data
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512-Mbit Double-Data-Rate SDRAM
transfer and all other limitations apply (e.g. contention between READ data and WRITE data must be avoided). The minimum delay from
a read or write command with auto precharge enable, to a command to a different banks is summarized in Table 18.
10) A Write command may be applied after the completion of data output.
TABLE 18
Truth Table 6: Concurrent Auto Precharge
From Command
To Command (different bank)
Minimum Delay with Concurrent Auto Unit
Precharge Support
WRITE w/AP
Read or Read w/AP
1 + (BL/2) + tWTR
Write to Write w/AP
BL/2
Precharge or Activate
1
Read or Read w/AP
BL/2
Write or Write w/AP
CL (rounded up) + BL/2
Precharge or Activate
1
Read w/AP
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tCK
tCK
tCK
tCK
tCK
tCK
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512-Mbit Double-Data-Rate SDRAM
5
Electrical Characteristics
This chapter describes the electrical characteristics.
5.1
Operating Conditions
This chapter contains the operating conditions tables.
TABLE 19
Absolute Maximum Ratings
Parameter
Voltage on I/O pins relative to VSS
Voltage on inputs relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating temperature (ambient)
Storage temperature (plastic)
Power dissipation (per SDRAM component)
Short circuit output current
Symbol
Values
Unit
Note
Min.
Typ.
Max.
VIN, VOUT
VIN
VDD
VDDQ
TA
–0.5
—
VDDQ + 0.5
V
—
–1
—
+3.6
V
—
–1
—
+3.6
V
—
–1
—
+3.6
V
—
0
—
+70
°C
for HYB...
–40
—
+85
°C
for HYI...
TSTG
PD
IOUT
–55
—
+150
°C
—
—
1
—
W
—
—
50
—
mA
—
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings
are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated
circuit.
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TABLE 20
Input and Output Capacitances
Parameter
Input Capacitance: CK, CK
Symbol
CI1
Values
Unit
Note/ Test Condition
TSOPII1)
Min.
Typ.
Max.
2.0
—
3.0
pF
1.5
—
2.5
pF
TFBGA 1)
Delta Input Capacitance
CdI1
—
—
0.25
pF
1)
Input Capacitance: All other input-only pins
CI2
1.5
—
2.5
pF
TFBGA 1)
2.0
—
3.0
pF
TSOPII 1)
Delta Input Capacitance: All other input-only pins
CdIO
—
—
0.5
pF
1)
Input/Output Capacitance: DQ, DQS, DM
CIO
3.5
—
4.5
pF
TFBGA 1)2)
4.0
—
5.0
pF
TSOPII 1)2)
pF
1)
Delta Input/Output Capacitance: DQ, DQS, DM
CdIO
—
—
0.5
1) These values are guaranteed by design and are tested on a sample base only. VDDQ = VDD = 2.5 V ± 0.2 V, f = 100 MHz, TA = 25 °C,
VOUT(DC) = VDDQ/2, VOUT (Peak to Peak) 0.2 V. Unused pins are tied to ground.
2) DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the
board level.
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TABLE 21
Electrical Characteristics and DC Operating Conditions
Parameter
Symbol
Unit Note/Test Condition 1)
Values
Min.
Typ.
Max.
VDD
VDDQ
VSS, VSSQ
2.3
2.5
2.7
2.3
2.5
VREF
VTT
0.49 × VDDQ
2.7
V
fCK ≤ 200 MHz
fCK ≤ 200 MHz 2)
0
V
—
0.51 × VDDQ
V
3)
VREF – 0.04
VREF + 0.04
V
4)
VIH.DC
VIL.DC
VIN.DC
VREF + 0.15
V
5)
V
5)
–0.3
VDDQ + 0.3
VREF – 0.15
VDDQ + 0.3
V
5)
Input Differential Voltage,
CK and CK Inputs
VID.DC
0.36
VDDQ + 0.6
V
5)6)
VI-Matching Pull-up Current
to Pull-down Current
VIRatio
0.71
1.4
—
7)
Input Leakage Current
II
–2
2
μA
Any input 0 V ≤ VIN ≤ VDD;
All other pins not under test
= 0 V 8)
Output Leakage Current
IOZ
–5
5
μA
DQs are disabled;
0 V ≤ VOUT ≤ VDDQ 8)
Output High Current,
Normal Strength Driver
IOH
—
TBD
mA
VOUT = 1.95 V
Output Low Current,
Normal Strength Driver
IOL
TBD
—
mA
VOUT = 0.35 V
Device Supply Voltage
Output Supply Voltage
Supply Voltage,
I/O Supply Voltage
Input Reference Voltage
I/O Termination Voltage
(System)
Input High (Logic1) Voltage
Input Low (Logic0) Voltage
Input Voltage Level,
CK and CK Inputs
0
0.5 × VDDQ
–0.3
V
1) 0 °C ≤ TA ≤ 70 °C; VDD = VDDQ = 2.5 V ± 0.2 V
2) Under all conditions, VDDQ must be less than or equal to VDD.
3) Peak to peak AC noise on VREF may not exceed ± 2% VREF.DC. VREF is also expected to track noise variations in VDDQ.
4) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in the DC level of VREF.
5) Inputs are not recognized as valid until VREF stabilizes.
6) VID is the magnitude of the difference between the input level on CK and the input level on CK.
7) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and
voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between
pull-up and pull-down drivers due to process variation.
8) Values are shown per pin.
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5.2
AC Characteristics
Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions,
IDD Specifications and Conditions, and Electrical Characteristics and AC Timing.
Notes
1. All voltages referenced to VSS.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage
levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. Figure 5 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended
to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a
production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system
environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line
terminated at the tester electronics).
4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still referenced
to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels
under normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between VIL(AC) and VIH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as
a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above
(below) the DC input LOW (HIGH) level).
6. For System Characteristics like Setup & Holdtime Derating for Slew Rate, I/O Delta Rise/Fall Derating, DDR SDRAM Slew
Rate Standards, Overshoot & Undershoot specification and Clamp V-I characteristics see the latest Industry specification
for DDR components.
FIGURE 5
AC Output Load Circuit Diagram / Timing Reference Load
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TABLE 22
AC Operating Conditions
Parameter
Symbol
Input High (Logic 1) Voltage, DQ, DQS and DM Signals
Input Low (Logic 0) Voltage, DQ, DQS and DM Signals
Input Differential Voltage, CK and CK Inputs
Input Closing Point Voltage, CK and CK Inputs
1)
2)
3)
4)
5)
VIH.AC
VIL.AC
VID.AC
VIX.AC
Values
Min.
Max.
VREF + 0.31
—
Unit Note/ Test
Condition
VREF – 0.31
0.7
VDDQ + 0.6
0.5 × VDDQ– 0.2 0.5 × VDDQ+ 0.2
—
V
1)2)3)
V
1)2)3)
V
1)2)3)4)
V
1)2)3)5)
0 °C ≤ TA ≤ 70 °C; VDD = VDDQ = 2.5 V ± 0.2 V
Input slew rate = 1 V/ns.
Inputs are not recognized as valid until VREF stabilizes.
VID is the magnitude of the difference between the input level on CK and the input level on CK.
The value of VIX is expected to equal 0.5 × VDDQ of the transmitting device and must track variations in the DC level of the same.
TABLE 23
AC Timing - Absolute Specifications
Parameter
Symbol
–5
–6
DDR400
DDR333
Min.
Max.
Min.
Max.
Unit
Note/ Test
Condition 1)
DQ output access time from
CK/CK
tAC
–0.7
+0.7
–0.7
+0.7
ns
2)3)4)5)
CK high-level width
tCH
tCK
0.45
0.55
0.45
0.55
tCK
2)3)4)5)
5
8
6
12
ns
CL = 3.0 2)3)4)5)
6
12
6
12
ns
CL = 2.5 2)3)4)5)
7
12
7.5
12
ns
CL = 2.0 2)3)4)5)
0.45
0.55
0.45
0.55
tCK
tCK
2)3)4)5)
Clock cycle time
tCL
Auto precharge write recovery + tDAL
CK low-level width
precharge time
Min. : (tWR/tCK)+(tRP/tCK), Max. : —
2)3)4)5)6)
tDH
tDIPW
0.4
—
0.45
—
ns
2)3)4)5)
1.75
—
1.75
—
ns
2)3)4)5)6)
tDQSCK
–0.6
+0.6
–0.6
+0.6
ns
2)3)4)5)
DQS input low (high) pulse width tDQSL,H
(write cycle)
0.35
—
0.35
—
tCK
2)3)4)5)
DQ and DM input hold time
DQ and DM input pulse width
(each input)
DQS output access time from
CK/CK
DQS-DQ skew (DQS and
associated DQ signals)
tDQSQ
—
+0.40
—
+0.45
ns
TSOPII 2)3)4)5)
DQS-DQ skew (DQS and
associated DQ signals)
tDQSQ
—
+0.40
—
+0.40
ns
TFBGA 2)3)4)5)
Write command to 1st DQS
latching transition
tDQSS
0.72
1.25
0.75
1.25
tCK
2)3)4)5)
DQ and DM input setup time
tDS
0.4
—
0.45
—
ns
2)3)4)5)
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Parameter
Symbol
–5
–6
DDR400
DDR333
Unit
Note/ Test
Condition 1)
Min.
Max.
Min.
Max.
DQS falling edge hold time from tDSH
CK (write cycle)
0.2
—
0.2
—
tCK
2)3)4)5)
DQS falling edge to CK setup
time (write cycle)
tDSS
0.2
—
0.2
—
tCK
2)3)4)5)
Clock Half Period
tHP
Min. (tCL,
tCH)
—
Min. (tCL,
tCH)
—
ns
2)3)4)5)
Data-out high-impedance time
from CK/CK
tHZ
—
+0.7
—
+0.7
ns
2)3)4)5)7)
Address and control input hold
time
tIH
0.6
—
0.75
—
ns
fast slew rate
3)4)5)6)8)
0.7
—
0.8
—
ns
slow slew rate
3)4)5)6)8)
Control and Addr. input pulse
width (each input)
tIPW
Address and control input setup tIS
time
2.2
—
2.2
—
ns
2)3)4)5)9)
0.6
—
0.75
—
ns
fast slew rate
3)4)5)6)8)
0.7
—
0.8
—
ns
slow slew
rate3)4)5)6)8)
Data-out low-impedance time
from CK/CK
tLZ
–0.7
+0.7
–0.7
+0.7
ns
2)3)4)5)7)
Mode register set command
cycle time
tMRD
2
—
2
—
tCK
2)3)4)5)
DQ/DQS output hold time from
DQS
tQH
tHP –tQHS
—
tHP –tQHS
—
ns
2)3)4)5)
Data hold skew factor
tQHS
tQHS
tRAP
tRAS
tRC
—
+0.50
—
+0.55
ns
TSOPII 2)3)4)5)
—
+0.50
—
+0.50
ns
TFBGA 2)3)4)5)
tRCD
—
tRCD
—
ns
2)3)4)5)
40
70E+3
42
70E+3
ns
2)3)4)5)
55
—
60
—
ns
2)3)4)5)
tRCD
tREFI
15
—
18
—
ns
2)3)4)5)
—
7.8
—
7.8
μs
2)3)4)5)8)
Auto-refresh to Active/Autorefresh command period
tRFC
65
—
72
—
ns
2)3)4)5)
Precharge command period
tRP
tRPRE
tRPST
tRRD
15
—
18
—
ns
2)3)4)5)
0.9
1.1
0.9
1.1
2)3)4)5)
0.40
0.60
0.40
0.60
tCK
tCK
10
—
12
—
ns
2)3)4)5)
tWPRE
Max. (0.25 × —
tCK, 1.5 ns)
0.25 × tCK
—
ns
2)3)4)5)
Data hold skew factor
Active to Autoprecharge delay
Active to Precharge command
Active to Active/Auto-refresh
command period
Active to Read or Write delay
Average Periodic Refresh
Interval
Read preamble
Read postamble
Active bank A to Active bank B
command
Write preamble
Rev. 1.41, 2007-12
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Parameter
Symbol
–5
–6
DDR400
DDR333
Unit
Note/ Test
Condition 1)
Min.
Max.
Min.
Max.
tWPRES
tWPST
tWR
tWTR
0
—
0
—
ns
2)3)4)5)10)
0.40
0.60
0.40
0.60
tCK
2)3)4)5)11)
15
—
15
—
ns
2)3)4)5)
2
—
1
—
tCK
2)3)4)5)
Exit self-refresh to non-read
command
tXSNR
75
—
75
—
ns
2)3)4)5)
Exit self-refresh to read
command
tXSRD
200
—
200
—
tCK
2)3)4)5)
Write preamble setup time
Write postamble
Write recovery time
Internal write to read command
delay
1) 0 °C ≤ TA ≤ 70 °C; VDD = VDDQ = 2.5 V ± 0.2 V
2) Input slew rate ≥ 1 V/ns.
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time.
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between VIH.AC and VIL.AC.
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) The specific requirement is that DQS be valid (HIGH,LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specificationsof the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW at this time, depending
on tDQSS.
11) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
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TABLE 24
IDD Conditions
Parameter
Symbol
Operating Current: one bank; active/ precharge; tRC = tRCMIN; tCK = tCKMIN;
DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two
clock cycles.
IDD0
Operating Current: one bank; active/read/precharge; Burst = 4;
Refer to the following page for detailed test conditions.
IDD1
Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE ≤VILMAX; tCK = tCKMIN
IDD2P
IDD2F
Precharge Floating Standby Current: CS ≥ VIHMIN, all banks idle;
CKE ≥ VIHMIN; tCK = tCKMIN, address and other control inputs changing once per clock cycle, VIN = VREF for DQ, DQS
and DM.
Precharge Quiet Standby Current: CS ≥ VIHMIN, all banks idle; CKE ≥ VIHMIN; tCK = tCKMIN, address and other
control inputs stable at ≥ VIHMIN or ≤ VILMAX; VIN=VREF for DQ, DQS and DM.
IDD2Q
Active Power-Down Standby Current: one bank active; power-down mode;
CKE ≤ VILMAX; tCK= tCKMIN; VIN = VREF for DQ, DQS and DM.
IDD3P
Active Standby Current: one bank active; CS ≥ VIHMIN; CKE ≥ VIHMIN; tRC = tRASMAX; tCK = tCKMIN; DQ, DM and DQS IDD3N
inputs changing twice per clock cycle; address and control inputs changing once per clock cycle
Operating Current: one bank active; Burst = 2; reads; continuous burst; address and control inputs changing
once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A,
CL = 3 for DDR333; tCK = tCKMIN; IOUT = 0 mA
IDD4R
Operating Current: one bank active; Burst = 2; writes; continuous burst; address and control inputs changing
once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A,
CL = 3 for DDR333; tCK = tCKMIN
IDD4W
Auto-Refresh Current: tRC = tRFCMIN, burst refresh
IDD5
IDD6
IDD7
Self-Refresh Current: CKE ≤ 0.2 V; external clock on; tCK = tCKMIN
Operating Current: four bank; four bank interleaving with BL = 4; Refer to the following page for detailed test
conditions.
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TABLE 25
IDD Specification
–6
–5
DDR333
DDR400
Unit
Note
3)
Symbol
Typ.
Max.
Typ.
Max.
IDD0
60
70
60
75
mA
×4/×8 4)1)
70
85
75
90
mA
×16 1)
65
80
70
85
mA
×4/×8 1)
80
95
90
110
mA
×16 1)
1.1
4.6
1.1
4.6
mA
1)
21
25
25
30
mA
1)
15
22
17
23
mA
1)
11
15
12
16
mA
1)
32
37
35
42
mA
×4/×8 1)
33
40
38
45
mA
×16 1)
70
85
80
90
mA
×4/×8 1)
95
115
110
135
mA
×16 1)
75
90
85
95
mA
×4/×8 1)
100
120
115
135
mA
×16 1)
130
175
145
190
mA
1)
1.6
5
1.6
5
mA
2)
–
2.5
–
2.5
mA
Low power part - (L)
175
205
195
230
mA
×4/×8 1)
190
230
210
250
mA
×16 1)
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
1) Input slew rate = 1 V/ns.
2) Enables on-chip refresh and address counters.
3) Test conditions for typical values: VDD = 2.5 V (DDR333), VDD = 2.6 V (DDR400), TA = 25 °C, test conditions for maximum values: VDD =
2.7 V, TA = 10 °C.
4) IDD specifications are tested after the device is properly initialized and measured at 166 MHz for DDR333, and 200 MHz for DDR400.
Rev. 1.41, 2007-12
03292006-3TFJ-HNV3
34
Date: 2007-12-13
Internet Data Sheet
HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
6
Package Outlines
The package used for this product family.
Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
FIGURE 6
-).
'!5
'
%0
,!.%
Package Outline P(G)-TSOPII-66
X
- X
-!
8
X
3%!4
).
'0,!.%
-!
8
)NDEX ARKING
$O ESN OTINCLUDEPLA STICO RME TA LPROTR USIONOF M
AXP ERSIDE
$O ESN OTINCLUDEPLA STICP ROTRUSION OFMA XPERS IDE
$O ESN OTINCLUDEDAM
BARP ROTRUSIO NOFMA X
&0/
?0
?
43
/
0))?
Rev. 1.41, 2007-12
03292006-3TFJ-HNV3
35
Date: 2007-12-13
Internet Data Sheet
HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
FIGURE 7
Package Outline P-TFBGA-60
5
5
7
8
5
7
7
%!$&0%%1.+$%0"!++1'0%%-1.+$%0"!++1
!#*!'%.0)%-2!2).-,!0*
!$3-)2,!0*)-'
)$$+%.&/!#*!'%1%$'%1
3,,6/!$14)2(.32"!++
Rev. 1.41, 2007-12
03292006-3TFJ-HNV3
36
Date: 2007-12-13
Internet Data Sheet
HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
FIGURE 8
Package Outline PG-TFBGA-60
5
5
7
8
5
7
7
%!$&0%%1.+$%0"!++1'0%%-1.+$%0"!++1
!#*!'%.0)%-2!2).-,!0*
!$3-)2,!0*)-'
)%1.02&)$3#)!+
)$$+%.&/!#*!'%1%$'%1
3,,6/!$14)2(.32"!++
.+$%0"!++$)!,%2%00%&%012./.120%&+.4#.-$)2)./0%0%&+.4$)!,%2%0)1
,,
Rev. 1.41, 2007-12
03292006-3TFJ-HNV3
37
Date: 2007-12-13
Internet Data Sheet
HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
7
Product Nomenclature
For reference the Qimonda SDRAM component nomenclature is enclosed in this chapter.
TABLE 26
Example for Nomenclature Fields
Example for
DDR SDRAM
Field Number
1
2
3
4
5
6
7
8
HYB
25
D
512
80
0
D
E
9
10
–4
TABLE 27
DDR Memory Components
Field
Description
Values
Coding
1
Qimonda Component Prefix
HYB
Memory components
HYI
Memory components, industrial temperature range (-40°C – +85 °C)
2
Interface Voltage [V]
25
2.5 V
3
DRAM Technology
D
Double Data Rate SDRAM
4
Component Density [Mbit]
64
64 Mbit
128
128 Mbit
256
256 Mbit
5
Number of I/Os
6
Product Variations
7
Die Revision
8
Package,
Lead-Free Status
512
512 Mbit
40
×4
80
×8
16
×16
0 .. 9
look up table
A
First
B
Second
C
Third
D
Fourth
C
FBGA, lead containing
E
TSOP, lead- and halogen-free
F
FBGA, lead- and halogen-free
T
TSOP, lead containing
9
Power
–
Standard power product
10
Speed Grade
–4
DDR500B
–4A
DDR500A
Rev. 1.41, 2007-12
03292006-3TFJ-HNV3
–5
DDR400B
–5A
DDR400A
–6
DDR333B
38
Date: 2007-12-13
Internet Data Sheet
HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
List of Illustrations
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Pin Configuration TSOPII-66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration for x4 Organization, TFBGA-60, Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration for x8 Organization, TFBGA-60, Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration for x16 Organization, TFBGA-60, Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Output Load Circuit Diagram / Timing Reference Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outline P(G)-TSOPII-66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outline P-TFBGA-60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outline PG-TFBGA-60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rev. 1.41, 2007-12
03292006-3TFJ-HNV3
39
Date: 2007-12-13
11
15
16
17
29
35
36
37
Internet Data Sheet
HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information for RoHS Compliant Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Ordering Information for non RoHS Compliant Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Abbreviations for Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations for Ball Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Mode Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Burst Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Truth Table 1: Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Truth Table 2: DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Truth Table 3: Clock Enable (CKE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Truth Table 4: Current State Bank n - Command to Bank n (same bank) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Truth Table 5: Current State Bank n - Command to Bank m (different bank). . . . . . . . . . . . . . . . . . . . . . . . . . 24
Truth Table 6: Concurrent Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Input and Output Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Electrical Characteristics and DC Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AC Timing - Absolute Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
IDD Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
IDD Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Example for Nomenclature Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
DDR Memory Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Rev. 1.41, 2007-12
03292006-3TFJ-HNV3
40
Date: 2007-12-13
Internet Data Sheet
HY[B/I]25D512[40/80/16]0C[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
2.1
2.2
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Configuration for TSOPII-66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Configuration for TFBGA-60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
3.1
3.1.1
3.2
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Burst Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5
5.1
5.2
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7
Product Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Rev. 1.41, 2007-12
03292006-3TFJ-HNV3
41
Date: 2007-12-13
18
18
19
20
Internet Data Sheet
Edition 2007-12
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
www.qimonda.com
Date: 2007-12-13
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