557GI-03LFT

DATASHEET ICS557-03 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE Description Features The ICS557-03 is a spread spectrum clock generator that supports PCI-Express Gen 1 and Ethernet requirements. The device is used for PC or embedded systems to substantially reduce electromagnetic interference (EMI). The device provides two differential (HCSL) spread spectrum outputs. The spread type and amount are configured via select pin. Using IDT’s patented Phase-Locked Loop (PLL) techniques, the device takes a 25 MHz crystal input and produces two pairs of differential outputs at 25 MHz, 100 MHz, 125 MHz or 200 MHz clock frequencies for HCSL, and 25 MHz or 100 MHz for LVDS. • Packaged in 16-pin TSSOP • RoHS 5 (green) or RoHS 6 (green and lead free) compliant packaging • • • • • • • • Supports HCSL or LVDS output levels Operating voltage of 3.3 V Input frequency of 25 MHz Jitter 60 ps (cycle-to-cycle) Spread Spectrum capability Industrial and commercial temperature ranges For PCIe Gen2 applications, see the 5V41065 For PCIe Gen3 applications, see the 5V41235 Block Diagram VDD 2 SS1:SS0 S1:S0 2 CLK0 Control Logic 2 X1/ICLK 25 MHz crystal or clock X2 Optional tuning crystal capacitors IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE CLK0 Phase Lock Loop CLK1 Clock Buffer/ Crystal Oscillator CLK1 2 GND 1 Rr(IREF) OE ICS557-03 REV U 112111 ICS557-03 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE PCIE SSCG Pin Assignment Output Select Table 1 (MHz) S1 S0 CLK(1:0), CLK(1:0) 0 0 25M 0 1 100M S0 1 S1 2 15 CLK0 SS0 3 14 CLK0 1 0 125M X1/ICLK 4 13 GNDODA 1 1 200M X2 5 12 VDDODA OE 6 11 CLK1 GNDXD 7 10 SS1 8 9 16 VDDXD Spread Selection Table 2 SS1 SS0 Spread% CLK1 0 0 No Spread IREF 0 1 Down -0.5 1 0 Down -0.75 1 1 No Spread 16-pin (173 mil) TSSOP Pin Descriptions Pin Number Pin Name Pin Type Pin Description 1 S0 Input Select pin 0. See Table1. Internal pull-up resistor. 2 S1 Input Select pin 1. See Table 1. Internal pull-up resistor. 3 SS0 Input Spread Select pin 0. See Table 2. Internal pull-up resistor. 4 X1/ICLK Input Crystal or clock input. Connect to a 25 MHz crystal or single ended clock. 5 X2 6 OE Input Output enable. Tri-states outputs and device is not shut down. Internal pull-up resistor. 7 GNDXD Power Connect to ground. 8 SS1 Input Spread Select pin 1. See Table 2. Internal pull-up resistor. 9 IREF Output Precision resistor attached to this pin is connected to the internal current reference. 10 CLK1 Output HCSL complimentary clock output 1. 11 CLK1 Output HCSL true clock output 1. 12 VDDODA Power Connect to voltage supply +3.3 V for output driver and analog circuits 13 GNDODA Power Connect to ground. 14 CLK0 Output HCSL complimentary clock output 0. 15 CLK0 Output HCSL true clock output 0. 16 VDDXD Output Crystal connection. Leave unconnected for clock input. Power Connect to voltage supply +3.3 V for crystal oscillator and digital circuit. IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE 2 ICS557-03 REV U 112111 ICS557-03 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE PCIE SSCG Applications Information Output Structures External Components A minimum number of external components are required for proper operation. IREF =2.3 mA 6*IREF Decoupling Capacitors Decoupling capacitors of 0.01 μF should be connected between each VDD pin and the ground plane, as close to the VDD pin as possible. Do not share ground vias between components. Route power from power source through the capacitor pad and then into ICS pin. Crystal A 25 MHz fundamental mode parallel resonant crystal should be used. This crystal must have less than 300 ppm of error across temperature in order for the ICS557-03 to meet PCI Express specifications. R R 475Ω See Output Termination Sections - Pages 3 ~ 5 Crystal Capacitors General PCB Layout Recommendations Crystal capacitors are connected from pins X1 to ground and X2 to ground to optimize the accuracy of the output frequency. For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1. Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. CL= Crystal’s load capacitance in pF Crystal Capacitors (pF) = (CL- 8) * 2 2. No vias should be used between decoupling capacitor and VDD pin. For example, for a crystal with a 16 pF load cap, each external crystal cap would be 16 pF. (16-8)*2=16. 3. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. Current Source (Iref) Reference Resistor - RR If board target trace impedance (Z) is 50Ω, then RR = 475Ω (1%), providing IREF of 2.32 mA. The output current (IOH) is equal to 6*IREF. 4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). Other signal traces should be routed away from the ICS557-03.This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. Output Termination The PCI-Express differential clock outputs of the ICS557-03 are open source drivers and require an external series resistor and a resistor to ground. These resistor values and their allowable locations are shown in detail in the PCI-Express Layout Guidelines section. The ICS557-03 can also be configured for LVDS compatible voltage levels. See the LVDS Compatible Layout Guidelines section. IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE 3 ICS557-03 REV U 112111 ICS557-03 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE PCIE SSCG PCI-Express Layout Guidelines Common Recommendations for Differential Routing L1 length, Route as non-coupled 50 ohm trace. L2 length, Route as non-coupled 50 ohm trace. L3 length, Route as non-coupled 50 ohm trace. RS RT Dimension or Value 0.5 max 0.2 max 0.2 max 33 49.9 Unit inch inch inch ohm ohm Differential Routing on a Single PCB L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Dimension or Value 2 min to 16 max 1.8 min to 14.4 max Unit inch inch Differential Routing to a PCI Express Connector L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Dimension or Value 0.25 to 14 max 0.225 min to 12.6 max Unit inch inch PCI-Express Device Routing L1 L2 L4 RS L1’ L4’ L2’ RS ICS557-03 Output Clock RT L3’ RT L3 PCI-Express Load or Connector Typical PCI-Express (HCSL) Waveform 700 mV 0 tOR 500 ps 0.525 V 0.175 V 500 ps tOF 0.525 V 0.175 V IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE 4 ICS557-03 REV U 112111 ICS557-03 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE PCIE SSCG LVDS Compatible Layout Guidelines Vdiff Vp-p 0.45v 0.22v 0.58 0.28 0.80 0.40 0.60 0.3 R1a = R1b = R1 R2a = R2b = R2 Alternative T ermination for LVDS and other Common Differential Signals Vcm R1 R2 R3 R4 Note 1.08 33 150 100 100 0.6 33 78.7 137 100 0.6 33 78.7 none 100 ICS874003i-02 input compatible 1.2 33 174 140 100 Standard LVDS LVDS Device Routing Figure 3 L2 L1 R3 R1a L4 R4 L4' L2' L1' R1b HCSL Output Buffer R2a R2b L3' Down Device REF_CLK Input L3 Typical LVDS Waveform 1325 mV 1000 mV tOR 500 ps 1250 mV 1150 mV 500 ps tOF 1250 mV 1150 mV IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE 5 ICS557-03 REV U 112111 ICS557-03 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE PCIE SSCG Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS557-03. These ratings are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDDXD, VDDODA 7V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature (commercial) 0 to +70° C Ambient Operating Temperature (industrial) -40 to +85° C Storage Temperature -65 to +150° C Junction Temperature 125° C Soldering Temperature 260° C ESD Protection (Input) 2000 V min. (HBM) DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±10%, Ambient Temperature -40 to +85° C Parameter Symbo l Supply Voltage V Input High Voltage1 Input Low Voltage1 2 Input Leakage Current Operating Supply Current Input Capacitance Output Capacitance Conditions Min. Typ. 2.97 3.3 Max. Units 3.63 V VIH S0, S1, OE, ICLK, SS0, SS1 2.0 VDD +0.3 V VIL S0, S1, OE, ICLK, SS0, SS1 VSS-0.3 0.8 V IIL 0 < Vin < VDD -5 5 μA IDD 50Ω, 2 pF 78 mA IDDOE OE =Low 44 mA Input pin capacitance 7 pF Output pin capacitance 6 pF 5 nH CIN COUT Pin Inductance LPIN Output Resistance ROUT CLK outputs Pull-up Resistor RPU S0, S1, OE, SS0, SS1 3.0 kΩ 100 kΩ 1. Single edge is monotonic when transitioning through region. 2. Inputs with pull-ups/-downs are not included. IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE 6 ICS557-03 REV U 112111 ICS557-03 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE PCIE SSCG AC Electrical Characteristics - CLKOUT, HCSL Unless stated otherwise, VDD=3.3 V ±10%, Ambient Temperature -40 to +85° C Parameter Symbol Conditions Min. Input Frequency Typ. Max. 25 Output Frequency MHz 200 MHz Output High Voltage1,2 VOH 660 700 850 mV Voltage1,2 VOL -150 0 27 mV 250 350 550 mV 140 mV 80 ps Output Low HCSL termination Units Crossing Point Voltage1,2 Absolute Crossing Point Voltage1,2,4 Variation over all edges Jitter, Cycle-to-Cycle1,3 Modulation Frequency Rise Fall Time1,2 tOR Time1,2 tOF Skew between outputs Duty Spread spectrum 30 31.5 33 kHz From 0.175 V to 0.525 V 175 332 700 ps From 0.525 V to 0.175 V 175 344 700 ps 50 ps 55 % 12 us At crossing point Voltage Cycle1,3 45 Output Enable Time5 Output Disable Time5 All outputs 12 us Power-up Time tSTABLE All outputs From power-up VDD=3.3 V 3.0 3.5 ms Spread Change Time tSPREAD Settling period after spread change 3.0 3.5 ms 1 Test setup is RL=50 ohms with 2 pF, Rr = 475Ω (1%). taken from a single-ended waveform. 3 Measurement taken from a differential waveform. 4 Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal. 5 CLKOUT pins are tri-stated when OE is asserted low. CLKOUT is driven differential when OE is high unless its PD= low. 2 Measurement IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE 7 ICS557-03 REV U 112111 ICS557-03 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE PCIE SSCG AC Electrical Characteristics - CLKOUT, LVDS Unless stated otherwise, VDD=3.3 V ±10%, Ambient Temperature -40 to +85° C Parameter Symbol Conditions Min. Input Frequency Typ. Max. Units 25 Output Frequency LVDS termination MHz 100 MHz Differential Output Voltage VOD 247 454 mV Offset Voltage VOS 1.125 1.375 V 50 mV 50 mV 80 ps ∆VOD ∆VOS |Change to VOD| |Change to VOS| Jitter, Cycle-to-Cycle1,3 Modulation Frequency Spread spectrum 30 33 kHz Slew Rate, Rise1,3 tSLR Measured from ±150 mV from crossing point voltage 1 4 V/ns Slew Rate, Fall1,3 tSLF Measured from ±150 mV from crossing point voltage 1 4 V/ns 50 ps Skew between outputs Duty 31.5 At crossing point Voltage Cycle1,3 55 % Output Enable Time5 All outputs 45 12 µs Output Disable Time5 All outputs 12 µs Power-up Time tSTABLE From power-up VDD=3.3 V 3 3.5 ms Spread Change Time tSPREAD Settling period after spread change 3 3.5 ms 1 Test setup is RL=50 ohms with 2 pF, Rr = 475Ω (1%). taken from a single-ended waveform. 3 Measurement taken from a differential waveform. 4 Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal. 5 CLKOUT pins are tri-stated when OE is asserted low. CLKOUT is driven differential when OE is high unless its PD= low. 2 Measurement Electrical Characteristics - Differential Phase Jitter Parameter Symbol Conditions Min Typ Max Units Notes Jitter, Phase tjphasePLL PCIe Gen 1 - - 86 ps (p-p) 1, 2 Note 1: Guaranteed by design and characterization, not 100% tested in production. Note 2: See http://www.pcisig.com for complete specs. IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE 8 ICS557-03 REV U 112111 ICS557-03 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE PCIE SSCG Thermal Characteristics Parameter Symbol θJA Thermal Resistance Junction to Ambient Conditions Still air θJA θJA 1 m/s air flow 3 m/s air flow θJC Thermal Resistance Junction to Case Marking Diagram (ICS557G-03LF) 16 Min. Max. Units 78 ° C/W 70 ° C/W 68 ° C/W 37 ° C/W Marking Diagram (ICS557GI-03LF) 16 9 9 557GI03L ###### YYWW 557G03LF ###### YYWW 1 Typ. 1 8 8 Notes: 1. ###### is the lot code. 2. YYWW is the last two digits of the year, and the week number that the part was assembled. 3. “LF” designates Pb (lead) free package. 4. “I” designates industrial temperature range. 5. Bottom marking: (origin). Origin = country of origin of not USA. IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE 9 ICS557-03 REV U 112111 ICS557-03 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE PCIE SSCG Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters Inches* 16 Symbol E1 A A1 A2 b C D E E1 e L a aaa E INDEX AREA 1 2 D A A2 Min Max -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.1 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0° 8° -0.10 A1 Min Max -0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0° 8° -0.004 c -Ce b SEATING PLANE L aaa C Ordering Information Part / Order Number Marking 557G-03LF See Page 8 557G-03LFT 557GI-03LF See Page 8 557GI-03LFT Shipping Packaging Package Temperature Tubes 16-pin TSSOP 0 to +70° C Tape and Reel 16-pin TSSOP 0 to +70° C Tubes 16-pin TSSOP -40 to +85° C Tape and Reel 16-pin TSSOP -40 to +85° C “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE 10 ICS557-03 REV U 112111 ICS557-03 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE PCIE SSCG Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. 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