5V41066PGGI8

DATASHEET IDT5V41066 4 OUTPUT PCIE GEN1/2 SYNTHESIZER Recommended Applications Features/Benefits 4 Output synthesizer for PCIe Gen1/2 • 20-pin TSSOP package; small board footprint • Spread-spectrum capable; reduces EMI • Outputs can be terminated to LVDS; can drive a wider General Description variety of devices The IDT5V41066 is a PCIe Gen2 compliant spread-spectrum-capable clock generator. The device has 4 differential HCSL outputs and can be used in communication or embedded systems to subtantially reduce electro-magnetic interference (EMI). The spread amount and output frequency are selectable via select pins. • Power down pin; greater system power management • OE control pin; greater system power management • Spread% and frequency pin selection; no software required to configure device • Industrial temperature range available; supports demanding embedded applications Output Features • For PCIe Gen3 applications, see the 5V41236 • 4 - 0.7V current mode differential HCSL output pairs Key Specifications • Cycle-to-cycle jitter < 100 ps • Output-to-output skew < 50 ps • PCIe Gen2 phase jitter < 3.0ps RMS Block Diagram VDD PD OE 2 3 SEL[2:0] Spread Spectrum/ Output clock selection Spread Spectrum Circuitry CLKOUTA X1 25 MHz crystal or clock Clock Oscillator X2 CLKOUTA CLKOUTB PLL Clock Synthesis CLKOUTB CLKOUTC CLKOUTC CLKOUTD CLKOUTD Optional tuning crystal capacitors 2 Rr(IREF) GND IDT® 4 OUTPUT PCIE GEN1/2 SYNTHESIZER 1 IDT5V41066 REV D 112211 IDT5V41066 4 OUTPUT PCIE GEN1/2 SYNTHESIZER Pin Assignment VDDXD 1 20 CLKA S0 2 19 CLKA S1 3 18 CLKB S2 4 17 CLKB X1 5 16 GNDODA X2 6 15 VDDODA PD 7 14 CLKC OE 8 13 CLKC GNDXD 9 12 CLKD 10 11 CLKD IREF 20-pin (173 mil) TSSOP Spread Spectrum Selection Table S2 S1 S0 Spread% Spread Type 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 -0.5 Down -1.0 Down -1.5 Down No Spread Not Applicable -0.5 Down -1.0 Down -1.5 Down No Spread Not Applicable IDT® 4 OUTPUT PCIE GEN1/2 SYNTHESIZER Output Frequency 100 100 100 100 200 200 200 200 2 IDT5V41066 REV D 112211 IDT5V41066 4 OUTPUT PCIE GEN1/2 SYNTHESIZER Pin Descriptions Pin Pin Name Pin Type Pin Description 1 2 3 4 5 6 7 8 VDDXD S0 S1 S2 X1 X2 PD OE Power Input Input Input Input Output Input Input Connect to +3.3 V digital supply. Spread spectrum select pin #0. See table above. Internal pull-up resistor. Spread spectrum select pin #1. See table above Internal pull-up resistor. Spread spectrum select pin #2. See table above. Internal pull-up resistor. Crystal connection. Connect to a fundamental mode crystal or clock input. Crystal connection. Connect to a fundamental mode crystal or leave open. Powers down all PLL’s and tri-states outputs when low. Internal pull-up resistor. Provides output on, tri-states output (High = enable outputs; Low = disable outputs). Internal pull-up resistor. 9 10 11 12 13 14 15 16 GND IREF CLKD CLKD CLKC CLKC VDDODA GND Power Output Output Output Output Output Power Power Connect to digital ground. Precision resistor attached to this pin is connected to the internal current reference. Selectable 100/200 MHz spread spectrum differential Complement output clock D. Selectable 100/200 MHz spread spectrum differential True output clock D. Selectable 100/200 MHz spread spectrum differential Complement output clock C. Selectable 100/200 MHz spread spectrum differential True output clock C. Connect to +3.3 V analog supply. Connect to analog ground. 17 CLKB Output Selectable 100/200 MHz spread spectrum differential Complement output clock B. 18 CLKB Output Selectable 100/200 MHz spread spectrum differential True output clock B. 19 CLKA Output Selectable 100/200 MHz spread spectrum differential Complement output clock A. 20 CLKA Output Selectable 100/200 MHz spread spectrum differential True output clock A. IDT® 4 OUTPUT PCIE GEN1/2 SYNTHESIZER 3 IDT5V41066 REV D 112211 IDT5V41066 4 OUTPUT PCIE GEN1/2 SYNTHESIZER Application Information Decoupling Capacitors Load Resistors RL As with any high-performance mixed-signal IC, the IDT5V41066 must be isolated from system power supply noise to perform optimally. Since the clock outputs are open source outputs, 50 ohm external resistors to ground are to be connected at each clock output. Decoupling capacitors of 0.01µF must be connected between each VDD and the PCB ground plane. Output Termination The PCI-Express differential clock outputs of the IDT5V41066 are open source drivers and require an external series resistor and a resistor to ground. These resistor values and their allowable locations are shown in detail in the PCI-Express Layout Guidelines section. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. The IDT5V41066 can also be configured for LVDS compatible voltage levels. See the LVDS Compatible Layout Guidelines section. 2) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). Other signal traces should be routed away from the IDT5V41066. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. External Components A minimum number of external components are required for proper operation. Decoupling capacitors of 0.01 μF should be connected between VDD and GND pairs (1,9 and 15,16) as close to the device as possible. On chip capacitors- Crystal capacitors should be connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value (in pf) of these crystal caps equal (CL-12)*2 in this equation, CL=crystal load capacitance in pf. For example, for a crystal with a 16 pF load cap, each external crystal cap would be 8 pF. [(16-12)x2]=8. Current Reference Source Rr (Iref) If board target trace impedance (Z) is 50Ω, then Rr = 475Ω (1%), providing IREF of 2.32 mA, output current (IOH) is equal to 6*IREF. IDT® 4 OUTPUT PCIE GEN1/2 SYNTHESIZER 4 IDT5V41066 REV D 112211 IDT5V41066 4 OUTPUT PCIE GEN1/2 SYNTHESIZER Output Structures 6*IREF IREF =2.3 mA R R 475Ω See Output Termination Sections - Pages 3 ~ 5 General PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1. Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. 2. No vias should be used between decoupling capacitor and VDD pin. 3. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). Other signal traces should be routed away from the IDT5V41066.This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. IDT® 4 OUTPUT PCIE GEN1/2 SYNTHESIZER 5 IDT5V41066 REV D 112211 IDT5V41066 4 OUTPUT PCIE GEN1/2 SYNTHESIZER Layout Guidelines SRC Reference Clock Common Recommendations for Differential Routing L1 length, route as non-coupled 50ohm trace L2 length, route as non-coupled 50ohm trace L3 length, route as non-coupled 50ohm trace Rs Rt D imension or Value 0.5 max 0.2 max 0.2 max 33 49.9 Unit inch inch inch ohm ohm Figure 1 1 1 1 1 Down Device Differential Routing L4 length, route as coupled microstrip 100ohm differential trace L4 length, route as coupled stripline 100ohm differential trace 2 min to 16 max 1.8 min to 14.4 max inch inch 1 1 Differential Routing to PCI Express Connector L4 length, route as coupled microstrip 100ohm differential trace L4 length, route as coupled stripline 100ohm differential trace 0.25 to 14 max 0.225 min to 12.6 max inch inch 2 2 Figure 1: Down Device Routing L2 L1 Rs L4 L4' L2' L1' Rs Rt HCSL Output Buffer Rt L3' PCI Express Down Device REF_CLK Input L3 Figure 2: PCI Express Connector Routing L2 L1 Rs L4 L4' L2' L1' Rs Rt HCSL Output Buffer Rt L3' IDT® 4 OUTPUT PCIE GEN1/2 SYNTHESIZER 6 PCI Express Add-in Board REF_CLK Input L3 IDT5V41066 REV D 112211 IDT5V41066 4 OUTPUT PCIE GEN1/2 SYNTHESIZER Alternative Termination for LVDS and other Common Differential Signals (figure 3) Vdiff Vp-p Vcm R1 R2 R3 R4 Note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 Standard LVDS R1a = R1b = R1 R2a = R2b = R2 Figure 3 L2 L1 R3 R1a R4 L4 L4' L2' L1' R1b R2a HCSL Output Buffer R2b L3' Down Device REF_CLK Input L3 Cable Connected AC Coupled Application (figure 4) Component Value Note R5a, R5b 8.2K 5% R6a, R6b 1K 5% Cc 0.1 µF Vcm 0.350 volts Figure 4 3.3 Volts R5a R5b R6a R6b Cc L4 L4' Cc IDT® 4 OUTPUT PCIE GEN1/2 SYNTHESIZER 7 PCIe Device REF_CLK Input IDT5V41066 REV D 112211 IDT5V41066 4 OUTPUT PCIE GEN1/2 SYNTHESIZER Typical PCI-Express (HCSL) Waveform 700 mV 0 tOR 500 ps 500 ps 0.52 V 0.175 V tOF 0.52 V 0.175 V Typical LVDS Waveform 1325 mV 1000 mV tOR 500 ps 500 ps 1250 mV 1150 mV IDT® 4 OUTPUT PCIE GEN1/2 SYNTHESIZER tOF 1250 mV 1150 mV 8 IDT5V41066 REV D 112211 IDT5V41066 4 OUTPUT PCIE GEN1/2 SYNTHESIZER Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the IDT5V41066. These ratings are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD, VDDA 5.5 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature (commercial) 0 to +70° C Ambient Operating Temperature (industrial) -40 to +85° C Storage Temperature -65 to +150° C Junction Temperature 125° C Soldering Temperature 260° C ESD Protection (Input) 2000 V min. (HBM) DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C Parameter Symbol Supply Voltage Input High Voltage1 Input Low Voltage 1 2 Min. Typ. Max. V Conditions 3.135 3.3 3.465 Units VIH 2.2 VDD +0.3 V VIL VSS-0.3 0.8 V Input Leakage Current IIL 0 < Vin < VDD 5 μA Operating Supply Current @100 MHz IDD 115 125 mA IDDOE RS=33Ω, RP=50Ω, CL=2 pF OE =Low 42 48 mA IDDPD No load, PD =Low 350 500 μA Input Capacitance CIN -5 Input pin capacitance 7 pF Output pin capacitance 6 pF CINX 5 pF LPIN 5 nH Output Capacitance COUT X1, X2 Capacitance Pin Inductance Output Impedance Zo Pull-up Resistance RPUP CLK outputs 3.0 OE, SEL, PD pins kΩ 110 kΩ 1. Single edge is monotonic when transitioning through region. 2. Inputs with pull-ups/-downs are not included. IDT® 4 OUTPUT PCIE GEN1/2 SYNTHESIZER 9 IDT5V41066 REV D 112211 IDT5V41066 4 OUTPUT PCIE GEN1/2 SYNTHESIZER AC Electrical Characteristics - CLKOUT (A:D) Unless stated otherwise, VDD=3.3 V ±5%, Ambient Temperature -40 to +85° C Parameter Symbol Conditions Min. Typ. Input Frequency 25 Output Frequency 25 200 MHz 25 100 MHz 850 mV VOH HCSL VOL HCSL -150 Absolute 250 Crossing Point Crossing Point Voltage1,2,4 Jitter, Cycle-to-Cycle1,3 All outputs Modulation Frequency Rise Time1,2 Fall mV Variation over all edges Frequency Synthesis Error Time1,2 Rise/Fall Time MHz LVDS termination Voltage1,2 Voltage1,2 Units HCSL termination Output High Voltage1,2 Output Low Max. 550 mV 140 mV 100 ps 0 32.9 ppm Spread spectrum 30 33 kHz tOR From 0.175 V to 0.525 V 175 700 ps tOF From 0.525 V to 0.175 V 175 700 ps 125 ps Variation1,2 Output to Output Skew Duty Cycle1,3 45 50 ps 55 % Output Enable Time5 All outputs 50 100 ns Output Disable Time5 All outputs 50 100 ns 1.8 ms 30 ms Stabilization Time tSTABLE From power-up VDD=3.3 V Spread Spectrum Transition Time tSPREAD Stabilization time after spread spectrum changes 1 Test 7 setup is RS=33Ω, RP=50Ω with CL=2 pF, Rr = 475Ω (1%). taken from a single-ended waveform. 2 Measurement 3 Measurement taken from a differential waveform. 4 Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal. 5 CLKOUT pins are tri-stated when OE is asserted low. CLKOUT is driven differential when OE is high unless its PD= low. Electrical Characteristics - Differential Phase Jitter Parameter Jitter, Phase Symbol Conditions Min Typ Max Units Notes 30 86 ps (p-p) 1,2,3 tjphasePLL PCIe Gen1 tjphaseLO PCIe Gen2, 10 kHz < f < 1.5 MHz 0.76 3 ps (RMS) 1,2,3 PCIe Gen2, 1.5 MHz < f < Nyquist (50 MHz) 2.0 3.1 ps (RMS) 1,2,3 tjphaseHIGH Note 1. Guaranteed by design and characterization, not 100% tested in production. Note 2. See http://www.pcisig.com for complete specs. Note 3: Applies to 100MHz, spread off and 0.5% down spread only. IDT® 4 OUTPUT PCIE GEN1/2 SYNTHESIZER 10 IDT5V41066 REV D 112211 IDT5V41066 4 OUTPUT PCIE GEN1/2 SYNTHESIZER Thermal Characteristics Parameter Symbol Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Conditions Max. Units Still air 93 ° C/W θ JA 1 m/s air flow 78 ° C/W θ JA 3 m/s air flow 65 ° C/W 20 ° C/W θ JC Marking Diagram (5V41066PGGI) 20 11 11 IDT5V410 66PGGI #YYWW$ IDT5V410 66PGG #YYWW$ 1 Typ. θ JA Marking Diagram (5V41066PGG) 20 Min. 1 10 10 Notes: 1. Line 1 and 2: IDT part number. 2. Line 3: # – Die revision; YYWW – Date code; $ – Assembly location. 3. “G” after the two-letter package code designates RoHS compliant package. 4. “I” at the end of part number indicates industrial temperature range. 5. Bottom marking: country of origin if not USA. IDT® 4 OUTPUT PCIE GEN1/2 SYNTHESIZER 11 IDT5V41066 REV D 112211 IDT5V41066 4 OUTPUT PCIE GEN1/2 SYNTHESIZER Package Outline and Package Dimensions (20-pin TSSOP, 173 mil Body) Package dimensions are kept current with JEDEC Publication No. 95, MO-153 Millimeters Inches* 20 Symbol E1 A A1 A2 b c D E E1 e L a aaa E INDEX AREA 1 2 D Min Max 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 6.40 6.60 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0° 8° -0.10 Min Max 0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.252 0.260 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0° 8° -0.004 A A2 A1 c -Ce b SEATING PLANE L aaa C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature 5V41066PGG see page 10 Tubes 20-pin TSSOP 0 to +70° C 5V41066PGG8 Tape and Reel 20-pin TSSOP 0 to +70° C 5V41066PGGI Tubes 20-pin TSSOP -40 to +85° C 5V41066PGGI8 Tape and Reel 20-pin TSSOP -40 to +85° C “G” after the two-letter package code are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT® 4 OUTPUT PCIE GEN1/2 SYNTHESIZER 12 IDT5V41066 REV D 112211 IDT5V41066 4 OUTPUT PCIE GEN1/2 SYNTHESIZER Revision History Rev. Originator Date Description of Change A RDW 01/20/10 New datasheet; Preliminary initial release. B RDW 04/27/10 Updated electrical tables per char; released to final. C RDW 07/19/10 1. Updated title and general decription 2. Updated cycle-to-cycle jitter spec from 125 to 100 ps. D RDW 11/21/11 1. Changed title to “4 Output PCIe GEN1/2 Synthesizer” 2. Added note to Features section: “For PCIe Gen3 applications, see 5V41236” 3. Updated Differential Phase Jitter table. IDT® 4 OUTPUT PCIE GEN1/2 SYNTHESIZER 13 IDT5V41066 REV D 112211 IDT5V41066 4 OUTPUT PCIE GEN1/2 SYNTHESIZER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. 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