DATASHEET
5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
Description
Features
The 5V49EE502 is a programmable clock generator
intended for high performance data-communications,
telecommunications, consumer, and networking
applications. There are four internal PLLs, each individually
programmable, allowing for four unique non-integer-related
frequencies. The frequencies are generated from a single
reference clock. The reference clock can come from one of
the two redundant clock inputs. Automatic or manual
switchover function allows any one of the redundant clocks
to be selected during normal operation.
•
•
•
•
•
•
The 5V49EE502 is in-system, programmable and can be
programmed through the use of I2C interface. An internal
EEPROM allows the user to save and restore the
configuration of the device without having to reprogram it on
power-up.
• Two independently controlled VDDO (1.8V to 3.3V)
• Each PLL has a 7-bit reference divider and a 12-bit
Internal non-volatile EEPROM
Fast (400kHz) mode I2C serial interface
Input frequency range: 1MHz to 200MHz
Output frequency range: 4.9kHz to 500MHz
Reference crystal input with programmable linear load
capacitance
— Crystal frequency range: 8MHz to 50MHz
feedback-divider
• 8-bit output-divider blocks
• Fractional division capability on one PLL
• Two of the PLLs support spread spectrum generation
Each of the four PLLs has an 7-bit reference divider and a
12-bit feedback divider. This allows the user to generate
four unique non-integer-related frequencies. The PLL loop
bandwidth is programmable to allow the user to tailor the
PLL response to the application. For instance, the user can
tune the PLL parameters to minimize jitter generation or to
maximize jitter attenuation. Spread spectrum generation
and/or fractional divides are allowed on two of the PLLs.
capability
• I/O standards:
— Outputs: 1.8V to 3.3 V LVTTL/ LVCMOS
— Outputs: LVPECL, LVDS and HCSL
— Inputs: 3.3 V LVTTL/ LVCMOS
There are a total of four 8-bit output dividers. Each output
bank can be configured to support LVTTL, LVPECL, LVDS
or HCSL logic levels. Out0 (Output 0) supports 3.3V
single-ended standard only. The outputs are connected to
the PLLs via a switch matrix. The switch matrix allows the
user to route the PLL outputs to any output bank. This
feature can be used to simplify and optimize the board
layout. In addition, each output's slew rate and
enable/disable function is programmable.
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
Four internal PLLs
1
•
•
•
•
Programmable slew rate control
•
•
•
•
•
Individual output enable/disable
Programmable loop bandwidth
Programmable output inversion to reduce bimodal jitter
Redundant clock inputs with auto and manual switchover
options
Power-down mode
3.3V core VDD
Available in 24-QFN package
-40° to +85°C industrial temperature operation
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5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
Block Diagram
S
R
C
0
XIN/REF
XOUT
PLL0 (SS)
CLKIN
PLL1
OUT0
S
R
C
1
/DIV1
S
R
C
2
/DIV2
S
R
C
3
/DIV3
S
R
C
6
/DIV6
S1
OUT1
OUT2
CLKSEL
PLL2
PLL3 (SS)
SD/OE
S3
OUT3
OUT6
SDA
SCL
Control
Logic
SEL[2:0]
1. OUT1 & OUT2 and OUT3 & OUT6 pairs can be configured to be LVDS, LVPECL or HCSL, or two single-ended LVTTL outputs.
2. CLKIN, CLKSEL, SD/OE and SEL[2:0] have pull down resistors.
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
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EEPROM PROGRAMMABLE CLOCK GENERATOR
SEL2
SEL0
SEL1
SD/OE
GND
VDD
XOUT
XIN/REF
OUT0
Pin Configuration
19
1
OUT3
OUT6
GND
VDDx
CLKIN
AVDD
13
CLKSEL
SCLK
SDAT
VDD
OUT2
VDDO1
7
OUT1
GND
VDDO3
24-pin QFN
Pin Descriptions
Pin#
Pin Name
I/O
Pin Type
Pin Description
1
VDD
2
XOUT
3
XIN / REF
4
VDDx
5
CLKIN
6
GND
7
OUT1
O
Adjustable1
Configurable clock output 1.
8
OUT2
O
Adjustable1
Configurable clock output 2.
9
VDDO1
Power
Device power supply. Connect to 1.8 to 3.3V. Sets output voltage
levels for OUT1and OUT2.
10
VDD
Power
Device power supply. Connect to 3.3V.
11
SDAT
I/O
Open Drain
12
SCLK
I
LVTTL
I2C clock. An external pull-up resistor is required. See I2C
specification for pull-up value recommendation.
13
CLKSEL
I
LVTTL
Input clock selector. Weak internal pull down resistor.
14
AVDD
Power
Device analog power supply. Connect to 3.3V. Use filtered analog
power supply if available.
15
GND
Power
Connect to Ground.
16
OUT6
Power
Device power supply. Connect to 3.3V.
O
LVTTL
CRYSTAL_OUT – Reference crystal feedback.
I
LVTTL
CRYSTAL_IN – Reference crystal input or external reference clock
input.
Power
Crystal oscillator power supply. Connect to 3.3V through 5
resistor. Use filtered analog power supply if available.
LVTTL
Input clock. Weak internal pull down resistor.
Power
Connect to Ground.
I
O
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
Bidirectional I2C data. An external pull-up resistor is required. See
I2C specification for pull-up value recommendation.
Adjustable1
Configurable clock output 6.
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EEPROM PROGRAMMABLE CLOCK GENERATOR
Pin#
Pin Name
17
OUT3
18
VDDO3
19
SEL2
20
I/O
O
Pin Type
Adjustable
Pin Description
1
Configurable clock output 3.
Power
Device power supply. Connect to 1.8 to 3.3V. Sets output voltage
levels for OUT3 and OUT6.
I
LVTTL
Configuration select pin. Weak internal pull down resistor.
SEL1
I
LVTTL
Configuration select pin. Weak internal pull down resistor.
21
SEL0
I
LVTTL
Configuration select pin. Weak internal pull down resistor.
22
SD/OE
I
LVTTL
Enables/disables the outputs or powers down the chip. The SP bit
(0x02) controls the polarity of the signal to be either active HIGH or
LOW. (Default is active LOW.) Weak internal pull down resistor.
23
OUT0
O
Adjustable1
24
GND
Configurable clock output 0.
Power
Connect to Ground.
1.Outputs are user programmable to drive single-ended 3.3-V LVTTL, or differential LVDS, LVPECL or HCSL interface levels
2. Analog power plane should be isolated from a 3.3V power plane through a ferrite bead.
3. Each power pin should have a dedicated 0.01µF de-coupling capacitor. Digital VDDs may be tied together.
4. Unused clock inputs (REFIN or CLKIN) must be pulled high or low - they cannot be left floating. If the crystal oscillator is not used, XOUT must be left floating.
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
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PLL Features and Descriptions
7-bit
D
VCO
4-bit
12-bit
A
N
Sigm a-Delta
M odulator
PLL0 Block Diagram
7-bit
D
VCO
12-bit
N
PLL1, PLL2 and PLL3 Block Diagram
Pre-Divider
(D)1 Values
Multiplier
(M)2 Values
Programmable
Spread Spectrum
Loop Bandwidth Generation Capability
PLL0
1 - 127
10 - 8206
Yes
Yes
PLL1
1 - 127
1 - 4095
Yes
No
PLL2
1 - 127
1 - 4095
Yes
No
PLL3
3 - 127
12 - 4095
Yes
Yes
1.For PLL0, PLL1 and PLL2, D=0 means PLL power down. For PLL3, 0, 1, and 2 are DNU (do not use)
2.For PLL0, M = 2*N + A + 1 (for A > 0); M = 2*N (for A = 0); A < N-1. For PLL1, PLL2 and PLL3, M=N.
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
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EEPROM PROGRAMMABLE CLOCK GENERATOR
Reference Clock Input Pins and
Selection
XTAL load cap = 3.5pF + XTAL[4:0] * 0.125pF (Eq. 1)
The 5V49EE502 supports up to two clock inputs. One of the
clock inputs (XIN/ REF) can be driven by either an external
crystal or a reference clock. The second clock input (CLKIN)
can only be driven from an external reference clock. The
CLKSEL pin selects the input clock from either XTAL/REF or
CLKIN.
Bits
Step (pF)
Min (pF)
Max (pF)
XTAL
8
0.125
0
4
When using an external reference clock instead of a crystal
on the XTAL/REF pin, the input load capacitors may be
completely bypassed. This allows for the input frequency to
be up to 200MHz. When using an external reference clock,
the XOUT pin must be left floating, XTAL must be
programmed to the default value of “00h”, and the crystal
drive strength bit, XDRV (0x06), must be set to the default
value of “11h”.
Either clock input can be set as the primary clock. The
primary clock designation is to establish which is the main
reference clock to the PLLs. The non-primary clock is
designated as the secondary clock in case the primary clock
goes absent and a backup is needed. The PRIMSRC bit
(0xBE through 0xC3) determines which clock input will be
selected as primary clock. When PRIMSRC bit is “0”,
XIN/REF is selected as the primary clock, and when “1”,
CLKIN as the primary clock.
Switchover Modes
The 5V49EE502 features redundant clock inputs which
supports both Automatic and Manual switchover mode.
These two modes are determined by the configuration bits,
SM (0xBE through 0xC3). The primary clock source can be
programmed, via the PRIMSRC bit, to be either XIN/REF or
CLKIN. The other clock input will be considered as the
secondary source. Note that the switchover modes are
asynchronous. If the reference clocks are directly routed to
OUTx with no phase relationship, short pulses can be
generated during switchover. The automatic switchover
mode will work only when the primary clock source is
XIN/REF. Switchover modes are not supported for crystal
input configurations.
The two external reference clocks can be manually selected
using the CLKSEL pin. The SM bits (0xBE through 0xC3)
must be set to "0x" for manual switchover which is detailed
in SWITCHOVER MODES section.
Crystal Input (XIN/REF)
The crystal used should be a fundamental mode quartz
crystal; overtone crystals should not be used.
When the XIN/REF pin is driven by a crystal, it is important
to set the internal inverter oscillator drive strength and
tuning/load capacitor values correctly to achieve the best
clock performance. These values are programmable
through I2C interface to allow for maximum compatibility
with crystals from various manufacturers, processes,
performances, and qualities. The internal load capacitors
are true parallel-plate capacitors for ultra-linear
performance. Parallel-plate capacitors were chosen to
reduce the frequency shift that occurs when non-linear load
capacitance interacts with load, bias, supply, and
temperature changes. External non-linear crystal load
capacitors should not be used for applications that are
sensitive to absolute frequency requirements. The value of
the internal load capacitors are determined by XTAL[4:0]
bits. The load capacitance can be set with a resolution of
0.125pF for a total crystal load ranging from 3.5pF to 7.5pF.
Check with the crystal vendor's load capacitance
specification for the exact setting to tune the internal load
capacitor. The following equation governs how the total
internal load capacitance is set.
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
Parameter
Manual Switchover Mode
When SM[1:0] is "0x", the redundant inputs are in manual
switchover mode. In this mode, CLKSEL pin is used to
switch between the primary and secondary clock sources.
As previously mentioned, the primary and secondary clock
source setting is determined by the PRIMSRC bit. During
the switchover, no glitches will occur at the output of the
device, although there may be frequency and phase drift,
depending on the exact phase and frequency relationship
between the primary and secondary clocks.
Automatic Switchover Mode
The redundant inputs are in automatic switchover mode.
Automatic switchover mode has revertive functionality. The
input clock selection will switch to the secondary clock
source when there are no transitions on the primary clock
source for two secondary clock cycles. If both reference
clocks are at different frequencies, the device will always
remain on the primary clock unless it is absent for two
secondary clock cycles. The secondary clock must always
run at a frequency less than or equal to the primary clock
frequency.
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EEPROM PROGRAMMABLE CLOCK GENERATOR
Reference Divider, Feedback Divider, and
Output Divider
Each PLL incorporates a 7-bit reference divider (D[6:0]) and
a 12-bit feedback divider (N[11:0]) that allows the user to
generate four unique non-integer-related frequencies. Each
output divide supports 8-bit output-divider (PM and Q[7:0]).
The following equation governs how the output frequency is
calculated.
(M
)
D
Q[6:0]
PM
Output Divider
111 1111
0
Disabled
1
/1
0
/2
1
/((Q[6:0] + 2) * 2)
'0' and set NSSC[2:0],
SS_OFFSET[5:0], SD[3:0], and the A[3:0] (in the total M
value) accordingly. To disable spread spectrum generation,
set TSSC = '0'.
M = 2 * N + A + 1 (for A>0)
M = 2 * N (for A = 0)
For PLL1, PLL2 and PLL3,
M=N
PM and Q[6:0] are the bits used to program the 8-bit
output-dividers for outputs OUT1-6. OUT0 does not have
any output divide along its path. The 8-bit output-dividers
will bypass or divide down the output banks' frequency with
even integer values ranging from 2 to 256.
TSSC[3:0]
There is the option to choose between disabling the
output-divider, utilizing a div/1, a div/2, or the 7-bit Q-divider
by using the PM bit. If the output is disabled, it will be driven
High, Low or High Impedance, depending on OEM[1:0].
Each bank, except for OUT0, has a PM bit. When disabled,
no clocks will appear at the output of the divider, but will
remain powered on. The output divides selection table is
shown below.
These bits are used to determine the number of
phase/frequency detector cycles per spread spectrum cycle
(ssc) steps. The modulation frequency can be calculated
with the TSSC bits in conjunction with the NSSC bits. Valid
TSSC integer values for the modulation frequency range
from 5 to 14. Values of 0 – 4 and 15 should not be used.
NSSC[2:0]
These bits are used to determine the number of
delta-encoded samples used for a single quadrant of the
spread spectrum waveform. All four quadrants of the spread
spectrum waveform are mirror images of each other. The
modulation frequency is also calculated based on the NSSC
bits in conjunction with the TSSC bits. Valid NSSC integer
values range from 1 to 6. Values of 0 and 7 should not be
used.
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SS_OFFSET[5:0]
Modulation frequency:
These bits are used to program the fractional offset with
respect to the nominal M integer value. For center spread,
the SS_OFFSET is set to '0' so that the spread spectrum
waveform is centered about the nominal M (Mnom) value.
For down spread, the SS_OFFSET > '0' such the spread
spectrum waveform is centered about the (Mideal -1
+SS_Offset) value. The downspread percentage can be
thought of in terms of center spread. For example, a
downspread of -1% can also be considered as a center
spread of ±0.5% but with Mnom shifted down by one and
offset. The SS_OFFSET has integer values ranging from 0
to 63.
FPFD = FIN / D (Eq. 6)
FVCO = FPFD * MNOM (Eq. 7)
FSSC = FPFD / (4 * Nssc * Tssc) (Eq. 8)
Spread:
= SD0 + SD1 + SD2 + …+ SD11
the number of samples used depends on the NSSC value
63 - SS_OFFSET
SD[3:0]
±Spread% = (* 100)/(64 * (2*N[11:0] + A[3:0] + 1) (Eq. 9)
These bits are used to shape the profile of the spread
spectrum waveform. These are delta-encoded samples of
the waveform. There are twelve sets of SD samples. The
NSSC bits determine how many of these samples are used
for the waveform. The sum of these delta-encoded samples
(sigma delta- encoded samples) determine the amount of
spread and should not exceed (63 - SS_OFFSET). The
maximum spread is inversely proportional to the nominal M
integer value.
±Max Spread% / 100 = 1 / MNOM or 2 / MNOM (X2=1)
DITH
This bit is used for dithering the sigma-delta-encoded
samples. This will randomize the least-significant bit of the
input to the spread spectrum modulator. Set the bit to '1' to
enable dithering.
X2
This bit will double the total value of the
sigma-delta-encoded-samples which will increase the
amplitude of the spread spectrum waveform by a factor of
two. When X2 is '0', the amplitude remains nominal but if set
to '1', the amplitude is increased by x2. The following
equations govern how the spread spectrum is set:
TSSC = TSSC[3:0] + 2 (Eq. 2)
NSSC = NSSC[2:0] * 2 (Eq. 3)
SD[3:0]K = SJ+1(unencoded) - SJ(unencoded) (Eq. 4)
where SJ is the unencoded sample out of a possible 12 and
SDK is the delta-encoded sample out of a possible 12.
Amplitude = ((2*N[11:0] + A[3:0] + 1) * Spread% / 100) /2
(Eq. 5)
if 1 < Amplitude < 2, then set X2 bit to '1'.
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Profile:
Tssc = 14 + 2 = 16
Waveform starts with SS_OFFSET, SS_OFFSET + SDJ,
SS_OFFSET + SDJ+1, etc.
Nssc = 6 × 2 = 12
Nssc × Tssc = 192
Spread Spectrum Using Sinusoidal Profile
Use Eq.10 to determine the value of the
sigma-delta-encoded samples.
±2% = * 100)/(64 × 48)
= 61.4
Either round up or down to the nearest integer value.
Therefore, we end up with 61 or 62 for sigma-delta-encoded
samples. Since the sigma-delta-encoded samples must not
exceed 63 with SS_OFFSET set to '0', 61 or 62 is well within
the limits. It is the discretion of the user to define the shape
of the profile that is better suited for the intended application.
Using Eq. 9 again, the actual spread for the
sigma-delta-encoded samples of 56 and 57 are ±1.99% and
±2.02%, respectively.
Use Eq.10 to determine if the X2 bit needs to be set;
Amplitude = 48 × (1.99 or 2.02) / 100/2 = 0.48 < 1
Therefore, the X2 = '0 '. The dither bit is left to the discretion
of the user.
Example
FIN = 25MHz, FOUT = 100MHz, Fssc = 33kHz with center
spread of ±2%. Find the necessary spread spectrum
register settings.
The example above was of a center spread using spread
spectrum. For down spread, the nominal M value can be set
one integer value lower to 47.
Since the spread is center, the SS_OFFSET can be set to
'0'. Solve for the nominal M value; keep in mind that the
nominal M should be chosen to maximize
Note that the 5V49EE502 should not be programmed with
TSSC > '0', SS_OFFSET = '0', and SD = '0' in order to
prevent an unstable state in the modulator.
the VCO. Start with D = 1, using Eq.6 and Eq.7.
The PLL loop bandwidth must be at least 10x the
modulation frequency along with higher damping (larger
uz) to prevent the spread spectrum from being filtered and
reduce extraneous noise. Refer to the LOOP FILTER
section for more detail on uz. The A[3:0] must be used for
spread spectrum, even if the total multiplier value is an even
integer.
MNOM = 1200MHz / 25MHz = 48
Using Eq.4, we arbitrarily choose N = 22, A = 3. Now that we
have the nominal M value, we can determine TSSC and
NSSC by using Eq.8.
Nssc × Tssc = 25MHz / (33kHz × 4) = 190
However, using Eq. 2 and Eq.3, we find that the closest
value is when TSSC = 14 and NSSC = 6. Keep in mind to
maximize the number of samples used to enhance the
profile of the spread spectrum waveform.
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Spread Spectrum Generation (PLL3)
Zero capacitor (Cz) = 196pF + CZ × 217pF
PLL3 support spread spectrum generation capability, which
users have the option of turning on and off. Spread
spectrum profile, frequency, and spread are fully
programmable (within limits). The technique is different from
that used in PLL0. The programmable spread spectrum
generation parameters are SS_D3[7:0], SSVCO[15:0],
SSENB, IP3[4:0] and RZ3[3:0] bits. These bits are in the
memory address range of 0x4C to 0x85 for PLL3. The
spread spectrum generation on PLL3 can be
enabled/disabled using the SSENB bit. To enable spread
spectrum, set SSENB = '1'.
Pole capacitor (Cp) = 15pF
Charge pump (Ip) = 6 × (IP[0] + 2 × IP[1]+4 × IP[2]) uA
VCO gain (KVCO) = 900 MHz/V × 2
The following equations govern how the loop filter is set for
PLL3:
For Non-Spread Spectrum Operation:
Resistor(Rz) =
For Spread Enabled:
Spread spectrum is configured using SS_D3(spread
spectrum reference divide)
SS_D3 =
FIN
4 * FMOD
(12.5 + 12.5*(RZ[1] + 2*RZ[2] + 4*RZ[3]))
kOhms (Eq. 12)
* RZ[0] + 6*(1 – RZ[0])
For Spread Spectrum Operation:
(Eq. 10)
Resistor(Rz) =
(62.5 + 12.5*(RZ[1] + 2*RZ[2] + 4*RZ[3]))
kOhms (Eq. 13)
* RZ[0] + 6*(1 – RZ[0])
and SSVCO (spread spectrum loop feedback counter).
SSVCO = [0.5 *
FVCO
FMOD
Zero capacitor (Cz) = 250pF
* ( 1 + SS/400) + 5] (Eq. 11)
Pole capacitor (Cp) = 15pF
For Non-Spread Spectrum Operation:
SS is the total Spread Spectrum amount (I.e. center spread
+0.5% has a total spread of 1.0% and down spread -0.5%
has a total spread of 0.5%.)
24 * (1 + (2 * IP[0]) + (4 * IP[1]) + (8 * IP[2])) A (Eq. 14)
Charge
=
pump (Ip)
3 + (5 * IP[3]) + (11 * IP[4])
Loop Filter
For Spread Spectrum Operation:
The loop filter for each PLL can be programmed to optimize
the jitter performance. The low-pass frequency response of
the PLL is the mechanism that dictates the jitter transfer
characteristics. The loop bandwidth can be extracted from
the jitter transfer. A narrow loop bandwidth is good for jitter
attenuation while a wide loop bandwidth is best for low-jitter
frequency generation. The specific loop filter components
that can be programmed are the resistor via the RZ[3:0] bits,
zero capacitor via the CZ bit (for PLL0, PLL1 and PLL2), and
the charge pump current via the IP[2:0] bits (for PLL0, PLL1
and PLL2) or IP[3:0] (for PLL3).
12 * (1 + (2 * IP[0]) + (4 * IP[1]) + (8 * IP[2])) A (Eq. 14)
Charge
=
pump (Ip)
27 + (5 * IP[3]) + (11 * IP[4])
VCO gain (KVCO) = 900 MHz/V × 2
The following equations govern how the loop filter is set for
PLL0 - PLL2:
Resistor (Rz) = (RZ[0] + 2 × RZ[1]+4 × RZ[2] + 8 × RZ[3]) ×
4.0kOhm
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PLL Loop Bandwidth:
Charge pump gain (K) = Ip / 2
VCO gain (KVCO) = 900 MHz/V × 2
M = Total multiplier value (See the Reference Divider,
Feedback Divider and Output Divider section for more
detail)
c = (Rz × K× KVCO × Cz)/(M × (Cz + Cp))
Fc = c / 2
Note, the phase/frequency detector frequency (FPFD) is
typically seven times the PLL closed-loop bandwidth (Fc)
but too high of a ratio will reduce the phase margin thus
compromising loop stability.
To determine if the loop is stable, the phase margin (m)
needs to be calculated as follows.
Phase Margin:
z = 1 / (Rz × Cz)
p = (Cz + Cp)/(Rz × Cz × Cp)
m = (360 / 2) * [tan-1(c/ z) - tan-1(c/ p)]
To ensure stability in the loop, the phase margin is
recommended to be > 60° but too high will result in the lock
time being excessively long. Certain loop filter parameters
would need to be compromised to not only meet a required
loop bandwidth but to also maintain loop stability.
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SEL[2:0] Function
SD/OE Pin Function
The 5V49EE502 can support up to six unique
configurations. Users may pre-programmed all these
configurations, and select the configurations using SEL[2:0]
pins. Alternatively, users may use I2C interface to configure
these registers on-the-fly.
SEL2 SEL1 SEL0
The polarity of the SD/OE signal pin can be programmed to
be either active HIGH or LOW with the SP bit (0x02). When
SP is “0” (default), the pin becomes active LOW and when
SP is “1”, the pin becomes active HIGH. The SD/OE pin can
be configured as either to shutdown the PLLs or to
enable/disable the outputs.
Configuration Selections
0
0
0
Select CONFIG0
0
0
1
Select CONFIG1
0
1
0
Select CONFIG2
0
1
1
Select CONFIG3
1
0
0
Select CONFIG4
1
0
1
Select CONFIG5
1
1
0
Reserved (Do not use)
1
1
1
Reserved (Do not use)
OUTn
SP
SD/OE Input
OE
Global Shutdown
SH
Truth Table
SH bit SP bit OSn bit OEn bit SD/OE
Crystal/Clock Selection
XTCLKSEL bit is used to bypass a crystal oscillator circuit
when external clock source is used.
PRIMSRC bit is used to select a primary clock from
XIN/REF and CLKIN.
PRIMSRC bit Primary
0
XIN/REF
1
CLKIN
CLKSEL input
0
1
CLKSEL
0
0
1
1
SMx[1:0] Switching Mode
0x
10
11
Secondary
CLKIN
XIN/REF
Clock Source
Primary Clock Source
Secondary Clock Source
PRIMSRC
0
1
0
1
Manual
Auto
Auto-Revertive
Reference Clock
XIN/REF
CLKIN
CLKIN
XIN/REF
OUTn
0
0
0
0
0
0
0
0
0
1
1
1
x
0
1
1
x
x
0
1
High-Z2
Enabled
Enabled
Suspended
0
0
0
0
1
1
1
1
0
1
1
1
x
0
1
1
x
x
0
1
High-Z2
Enabled
Suspended
Enabled
1
1
1
0
0
0
0
1
1
x
0
1
0
0
0
High-Z2
Enabled
Enabled
1
1
1
1
1
1
1
x
0
1
1
x
x
0
1
x
0
0
0
1
High-Z2
Enabled
Suspended
Suspended 1
Note 1 : Global Shutdown
Note 2 : Hi-Z regardless of OEM bits
Configuration OUTx IO Standard
Primary to Secondary to
Secondary Primary
No
No
Yes
No
Yes
Yes
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
OS
Users can configure the individual output IO standard from
a specified 1.8V to 3.3V power supplies. Each output can
support 1.8V to 3.3V LVTTL. Each output pair can support
LVDS, LVPECL or HCSL from the specified 3.3V power
supply. OUT0 can only be 3.3V single-ended output.
12
5V49EE502
JUNE 18, 2018
5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
Programming the Device
The frame formats are shown in the following illustration.
I2C may be used to program the 5V49EE502.
– Device (slave) address = 7'b1101010
I2C Programming
The 5V49EE502 is programmed through an I2C-Bus serial
interface, and is an I2C slave device. The read and write
transfer formats are supported. The first byte of data after a
write frame to the correct slave address is interpreted as the
register address; this address auto-increments after each
byte written or read.
Framing
Each frame starts with a “Start Condition” and ends with an “End Condition”. These are both generated by the Master
device.
MSB
1
LSB
1
0
1
0
1
0
R/W
7-bit slave address
R/W
0 – Slave will be written by master
1 – Slave will be read by master
ACK from Slave
The first byte transmitted by the Master is the Slave Address followed by the R/W bit.
The Slave acknowledges by sending a “1” bit.
First Byte Transmitted on I2C Bus
External I2C Interface Condition
KEY:
From Master to Slave
From Master to Slave, but can be omitted if followed by the correct sequence
Normally, data transfer is terminated by a STOP condition generated by the Master. However, if the Master still wishes to communicate on the bus, it can
generate a separate START condition, and address another Slave address without first generating a STOP condition.
From Slave to Master
SYMBOLS:
ACK - Acknowledge (SDAT LOW)
NACK – Not Acknowledge (SDAT HIGH)
SR – Repeated Start Condition
S – START Condition
P – STOP Condition
Progwrite
S
Address
R/W
ACK
Command Code
ACK
Register
ACK
Data
ACK
7-bits
0
1-bit
8-bits: xxxx xx00
1-bit
8-bits
1-bit
8-bits
1-bit
P
Progwrite Command Frame
Writes can continue as long as a Stop condition is not sent and each byte will increment the register address.
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
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5V49EE502
JUNE 18, 2018
5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
Progread
Note: If the expected read command is not from the next higher register to the previous read or write command, then set a
known “read” register address prior to a read operation by issuing the following command:
S
Address
R/W
ACK
Command Code
ACK
Register
ACK
7-bits
0
1-bit
8-bits: xxxx xx00
1-bit
8-bits
1-bit
P
Prior to Progread Command Set Register Address
The user can ignore the STOP condition above and use a repeated START condition instead, straight after the slave
acknowledgement bit (i.e., followed by the Progread command):
S
Address
R/W
ACK
ID Byte
ACK
Data_1
ACK
Data_2
ACK
7-bits
1
1-bit
8-bits
1-bit
8-bits
1-bit
8-bits
1-bit
Data_last NACK
8-bits
P
1-bit
Progread Command Frame
Progsave
S
Address
R/W
ACK
Command Code
ACK
7-bits
0
1-bit
8-bits: xxxx xx01
1-bit
P
Note:
PROGWRITE is for writing to the 5V49EE502 registers.
PROGREAD is for reading the 5V49EE502 registers.
PROGSAVE is for saving all the contents of the 5V49EE502 registers to the EEPROM.
PROGRESTORE is for loading the entire EEPROM contents to the 5V49EE502 registers.
Progrestore
S
Address
R/W
ACK
Command Code
ACK
7-bits
0
1-bit
8-bits: xxxx xx10
1-bit
P
EEPROM Interface
The 5V49EE502 can also store its configuration in an internal EEPROM. The contents of the device's internal programming
registers can be saved to the EEPROM by issuing a save instruction (ProgSave) and can be loaded back to the internal
programming registers by issuing a restore instruction (ProgRestore).
To initiate a save or restore using I2C, only two bytes are transferred. The Device Address is issued with the read/write bit
set to “0”, followed by the appropriate command code. The save or restore instruction executes after the STOP condition is
issued by the Master, during which time the 5V49EE502 will not generate Acknowledge bits. The 5V49EE502 will
acknowledge the instructions after it has completed execution of them. During that time, the I2C bus should be interpreted
as busy by all other users of the bus.
On power-up of the 5V49EE502, an automatic restore is performed to load the EEPROM contents into the internal
programming registers. The 5V49EE502 will be ready to accept a programming instruction once it acknowledges its 7-bit I2C
address.
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
14
5V49EE502
JUNE 18, 2018
5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
I2C Bus DC Characteristics
Symbol
Parameter
VIH
Input HIGH Level
VIL
Input LOW Level
VHYS
IIN
Conditions
Min
Typ
Max
0.7xVDD
V
0.3xVDD
Hysteresis of Inputs
0.05xVDD
Output LOW Voltage
V
V
Input Leakage Current
VOL
Unit
IOL = 3 mA
±1.0
µA
0.4
V
I2C Bus AC Characteristics for Standard Mode
Symbol
FSCLK
tBUF
Parameter
Min
Serial Clock Frequency (SCL)
0
Typ
Max
Unit
100
kHz
Bus free time between STOP and START
4.7
µs
tSU:START
Setup Time, START
4.7
µs
tHD:START
Hold Time, START
4
µs
tSU:DATA
Setup Time, data input (SDA)
250
ns
tHD:DATA
Hold Time, data input (SDA) 1
0
µs
tOVD
Output data valid from clock
3.45
µs
CB
Capacitive Load for Each Bus Line
400
pF
tR
Rise Time, data and clock (SDAT, SCLK)
1000
ns
tF
Fall Time, data and clock (SDAT, SCLK)
300
ns
tHIGH
HIGH Time, clock (SCLK)
4
µs
tLOW
LOW Time, clock (SCLK)
4.7
µs
4
µs
tSU:STOP
Setup Time, STOP
Note 1: A device must internally provide a hold time of at least 300 ns for the SDAT signal (referred to the VIH(MIN)
of the SCLK signal) to bridge the undefined region of the falling edge of SCLK.
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
15
5V49EE502
JUNE 18, 2018
5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
I2C Bus AC Characteristics for Fast Mode
Symbol
FSCLK
tBUF
Parameter
Min
Serial Clock Frequency (SCL)
0
Typ
Max
Unit
400
kHz
Bus free time between STOP and START
1.3
µs
tSU:START
Setup Time, START
0.6
µs
tHD:START
Hold Time, START
0.6
µs
tSU:DATA
Setup Time, data input (SDA)
100
ns
tHD:DATA
Hold Time, data input (SDA)
1
0
µs
tOVD
Output data valid from clock
0.9
µs
CB
Capacitive Load for Each Bus Line
400
pF
tR
Rise Time, data and clock (SDA, SCL)
20 + 0.1xCB
300
ns
tF
Fall Time, data and clock (SDA, SCL)
20 + 0.1xCB
300
ns
tHIGH
HIGH Time, clock (SCL)
0.6
µs
tLOW
LOW Time, clock (SCL)
1.3
µs
Setup Time, STOP
0.6
µs
tSU:STOP
Note 1: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(MIN)
of the SCL signal) to bridge the undefined region of the falling edge of SCL.
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
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5V49EE502
JUNE 18, 2018
5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 5V49EE502. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any
other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only
over the recommended operating temperature range.
Symbol
VDD
VI
Description
Min
Max
Unit
-0.5
+4.6
V
-0.5
+4.6
V
-0.5
VDD+0.5
V
150
°C
150
°C
Internal Power Supply Voltage
Input Voltage
1
VO
Output Voltage (not to exceed
TJ
Junction Temperature
TSTG
Storage Temperature
4.6V)1
-65
1.Input negative and output voltage ratings may be exceeded if the input and output current ratings are observed.
Recommended Operation Conditions
Symbol
Parameter
Min
Typ
Max
Unit
VDD
Power supply voltage for VDD pins supporting core and
outputs
3.135
3.3
3.465
V
VDDX
Power supply voltage for crystal oscillator. Use filtered
analog power supply if available.
3.135
3.3
3.465
V
AVDD
Analog power supply voltage. Use filtered analog
power supply if available.
3.135
3.3
3.465
V
VDDOX
3.3V VDDO Range
3.0
3.3
3.6
V
2.5V VDDO Range for 2.5V LVTTL
2.25
2.5
2.75
V
1.8V VDDO Range for 1.8V LVTTL
1.7
1.8
1.9
V
3.135
3.3
3.465
V
+85
°C
15
pF
8
pF
MHz
Power supply voltage for VDD pins supporting
LVDS/LVPECL/HCSL outputs
TA
Operating temperature, ambient
-40
CLOAD_OUT Maximum load capacitance (3.3V LVTTL only)
Maximum load capacitance (1.8V/2.5V LVTTL only)
FIN
tPU
External reference crystal
8
50
External reference clock CLKIN
1
200
0.05
5
Power up time for all VDDs to reach minimum specified
voltage (power ramps must be monotonic)
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
17
5V49EE502
ms
JUNE 18, 2018
5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
Capacitance (TA = +25 °C)
Symbol
Parameter
CIN
Min
Input Capacitance (CLKIN, CLKSEL, SD/OE,
SDA, SCL, SEL[2:0])
Pull-down
Resistor
CLKIN, CLKSEL, SD/OE, SEL[2:0]
Typ
Max
Unit
3
7
pF
180
k
Crystal Specifications
XTAL_FREQ
Crystal frequency
8
XTAL_MIN
Minimum crystal load capacitance
XTAL_MAX
Maximum crystal load capacitance
XTAL_VPP
Voltage swing (peak-to-peak, nominal)
50
MHz
3.5
pF
1.5
35.5
pF
3.2
V
2.3
DC Electrical Characteristics for 3.3-V LVTTL 1
Symbol
Parameter
Test Conditions
Min
Typ
Unit
VDD
V
0.4
V
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
0.8
V
Output Leakage Current 3-state outputs. VO = VDD or GND,
VDD = 3.6V
10
µA
IOZDD
2.4
Max
2
V
Note 1: See “Recommended Operating Conditions” table.
Power Supply Characteristics for PLLs and LVTTL Outputs
Total Supply Current Vs PLL Frequency
Supply current Vs Output Frequency
80
70
60
Supply Current(mA)
Total Supply Current(mA)
70
50
40
30
20
10
60
50
40
30
20
10
0
0
200
400
600
800
1000
0
1200
0
PLL Frequency(MHz)
25
50
75
100
125
150
175
200
Output Frequency(MHz)
PLL0 ON IDD(mA)
PLL0+PLL1 On IDD(mA)
No outputs
REF output on
PLL0+PLL1+PLL2 on IDD(mA)
All Plls ON IDD(mA)
4 outputs on
5 outputs on
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
18
2 outputs on
5V49EE502
3 outputs on
JUNE 18, 2018
5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
DC Electrical Characteristics for LVDS
Symbol
Parameter
Min
Typ
Max
Unit
VOT (+)
Differential Output Voltage for the TRUE binary state
247
454
mV
VOT (-)
Differential Output Voltage for the FALSE binary state
-247
-454
mV
50
mV
1.375
V
50
mV
VOT
VOS
Change in VOT between Complimentary Output States
Output Common Mode Voltage (Offset Voltage)
VOS
1.125
1.2
Change in VOS between Complimentary Output States
IOS
Outputs Short Circuit Current, VOUT+ or VOUT- = 0V or VDD
9
24
mA
IOSD
Differential Outputs Short Circuit Current, VOUT+ = VOUT-
6
12
mA
Power Supply Characteristics for LVDS Outputs 1
Symbol
Test Conditions 2
Parameter
Typ
Max
Unit
IDDQ
Quiescent VDD Power
Supply Current
REF = LOW
Outputs enabled, all outputs unloaded
68
90
mA
IDDD
Dynamic VDD Power Supply
Current per Output
VDD = Max., CL = 0pF
30
45
µA/MHz
ITOT
Total Power VDD Supply
Current
FREFERENCE CLOCK = 100MHz, CL = 2pF
86
130
mA
FREFERENCE CLOCK = 200MHz, CL = 2pF
100
150
FREFERENCE CLOCK = 400MHz, CL = 2pF
122
190
Note 1: Output banks 4 and 5 are toggling. Other output banks are powered down.
Note 2: The termination resistors are excluded from these measurements.
DC Electrical Characteristics for LVPECL
Symbol
Parameter
Min
Typ
Max
Unit
VOH
Output Voltage HIGH, terminated through 50 tied to VDD - 2V
VDD - 1.2
VDD - 0.9
V
VOL
Output Voltage LOW, terminated through 50 tied to VDD - 2V
VDD - 1.95
VDD - 1.61
V
0.55
0.93
V
VSWING
Peak-to-Peak Output Voltage Swing
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
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5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
Power Supply Characteristics for LVPECL Outputs 1
Symbol
Test Conditions 2
Parameter
Typ
Max
Unit
IDDQ
Quiescent VDD Power
Supply Current
REF = LOW
Outputs enabled, all outputs unloaded
86
110
mA
IDDD
Dynamic VDD Power Supply
Current per Output
VDD = Max., CL = 0pF
35
50
µA/MHz
ITOT
Total Power VDD Supply
Current
FREFERENCE CLOCK = 100MHz, CL = 2pF
120
180
mA
FREFERENCE CLOCK = 200MHz, CL = 2pF
130
190
FREFERENCE CLOCK = 400MHz, CL = 2pF
140
210
Note 1: Output banks 4 and 5 are toggling. Other output banks are powered down.
Note 2: The termination resistors are excluded from these measurements.
DC Electrical Characteristics for HCSL
Symbol
Parameter
Min
Typ
Max
Unit
VOH
Output Voltage HIGH
660
700
850
mV
VOL
Output Voltage LOW
-150
0
27
mV
Absolute
250
350
550
mV
Crossing Point
Voltage
Power Supply Characteristics for HCSL Outputs 1
Symbol
Test Conditions 2
Parameter
Typ
Max
Unit
IDDQ
Quiescent VDD Power
Supply Current
REF = LOW
Outputs enabled, all outputs unloaded
68
90
mA
IDDD
Dynamic VDD Power Supply
Current per Output
VDD = Max., CL = 0pF
30
45
µA/MHz
ITOT
Total Power VDD Supply
Current
FREFERENCE CLOCK = 100MHz, CL = 2pF
86
130
mA
FREFERENCE CLOCK = 200MHz, CL = 2pF
100
150
FREFERENCE CLOCK = 400MHz, CL = 2pF
122
190
Note 1: Output banks 4 and 5 are toggling. Other output banks are powered down.
Note 2: The termination resistors are excluded from these measurements.
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
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5V49EE502
JUNE 18, 2018
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EEPROM PROGRAMMABLE CLOCK GENERATOR
AC Timing Electrical Characteristics
(Spread Spectrum Generation = OFF)
Symbol
fIN 1
1 / t1
Parameter
Input Frequency
Output Frequency
Test Conditions
Min.
Typ.
Max.
Units
Input frequency limit (CLKIN)
1
200
MHz
Input frequency limit (XIN/REF)
8
100
MHz
Single ended clock output limit (LVTTL)
0.001
200
MHz
Differential clock output limit (LVPECL/
LVDS/HCSL)
0.001
500
fVCO
VCO Frequency
VCO operating frequency range
100
1200
MHz
fPFD
PFD Frequency
PFD operating frequency range
0.5 1
100
MHz
fBW
Loop Bandwidth
Based on loop filter resistor and capacitor
values
0.01
10
MHz
t2
Input Duty Cycle
Duty Cycle for input
40
60
%
t3
Output Duty Cycle
Measured at VDD/2, all outputs except
Reference output
45
55
%
Measured at VDD/2, Reference output
40
60
%
t4
2
t5
Slew Rate, SLEW[1:0] = 00
Single-ended 3.3V LVCMOS output clock rise
and fall time, 20% to 80% of VDD
(Output Load = 5pF)
3.5
Slew Rate, SLEW[1:0] = 01
Single-ended 3.3V LVCMOS output clock rise
and fall time, 20% to 80% of VDD
(Output Load = 5pF)
2.75
Slew Rate, SLEW[1:0] = 10
Single-ended 3.3V LVCMOS output clock rise
and fall time, 20% to 80% of VDD
(Output Load = 5pF)
2
Slew Rate, SLEW[1:0] = 11
Single-ended 3.3V LVCMOS output clock rise
and fall time, 20% to 80% of VDD
(Output Load = 5pF)
1.25
Rise Times
LVDS, 20% to 80%
600
Fall Times
LVDS, 80% to 20%
600
Rise Times
LVPECL, 20% to 80%
600
Fall Times
LVPECL, 80% to 20%
600
Rise Times
HCSL, From 0.175 V to 0.525 V
175
400
700
HCSL, From 0.525 V to 0.175 V
175
400
700
Peak-to-peak period jitter, 1PLL, multiple
output frequencies switching, LVTTL outputs
80
100
ps
Peak-to-peak period jitter, all 4 PLLs on,
LVTTL outputs3
200
270
ps
Peak-to-peak period jitter, 1PLL, multiple
output frequencies switching, LVPECL, LVDS
or HCSL outputs
60
80
ps
Peak-to-peak period jitter, all 4 PLLs on,
LVPECL, LVDS or HCSL outputs
120
160
ps
Fall Times
t7
Clock Jitter
6
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
21
5V49EE502
V/ns
ps
ps
ps
JUNE 18, 2018
5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
Symbol
Parameter
t8
t9 4
t10
5
Test Conditions
Output Skew
Skew between output to output on the same
bank
Lock Time
PLL lock time from power-up
Lock Time
PLL lock time from shutdown mode
Min.
Typ.
10
Max.
Units
75
ps
20
ms
2
ms
1.Practical lower frequency is determined by loop filter settings.
2.A slew rate of 2.75V/ns or greater should be selected for output frequencies of 100MHz or higher.
3.Jitter measured with clock outputs of 27MHz, 48MHz, 24.576MHz, 74.25MHz and 25MHz.
4.Includes loading the configuration bits from EEPROM to PLL registers. It does not include EEPROM programming/write time.
5.Actual PLL lock time depends on the loop configuration.
6. Not guaranteed until customer specific configuration is approved by IDT.
Spread Spectrum Generation Specifications
Symbol
fIN
1
Description
Min
Input Frequency Input Frequency Limit
fMOD
fSPREAD
Parameter
2
Typ
1
33
Max
Unit
400
MHz
120
kHz
%fOUT
Mod Frequency
Modulation Frequency
Spread Value
Amount of Spread Value (programmable) – Down Spread
-0.5
-4.0
Amount of Spread Value (programmable) – Center Spread
±0.25
±2.0
1.Practical lower frequency is determined by loop filter settings.
2. Not guaranteed until customer specific configuration is approved by IDT.
Test Circuits and Conditions
VDDOx
VDD
0.1µF
CLKOUT
OUTx
0.1µF
CL
GND
Test Circuits for DC Outputs
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
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EEPROM PROGRAMMABLE CLOCK GENERATOR
Other Termination Scheme (Block Diagram)
2 pF
CLKOUT
OUTx
OUTx
CLKOUT
5 pF
CLKOUT
2 pF
GND
GND
LVDS: 100 between differential outputs
LVTTL: 5 pF for each output
VDD-2V
49.9 Ohm
49.9 Ohm
2 pF
2 pF
33 Ohm
CLKOUT
CLKOUT
OUTx
OUTx
33 Ohm
CLKOUT
CLKOUT
2 pF
49.9 Ohm
49.9 Ohm
2 pF
GND
GND
VDD-2V
LVPECL
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
GND
HCSL
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EEPROM PROGRAMMABLE CLOCK GENERATOR
Programming Registers Table
Default
Register
Addr
Hex
Value
Bit #
7
0x00
00
0x01
00
0x02
02
SP
0x03
02
Reserved
0x04
0F
SH
0x05
04
0x06
00
0x07
00
0x08
00
6
5
4
3
2
1
Reserved
HW/SW
Reserved
OE6
OE5
SEL[2:0]
OE4
OE3
OE2
OE1
OS*[6:0]
Reserved
Reserved
Description
0
XTCLKSEL
Hardware/Software Mode control
HW/SW - 0=HW, 1=SW
SEL[2:0] - selects configuration in
SW mode
OE0
OEx=Output Power Suspend
function for OUTx (‘1’=OUTx will be
suspended on SD/OE pin. Disable
mode is defined by OEMx bits),
‘0’=outputs enabled and no
association with OE pin (default).
OS*[6:0] - output suspend, active
low. Overwrites OE setting.
PLLS*[3:0]
PLLS*[3:0] - PLL Suspend, active
low
SH - shutdown/OE configuration
Reserved
XTCLKSEL - crystal/clock select.
0=crystal, 1=ICLK
Reserved
XTAL[4:0]
Reserved
XTAL[4:0] - crystal cap
Reserved
0x09
00
0x0A
10
CZ0_CFG4
IP0[2:0]_CFG4
RZ0[3:0]_CFG4
0x0B
10
CZ0_CFG5
IP0[2:0]_CFG5
RZ0[3:0]_CFG5
0x0C
10
CZ0_CFG0
IP0[2:0]_CFG0
RZ0[3:0]_CFG0
0x0D
10
CZ0_CFG1
IP0[2:0]_CFG1
RZ0[3:0]_CFG1
0x0E
10
CZ0_CFG2
IP0[2:0]_CFG2
RZ0[3:0]_CFG2
0x0F
10
CZ0_CFG3
IP0[2:0]_CFG3
0x10
00
Reserved
D0[6:0]_CFG0
0x11
00
Reserved
D0[6:0]_CFG1
0x12
00
Reserved
D0[6:0]_CFG2
0x13
00
Reserved
D0[6:0]_CFG3
0x14
00
Reserved
D0[6:0]_CFG4
0x15
00
Reserved
0x16
01
N0[7:0]_CFG4
0x17
01
N0[7:0]_CFG5
0x18
01
N0[7:0]_CFG0
0x19
01
N0[7:0]_CFG1
0x1A
01
N0[7:0]_CFG2
0x1B
01
0x1C
00
A0[3:0]_CFG0
N0[11:8]_CFG0
0x1D
00
A0[3:0]_CFG1
N0[11:8]_CFG1
0x1E
00
A0[3:0]_CFG2
N0[11:8]_CFG2
0x1F
00
A0[3:0]_CFG3
N0[11:8]_CFG3
0x20
00
A0[3:0]_CFG4
N0[11:8]_CFG4
0x21
00
A0[3:0]_CFG5
0x22
10
CZ1_CFG4
IP1[2:0]_CFG4
RZ1[3:0]_CFG4
0x23
10
CZ1_CFG5
IP1[2:0]_CFG5
RZ1[3:0]_CFG5
0x24
10
CZ1_CFG0
IP1[2:0]_CFG0
RZ1[3:0]_CFG0
0x25
10
CZ1_CFG1
IP1[2:0]_CFG1
RZ1[3:0]_CFG1
0x26
10
CZ1_CFG2
IP1[2:0]_CFG2
RZ1[3:0]_CFG2
0x27
10
CZ1_CFG3
IP1[2:0]_CFG3
RZ1[3:0]_CFG3
Reserved
PLL0 loop parameter
RZ0[3:0]_CFG3
PLL0 input divider and input sell
D0[6:0] - 127 step Ref Div
D0 = 0 means power down.
D0[6:0]_CFG5
N - Feedback Divider
2 - 4095 (values of “0” and “1” are
not allowed) Total feedback with A,
using provided calculation
N0[7:0]_CFG3
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
N0[11:8]_CFG5
24
PLL1 Loop Parameter
5V49EE502
JUNE 18, 2018
5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
Default
Register
Addr
Hex
Value
Bit #
7
6
5
4
3
2
1
0x28
00
Reserved
D1[6:0]_CFG0
0x29
00
Reserved
D1[6:0]_CFG1
0x2A
00
Reserved
D1[6:0]_CFG2
0x2B
00
Reserved
D1[6:0]_CFG3
0x2C
00
Reserved
D1[6:0]_CFG4
0x2D
00
Reserved
0x2E
01
N1[7:0]_CFG4
0x2F
01
N1[7:0]_CFG5
0x30
01
N1[7:0]_CFG0
0x31
01
N1[7:0]_CFG1
0x32
01
N1[7:0]_CFG2
0x33
01
0x34
00
N3[11:8]_CFG0
N1[11:8]_CFG0
0x35
00
N3[11:8]_CFG1
N1[11:8]_CFG1
0x36
00
N3[11:8]_CFG2
N1[11:8]_CFG2
0x37
00
N3[11:8]_CFG3
N1[11:8]_CFG3
0x38
00
N3[11:8]_CFG4
N1[11:8]_CFG4
0x39
00
N3[11:8]_CFG5
0x3A
00
CZ2_CFG4
IP2[2:0]_CFG4
RZ2[3:0]_CFG4
0x3B
00
CZ2_CFG5
IP2[2:0]_CFG5
RZ2[3:0]_CFG5
0x3C
00
CZ2_CFG0
IP2[2:0]_CFG0
RZ2[3:0]_CFG0
0x3D
00
CZ2_CFG1
IP2[2:0]_CFG1
RZ2[3:0]_CFG1
0x3E
00
CZ2_CFG2
IP2[2:0]_CFG2
RZ2[3:0]_CFG2
0x3F
00
CZ2_CFG3
IP2[2:0]_CFG3
0x40
00
Reserved
D2[6:0]_CFG0
0x41
00
Reserved
D2[6:0]_CFG1
0x42
00
Reserved
D2[6:0]_CFG2
0x43
00
Reserved
D2[6:0]_CFG3
0x44
00
Reserved
D2[6:0]_CFG4
0x45
00
Reserved
0x46
01
N2[7:0]_CFG4
0x47
01
N2[7:0]_CFG5
0x48
01
N2[7:0]_CFG0
0x49
01
N2[7:0]_CFG1
0x4A
01
N2[7:0]_CFG2
0x4B
01
0x4C
80
SSENB_CFG0
0
0
IP3[4]_CFG0
N2[11:8]_CFG0
0x4D
80
SSENB_CFG1
0
0
IP3[4]_CFG1
N2[11:8]_CFG1
0x4E
80
SSENB_CFG2
0
0
IP3[4]_CFG2
N2[11:8]_CFG2
0x4F
80
SSENB_CFG3
0
0
IP3[4]_CFG3
N2[11:8]_CFG3
0x50
80
SSENB_CFG4
0
0
IP3[4]_CFG4
N2[11:8]_CFG4
0x51
80
SSENB_CFG5
0
0
IP3[4]_CFG5
N2[11:8]_CFG5
0x52
XX1
Reserved
0x53
XX1
Reserved
0x54
XX1
Reserved
0x55
XX1
Reserved
Description
0
PLL1 input divider and input sel
D1[6:0] - 127 step Ref Div
D1 = 0 means power down.
D1[6:0]_CFG5
N - Feedback Divider
2 - 4095 (value of “0” is not allowed)
Total feedback with A, using
provided calculation
N1[7:0]_CFG3
PLL3 Feedback Divider
N1[11:8]_CFG5
PLL2 Loop Parameter
RZ2[3:0]_CFG3
PLL2 Reference Divide and Input
Select
D2[6:0] - 127 step Ref Div
D2 = 0 means power down.
D2[6:0]_CFG5
N2[7:0] - PLL2 Feedback Divider
2 - 4095 (value of “0” is not
allowed).
(See Addr 0x4C:0x51 for N2[15:8])
N2[7:0]_CFG3
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
25
N2[11:8] - PLL2 Feedback Divide
PLL3 Spread Spectrum
SSENB - Spread Spectrum Enable
SSENB = 1 means ON
IP3[4:0] - PLL3 Charge Pump
Current.
5V49EE502
JUNE 18, 2018
5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
Default
Register
Addr
Hex
Value
Bit #
7
6
5
4
3
2
1
0x56
00
IP3[3:0]_CFG4
RZ3[3:0]_CFG4
0x57
00
IP3[3:0]_CFG5
RZ3[3:0]_CFG5
0x58
00
IP3[3:0]_CFG0
RZ3[3:0]_CFG0
0x59
00
IP3[3:0]_CFG1
RZ3[3:0]_CFG1
0x5A
00
IP3[3:0]_CFG2
RZ3[3:0]_CFG2
0x5B
00
IP3[3:0]_CFG3
0x5C
03
Reserved
D3[6:0]_CFG0
0x5D
03
Reserved
D3[6:0]_CFG1
0x5E
03
Reserved
D3[6:0]_CFG2
0x5F
03
Reserved
D3[6:0]_CFG3
0x60
03
Reserved
D3[6:0]_CFG4
0x61
03
Reserved
0x62
0C
N3[7:0]_CFG4
0x63
0C
N3[7:0]_CFG5
0x64
0C
N3[7:0]_CFG0
0x65
0C
N3[7:0]_CFG1
0x66
0C
N3[7:0]_CFG2
0x67
0C
N3[7:0]_CFG3
0x68
00
SSVCO[7:0]_CFG0
0x69
00
SSVCO[7:0]_CFG1
0x6A
00
SSVCO[7:0]_CFG2
0x6B
00
SSVCO[7:0]_CFG3
0x6C
00
SSVCO[7:0]_CFG4
0x6D
00
SSVCO[7:0]_CFG5
0x6E
00
SS_D3[7:0]_CFG4
0x6F
00
SS_D3[7:0]_CFG5
0x70
00
SS_D3[7:0]_CFG0
0x71
00
SS_D3[7:0]_CFG1
0x72
00
SS_D3[7:0]_CFG2
0x73
00
SS_D3[7:0]_CFG3
0x74
01
0x75
03
OEM0[1:0]
SLEW0[1:0]
0x76
00
OEM1[1:0]
SLEW1[1:0]
0x77
00
Description
0
PLL3 Loop Parameter
RZ3[3:0]_CFG3
PLL3 Reference Divide and input
sel
D3[6:0] - 127 step Ref Div
D3 = 0 means power down.
D3[6:0]_CFG5
N - Feedback Divider
12 - 4095 (values of “0” through “11”
are not allowed)
SSVCO[7:0] - PLL3 Spread
Spectrum Loop Feedback Counter
See Addr 0x80:0x85 for
SSVCO[15:8]
SS_D[7:0] - PLL3 Spread Spectrum
Reference Divide
Reserved
Reserved
INV0
S1
INV1[1:0]
SLEW2[1:0]
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
Reserved
LVL1[1:0]
CMEN3
26
Output Controls
S1=1 - OUT1/OUT2 are from
DIV1/DIV2 respectively
S1=0 - Both from DIV2
S3 =1 - OUT3/OUT6 are from
DIV3/DIV6
S3=0 - Both from DIV6
SLEW# - LVTTL only
OEM#–output enable mode
x0 - tristated
01 - park low
11 - park high
OEM0 controls OUT0 only
S3
Output Controls
LVL1[1:0] - output pair OUT1/OUT2
[00] - LVTTL
[01] - LVDS
[10] - LVPECL
[11] - HCSL
INV1 [CLK1, CLK2]
[0] - normal
[1] - invert clock
OEM1 controls OIT1/OUT2
CMEN1
CMEN# - common mode enable
Set to 1 for LVDS
Set to 0 for LVTTL, LVPECL, HCSL
5V49EE502
JUNE 18, 2018
5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
Default
Register
Addr
Hex
Value
Bit #
7
6
OEM3[1:0]
5
4
3
SLEW3[1:0]
2
1
INV3[1:0]
Description
0
LVL3[1:0]
0x78
00
0x79
00
Reserved
0x7A
00
Reserved
0x7B
00
0x7C
XX1
Reserved
Reserved
0x7D
XX1
Reserved
Reserved
0x7E
XX1
Reserved
Reserved
0x7F
XX1
Reserved
Reserved
0x80
00
SSVCO[15:8]_CFG0
0x81
00
SSVCO[15:8]_CFG1
0x82
00
SSVCO[15:8]_CFG2
0x83
00
SSVCO[15:8]_CFG3
0x84
00
SSVCO[15:8]_CFG4
0x85
00
SSVCO[15:8]_CFG5
0x86
00
Reserved
Reserved
0x87
00
Reserved
Reserved
0x88
FF
PM1_CFG0
Q1[6:0]_CFG0
0x89
FF
PM1_CFG1
Q1[6:0]_CFG1
0x8A
FF
PM1_CFG2
Q1[6:0]_CFG2
0x8B
FF
PM1_CFG3
Q1[6:0]_CFG3
0x8C
FF
PM1_CFG4
Q1[6:0]_CFG4
0x8D
FF
PM1_CFG5
Q1[6:0]_CFG5
0x8E
7F
PM2_CFG4
Q2[6:0]_CFG4
0x8F
7F
PM2_CFG5
Q2[6:0]_CFG5
0x90
7F
PM2_CFG0
Q2[6:0]_CFG0
0x91
7F
PM2_CFG1
Q2[6:0]_CFG1
0x92
7F
PM2_CFG2
Q2[6:0]_CFG2
0x93
7F
PM2_CFG3
Q2[6:0]_CFG3
0x94
7F
PM3_CFG0
Q3[6:0]_CFG0
0x95
7F
PM3_CFG1
Q3[6:0]_CFG1
0x96
7F
PM3_CFG2
Q3[6:0]_CFG2
0x97
7F
PM3_CFG3
Q3[6:0]_CFG3
0x98
7F
PM3_CFG4
Q3[6:0]_CFG4
0x99
7F
PM3_CFG5
Q3[6:0]_CFG5
0x9A
7F
PM4_CFG4
Q4[6:0]_CFG4
0x9B
7F
PM4_CFG5
Q4[6:0]_CFG5
0x9C
7F
PM4_CFG0
Q4[6:0]_CFG0
0x9D
7F
PM4_CFG1
Q4[6:0]_CFG1
0x9E
7F
PM4_CFG2
Q4[6:0]_CFG2
0x9F
7F
PM4_CFG3
Q4[6:0]_CFG3
0xA0
7F
PM5_CFG0
Q5[6:0]_CFG0
0xA1
7F
PM5_CFG1
Q5[6:0]_CFG1
0xA2
7F
PM5_CFG2
Q5[6:0]_CFG2
0xA3
7F
PM5_CFG3
Q5[6:0]_CFG3
0xA4
7F
PM5_CFG4
Q5[6:0]_CFG4
0xA5
7F
PM5_CFG5
Q5[6:0]_CFG5
0xA6
7F
PM6_CFG4
Q6[6:0]_CFG4
Reserved
Reserved
SLEW6[1:0]
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
OEM3 controls OUT3 and OUT6
CMEN5
27
CMEN4
PLL3 Spread Spectrum Feedback
Counter
Output Divides
for Q111111,
PM=0 - Divide by 2
PM=1, (Q+2)*2
for Q=1111111
PM=0, disable the output divider
PM=1, bypass the output divide,
(divide by 1)
5V49EE502
JUNE 18, 2018
5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
Default
Register
Addr
Hex
Value
Bit #
7
6
5
4
3
2
1
Description
0
0xA7
7F
PM6_CFG5
Q6[6:0]_CFG5
0xA8
7F
PM6_CFG0
Q6[6:0]_CFG0
0xA9
7F
PM6_CFG1
Q6[6:0]_CFG1
0xAA
7F
PM6_CFG2
Q6[6:0]_CFG2
0xAB
7F
PM6_CFG3
0xAC
00
TSSC[3:0]_CFG0
NSSC[3:0]_CFG0
0xAD
00
TSSC[3:0]_CFG1
NSSC[3:0]_CFG1
0xAE
00
TSSC[3:0]_CFG2
NSSC[3:0]_CFG2
0xAF
00
TSSC[3:0]_CFG3
NSSC[3:0]_CFG3
0xB0
00
TSSC[3:0]_CFG4
NSSC[3:0]_CFG4
0xB1
00
TSSC[3:0]_CFG5
0xB2
00
DITH_CFG4
X2_CFG4
SSOFFSET[5:0]_CFG4
0xB3
00
DITH_CFG5
X2_CFG5
SSOFFSET[5:0]_CFG5
0xB4
00
DITH_CFG0
X2_CFG0
SSOFFSET[5:0]_CFG0
0xB5
00
DITH_CFG1
X2_CFG1
SSOFFSET[5:0]_CFG1
0xB6
00
DITH_CFG2
X2_CFG2
SSOFFSET[5:0]_CFG2
0xB7
00
DITH_CFG3
X2_CFG3
SSOFFSET[5:0]_CFG3
0xB8
11
SD1[3:0]_CFG0
SD0[3:0]_CFG0
0xB9
11
SD1[3:0]_CFG1
SD0[3:0]_CFG1
0xBA
11
SD1[3:0]_CFG2
SD0[3:0]_CFG2
0xBB
11
SD1[3:0]_CFG3
SD0[3:0]_CFG3
0xBC
11
SD1[3:0]_CFG4
SD0[3:0]_CFG4
0xBD
11
SD1[3:0]_CFG5
0xBE
AE
SRC1[1:0]_CFG4
SRC0[1:0]_CFG4
PDPL3_CFG4
SM[1:0]_CFG4
PRIMSRC_CFG4 Output Divide Source Selection
0xBF
AE
SRC1[1:0]_CFG5
SRC0[1:0]_CFG5
PDPL3_CFG5
SM[1:0]_CFG5
PRIMSRC_CFG5 PRIMSRC - primary source - crystal
Q6[6:0]_CFG3
PLL0 Spread Spectrum Control
NSSC[3:0]_CFG5
SD0[3:0]_CFG5
or ICLOCK
0 = crystal/REFIN
1 = CLKIN
0xC0
AE
SRC1[1:0]_CFG0
SRC0[1:0]_CFG0
PDPL3_CFG0
SM[1:0]_CFG0
PRIMSRC_CFG0 SM = switch mode
0x = manual
10 = reserved
11 = auto-revertive
0xC1
AE
SRC1[1:0]_CFG1
SRC0[1:0]_CFG1
PDPL3_CFG1
SM[1:0]_CFG1
PRIMSRC_CFG1 PDPL3 - PLL3 shutdown
0 = normal
1 = shut down
0xC2
AE
SRC1[1:0]_CFG2
SRC0[1:0]_CFG2
PDPL3_CFG2
SM[1:0]_CFG2
PRIMSRC_CFG2 SRC = MUX control bit prior to DIV#
SRC0[1:0]
00 - DIV1
01 - DIV3
10 - Reference input
0xC3
AE
0xC4
24
SRC4[0]_CFG
0
SRC3[2:0]_CFG0
SRC2[2:0]_CFG0
SRC1[2]_CFG0 SRC1/SRC2/SRC3.SRC5
0xC5
24
SRC4[0]_CFG
1
SRC3[2:0]_CFG1
SRC2[2:0]_CFG1
SRC1[2]_CFG1 001 - DIV3
0xC6
24
SRC4[0]_CFG
2
SRC3[2:0]_CFG2
SRC2[2:0]_CFG2
SRC1[2]_CFG2
0xC7
24
SRC4[0]_CFG
3
SRC3[2:0]_CFG3
SRC2[2:0]_CFG3
0xC8
24
SRC4[0]_CFG
4
SRC3[2:0]_CFG4
SRC2[2:0]_CFG4
SRC1[2]_CFG4
0xC9
24
SRC4[0]_CFG
5
SRC3[2:0]_CFG5
SRC2[2:0]_CFG5
SRC1[2]_CFG5
SRC1[1:0]_CFG3
SRC0[1:0]_CFG3
PDPL3_CFG3
SM[1:0]_CFG3
PRIMSRC_CFG3
000 - DIV1
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
28
010 - Reference input
011 - Reserved
100 - PLL0
101 - PLL1
SRC1[2]_CFG3 110 - PLL2
111 - PLL3
5V49EE502
JUNE 18, 2018
5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
Default
Register
Addr
Hex
Value
Bit #
7
6
5
4
3
2
1
Description
0
0xCA
49
SRC6[2:0]_CFG4
SRC5[2:0]_CFG4
SRC4[2:1]_CFG4
0xCB
49
SRC6[2:0]_CFG5
SRC5[2:0]_CFG5
SRC4[2:1]_CFG5
0xCC
49
SRC6[2:0]_CFG0
SRC5[2:0]_CFG0
SRC4[2:1]_CFG0
0xCD
49
SRC6[2:0]_CFG1
SRC5[2:0]_CFG1
SRC4[2:1]_CFG1
0xCE
49
SRC6[2:0]_CFG2
SRC5[2:0]_CFG2
SRC4[2:1]_CFG2
0xCF
49
SRC6[2:0]_CFG3
SRC5[2:0]_CFG3
SRC4[2:1]_CFG3
SRC6
000 - Reserved
001 - Reserved
010 - Reference input
011 - Reserved
100 - Reserved
101 - PLL1
110 - Reserved
111 - Reserved
Quiet MUX
Default Configuration: OUT1 = Reference Clock output, all other outputs turned off.
1
. Memory bytes do not exist. Readback will be last value in shift register. If reading sequentially, value in 0x51 will be
returned.
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
29
5V49EE502
JUNE 18, 2018
5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
Marking Diagram
4502LI
#YYWW$
Notes:
1. “#” is the lot number.
2. YYWW is the last two digits of the year and week that the part was assembled.
3. “$” is the assembly mark code.
4. “I” indicates industrial temperature range.
Thermal Characteristics for 24-QFN
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Thermal Resistance Junction to
Ambient
JA
Still air
47.6
C/W
JA
1 m/s air flow
42.4
C/W
JA
2.5 m/s air flow
39.9
C/W
Thermal Resistance Junction to Case
JC
60.7
C/W
Package Outline Drawings
The package outline drawings are appended at the end of this document and are accessible from the link below. The
package information is the most current data available.
www.idt.com/document/psc/nlnlg24p1-package-outline-40-x-40-mm-body-05-mm-pitch-qfn-epad-size-245-x-245-mm
Ordering Information
Part / Order Number
Shipping Packaging
Package
Temperature
5V49EE502NLGI
5V49EE502NLGI8
Tray
Reel
4 × 4 mm 24-QFN
4 × 4 mm 24-QFN
-40 to +85 C
-40 to +85 C
“G” after the two-letter package code denote Pb-Free configuration, RoHS compliant.
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
30
5V49EE502
JUNE 18, 2018
5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
Revision History
Date
September 24, 2012
July 10. 2015
Description of Change
Change differential outputs from 5pF loads to 2pF loads so that they are consistent with the industry.
Capacitive loads were also added to the test circuit diagrams for HCSL outputs. Slew Rate (t4) Output Load
test conditions were changed from 15pF to 5pF.
Added the following note under AC Timing Electrical Characteristics table:
“Not guaranteed until customer specific configuration is approved by IDT.”
August 3, 2016
Changed 5V49EE502NLGI shipping packaging from tray to tube.
June 18, 2018
1. Changed shipping packaging from tube to tray.
2. Updated package outline drawings.
3. Updated legal disclaimer.
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
31
5V49EE502
JUNE 18, 2018
5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
www.IDT.com
Sales
Tech Support
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
www.IDT.com/go/support
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
www.idt.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products
and/or specifications described herein at any time, without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the
described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The
information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of
others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where
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in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other
countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of
common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved.
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
32
5V49EE502
JUNE 18, 2018
24-VFQFPN, Package Outline Drawing
4.0 x 4.0 x 0.90 mm Body,0.50mm Pitch,Epad 2.45 x 2.45 mm
NLG24P1, PSC-4192-01, Rev 02, Page 1
© Integrated Device Technology, Inc.
24-VFQFPN, Package Outline Drawing
4.0 x 4.0 x 0.90 mm Body,0.50mm Pitch,Epad 2.45 x 2.45 mm
NLG24P1, PSC-4192-01, Rev 02, Page 2
Package Revision History
© Integrated Device Technology, Inc.
Description
Date Created
Rev No.
Sept 9, 2016
Rev 01
Sept 13, 2018
Rev 02 New Format, Recalculate Land Pattern Change QFN to VFQFPN
Add Chamfer on Epad
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