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5V50015PGG8

5V50015PGG8

  • 厂商:

    RENESAS(瑞萨)

  • 封装:

    TSSOP-8

  • 描述:

    IC CLK GENERATOR LOW EMI 8TSSOP

  • 数据手册
  • 价格&库存
5V50015PGG8 数据手册
DATASHEET IDT5V50015 LOW EMI CLOCK GENERATOR Description Features The IDT5V50015 generates a low EMI output clock from a clock or crystal input. The part is designed to dither the LCD interface clock for PDAs, printers, scanners, modems, copiers, and others. Using IDT’s proprietary mix of analog and digital Phase-Locked Loop (PLL) technology, the device spreads the frequency spectrum of the output, reducing the frequency amplitude peaks by several dB. • • • • Packaged in 8-pin SOIC/TSSOP Provides a spread spectrum output clock 135 MHz to 200 MHz operation Accepts a clock input (provides same frequency dithered output) • Center spread modulation • Peak reduction by 8 dB to 16 dB typical on 3rd through IDT offers many other clocks for computers and computer peripherals. Consult IDT when you need to remove crystals and oscillators from your board. 19th odd harmonics • Low EMI feature can be disabled • Operating voltage of 3.3 V • Advanced, low-power CMOS process Block Diagram VDD S1:0 SSCC 2 PLL Clock Synthesis and Spread Spectrum Circuitry SSCLK ICLK GND IDT™ LOW EMI CLOCK GENERATOR 1 IDT5V50015 REV F 031109 IDT5V50015 LOW EMI CLOCK GENERATOR SSCG Pin Assignment Spread Direction and Percentage Select Table ICLK 1 8 VDD VDD 2 7 S0 GND 3 6 S1 SSCLK 4 5 SSCC 8 pin (150 mil) SOIC/TSSOP S1 Pin 6 S0 Pin 7 Spread Direction Spread Percentage 0 0 1 1 0 1 0 1 Center Center Center Center ±0.5 ±1.0 ±1.5 ±2.0 0 = connect to GND 1 = connect directly to VDD Pin Descriptions Pin Number Pin Name Pin Type 1 ICLK Input Connect to a 130–200 MHz clock input. 2 VDD Power Connect to +3.3 V. 3 GND Power Connect to ground. 4 SSCLK Output Clock output with spread spectrum. 5 SSCC Input Spread spectrum enable/disable function. SSCC function is enabled when input is high and disabled when input is low. This pin is pulled high internally. 6 S1 Input Function select 1 input. Selects spread amount and direction per table above. Internal pull-down. 7 S0 Input Function select 0 input. Selects spread amount and direction per table above. Internal pull-down. 8 VDD Power Connect to +3.3 V. IDT™ LOW EMI CLOCK GENERATOR Pin Description 2 IDT5V50015 REV F 031109 IDT5V50015 LOW EMI CLOCK GENERATOR SSCG External Components Spread Spectrum Profile The IDT5V50015 low EMI clock generator uses an optimized frequency slew rate algorithm to facilitate down stream tracking of zero delay buffers and other PLL devices. The frequency modulation amplitude is constant with variations of the input frequency. The IDT5V50015 requires a minimum number of external components for proper operation. Decoupling Capacitor A decoupling capacitor of 0.01µF must be connected between VDD and GND on pins 2 and 3, as close to these pins as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit. Frequency Modulation Rate Series Termination Resistor When the PCB trace between the clock output and the load is over 1 inch, series termination should be used. To series terminate a 50Ω trace (a commonly used trace impedance) place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. Time PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) The 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. 2) To minimize EMI, the 33Ω series termination resistor (if needed) should be placed close to the clock output. 3) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the IDT5V50015. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. IDT™ LOW EMI CLOCK GENERATOR 3 IDT5V50015 REV F 031109 IDT5V50015 LOW EMI CLOCK GENERATOR SSCG Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the IDT5V50015. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature 0 to +70° C Storage Temperature -65 to +150° C Junction Temperature 125° C Soldering Temperature 260° C Recommended Operation Conditions Parameter Min. Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Typ. Max. Units 0 +70 °C +3.0 3.6 V Thermal Characteristics for 8TSSOP Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Symbol Conditions Min. Typ. Max. Units θJA Still air 110 ° C/W θJA 1 m/s air flow 100 ° C/W θJA 3 m/s air flow 80 ° C/W 35 ° C/W θJC Thermal Characteristics for 8SOIC Parameter Thermal Resistance Junction to Ambient Symbol Min. Typ. Max. Units θJA Still air 150 ° C/W θJA 1 m/s air flow 140 ° C/W θJA 3 m/s air flow 120 ° C/W 40 ° C/W 20 ° C/W Thermal Resistance Junction to Case θJC Thermal Resistance Junction to Top of Case ΨJT IDT™ LOW EMI CLOCK GENERATOR Conditions Still air 4 IDT5V50015 REV F 031109 IDT5V50015 LOW EMI CLOCK GENERATOR SSCG DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V, Ambient Temperature 0 to +70° C Parameter Symbol Operating Voltage VDD Supply Current IDD Conditions Min. Typ. Max. Units 3.0 3.3 3.6 V ICLK=150 MHz, Note 1 40 mA ICLK=200 MHz, Note 1 50 mA Input High Voltage VIH S1: S0 Input Low Voltage VIL S1: S0 Output High Voltage VOH IOH = -6 mA 2.4 V IOH =- 20 mA 2.0 V Output Low Voltage VOL 2.0 V 0.8 V IOL = 6 mA 0.4 V IOL = 20 mA 1.2 V 5 pF Input Capacitance CIN1 All inputs Pull-down Resistance RPD S1, S0 240 kΩ Pull-up Resistance RPU SSCC 240 kΩ 3 4 Note 1: CL = 15 pF. AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V, Ambient Temperature 0 to +70° C Parameter Symbol Conditions Min. Typ. Max. Units Input Clock Frequency 135 200 MHz Output Clock Frequency 135 200 MHz 50 53 % Output Clock Duty Cycle All outputs 47 Cycle to cycle Jitter ICLK=150 MHz, SS on 50 100 ps ICLK=200 MHz, SS on 75 100 ps Output Rise Time tR 20% to 80%, CL=15 pF, 150 MHz 0.9 ns Output Fall Time tF 80% to 20%, CL=15 pF, 150 MHz 0.9 ns ICLK=200 MHz 51.2 kHz ICLK=150 MHz 38.4 ICLK=130 MHz 32 Modulation Frequency IDT™ LOW EMI CLOCK GENERATOR 5 IDT5V50015 REV F 031109 IDT5V50015 LOW EMI CLOCK GENERATOR SSCG Package Outline and Package Dimensions (8-pin TSSOP) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 8 Symbol E1 A A1 A2 b C D E E1 e L α aaa E IN D E X AREA 1 2 D A 2 Min Max -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 2.90 3.10 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0° 8° 0.10 Inches Min Max -0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.114 0.122 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0° 8° 0.004 A A 1 c -C e b S E A T IN G P LA N E L aaa IDT™ LOW EMI CLOCK GENERATOR C 6 IDT5V50015 REV F 031109 IDT5V50015 LOW EMI CLOCK GENERATOR SSCG Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 8 Symbol E Min A A1 B C D E e H h L α H INDEX AREA 1 2 D A Inches Max Min 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0° 8° Max .0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .1890 .1968 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0° 8° h x 45 A1 C -Ce B SEATING PLANE L .10 (.004) C Ordering Information Part / Order Number Marking Shipping Packaging Package 5V50015PGG 5V50015PGG8 5V50015DCG 5V50015DCG8 TBD Tubes Tape and Reel Tubes Tape and Reel 8-pin TSSOP 8-pin TSSOP 8-pin SOIC 8-pin SOIC Temperature 0 to +70° 0 to +70° 0 to +70° 0 to +70° C C C C Parts that are ordered with a "G" after the two-letter package code are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ LOW EMI CLOCK GENERATOR 7 IDT5V50015 REV F 031109 IDT5V50015 LOW EMI CLOCK GENERATOR SSCG Revision History Rev. Originator Date Description of Change E 01/28/09 Release to final. F 03/11/09 Changed minimum input frequency from 130 to 135 MHz. IDT™ LOW EMI CLOCK GENERATOR 8 IDT5V50015 REV F 031109 IDT5V50015 LOW EMI CLOCK GENERATOR SSCG Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. © 2020 Renesas Electronics Corporation. All rights reserved.
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