7027S/L
HIGH-SPEED
32K x 16 DUAL-PORT
STATIC RAM
Features
◆
◆
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 15/25/35/55ns (max.)
– Industrial: 20ns (max.)
Low-power operation
– IDT7027S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7027L
Active: 750mW (typ.)
Standby: 1mW (typ.)
Separate upper-byte and lower-byte control for bus
matching capability.
Dual chip enables allow for depth expansion without
external logic
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
IDT7027 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in 100-pin Thin Quad Flatpack (TQFP) and 108-pin
Ceramic Pin Grid Array (PGA)
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
R/WL
UBL
R/WR
UBR
CE0L
CE1L
CE0R
CE1R
OEL
OER
LBL
LBR
I/O8-15R
I/O 8-15L
I/O
Control
I/O 0-7L
I/O
Control
I/O0-7R
(1,2)
BUSYR
BUSY L
A14L
Address
Decoder
A0L
32Kx16
MEMORY
ARRAY
7027
A14L
A0L
CE0L
CE1L
OEL
R/WL
A14R
A0R
A14R
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEML
INT L
Address
Decoder
.
(2)
M/S
NOTES:
1. BUSY is an input as a Slave (M/S=VIL) and an output as a Master (M/S=VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
(2)
A0R
CE0R
CE1R
OER
R/WR
SEMR
(2)
INTR
3199 drw 01
JUNE 2019
1
DSC 3199/12
7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Description
Industrial and Commercial Temperature Ranges
The IDT7027 is a high-speed 32K x 16 Dual-Port Static RAM,
designed to be used as a stand-alone 512K-bit Dual-Port RAM or as a
combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more word
systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32bit or wider memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
The device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (CE0 and CE1) permits the on-chip
circuitry of each port to enter a very low standby power mode.
Fabricated using CMOS high-performance technology, these devices typically operate on only 750mW of power. The IDT7027 is
packaged in a 100-pin Thin Quad Flatpack (TQFP) and a 108-pin ceramic
Pin Grid Array (PGA).
A9R
A10R
A11R
A12R
A13R
A14R
NC
NC
NC
LBR
UBR
CE0R
CE1R
SEMR
GND
R/WR
OER
GND
GND
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
Pin Configurations(1,2,3)
A8R
A7R
A6R
A5R
A4R
A3R
A2R
A1R
A0R
INTR
BUSYR
M/S
GND
BUSYL
INTL
NC
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76
50
49
77
48
78
79
47
80
46
45
44
81
82
83
84
43
42
41
85
86
87
88
89
90
91
7027
PNG100(4)
100-Pin
TQFP
Top View
40
39
38
37
36
92
35
34
93
33
94
32
31
95
96
30
97
29
98
28
27
26
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
99
NC
I/O9R
I/O8R
I/O7R
Vcc
I/O6R
I/O5R
I/O4R
I/O3R
I/O2R
I/O1R
I/O0R
GND
I/O0L
I/O1L
GND
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
Vcc
I/O8L
I/O9L
A9L
A10L
A11L
A12L
A13L
A14L
NC
NC
NC
LBL
UBL
CE0L
CE1L
SEML
Vcc
R/WL
OEL
GND
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
3199 drw 02
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
.
2
6.42
7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
81
12
84
11
83
86
90
09
107
02
108
01
103
59
105
62
OER
58
55
2
3
46
35
1
4
8
12
NC
A13L
7
A14L
10
NC
13
UBL
11
9
17
CE1L
21
GND
16
SEML
14
25
34
28
19
OEL
22
32
24
15
18
20
A9L
A12L
NC
LBL
CE0L
Vcc
R/WL
NC
29
A
B
C
D
E
F
G
H
23
26
K
I/O6L
30
NC
I/O8L
27
I/O15L I/O12L I/O9L
J
I/O3L
33
I/O7L
GND I/O13L I/O11L
GND
36
I/O5L
NC
I/O14L I/O10L
GND
38
I/O2L
Vcc
A10L
6
37
31
A7L
I/O0R
41
I/O0L
I/O4L
I/O3R
42
40
I/O1L
I/O5R
45
I/O4R
43
39
108-Pin PGA
Top View(5)
I/O7R
47
Vcc
I/O2R I/O1R
106
5
A11L
49
44
IDT7027G
GU108(4)
NC
50
I/O8R
I/O6R
NC
53
51
NC
I/O15R I/O11R
A3L
A6L
56
48
102
A4L
A8L
61
NC
NC
A1L
A5L
66
CE0R
54
GND I/O14R I/O12R I/O9R
52
98
100
A2L
64
57
I/O13R I/O10R
93
97
104
03
71
NC
M/S BUSYR
A0L
67
CE1R R/WR
60
NC
A2R
BUSYL INTL
101
04
75
A12R
63
GND
89
94
99
05
79
70
LBR
65
A6R
A0R
GND
96
06
73
68
SEMR GND
85
91
95
07
69
UBR
NC
A9R
A3R
INTR
76
82
88
72
NC
A13R
A5R
A1R
92
08
78
A8R
A4R
74
A14R
A11R
A7R
87
10
77
80
A10R
L
NC
M
3199
drw 03
INDEX
Pin Names
Left Port
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.21 in x 1.21 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Right Port
Names
CE0L, CE1L
CE0R, CE1R
Chip Enables
R/WL
R/WR
Read/Write Enable
OEL
OER
Output Enable
A0L - A14L
A0R - A14R
Address
I/O0L - I/O15L
I/O0R - I/O15R
Data Input/Output
SEML
SEMR
Semaphore Enable
UBL
UBR
Upper Byte Select
LBL
LBR
Lower Byte Select
INTL
INTR
Interrupt Flag
BUSYL
BUSYR
Busy Flag
M/S
Master or Slave Select
VCC
Power
GND
Ground
3199 tbl 01
3
6.42
7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I – Chip Enable
CE0
CE1
Mode
VIL
VIH
Port Selected (TTL Active)
< 0.2V
>VCC - 0.2V
Port Selected (CMOS Active)
VIH
X
Port Deselected (TTL Inactive)
X
VIL
Port Deselected (TTL Inactive)
>VCC - 0.2V
X
Port Deselected (CMOS Inactive)
X
Vcc
+ 10%.
Capacitance(1)
(TA = +25°C, f = 1.0mhz) TQFP ONLY
Symbol
Parameter
VCC
Supply Voltage
GND
Ground
VIH
Input High Voltage
(2)
COUT
VIL
Input Low Voltage
Typ.
Max.
Unit
5.0
5.5
V
0
0
0
V
____
6.0(2)
V
____
0.8
-0.5
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
Max.
Unit
VIN = 0V
9
pF
VOUT = 0V
10
pF
NOTES:
1. This parameter is determined by device characterization but is not production tested.
2. COUT also references CI/O.
4.5
(1)
Output
Capacitance
Conditions
3199 tbl 08
Min.
2.2
Input Capacitance
CIN
Recommended DC Operating
Conditions
Symbol
Parameter
V
3199 tbl 07
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
7027S
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
VCC = 5.5V, VIN = 0V to V CC
___
10
___
5
µA
Output Leakage Current
CE = VIH, VOUT = 0V to V CC
___
10
___
5
µA
VOL
Output Low Voltage
IOL = 4mA
___
0.4
___
0.4
V
VOH
Output High Voltage
IOH = -4mA
2.4
___
2.4
___
|ILI|
(1)
Input Leakage Current
|ILO|
Test Conditions
7027L
V
3199 tbl 09
NOTE:
1. At Vcc < 2.0V, input leakages are undefined.
5
6.42
7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,6) (VCC = 5.0V ± 10%)
7027X15
Com'l Only
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL Level
Inputs)
Standby Current
(One Port - TTL Level
Inputs)
Full Standby Current
(Both Ports - All CMOS
Level Inputs)
Full Standby Current
(One Port - All CMOS
Level Inputs)
Test Condition
Version
7027X20
Com'l
& Ind
7027X25
Com'l
& Ind
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Unit
190
180
325
285
180
170
305
265
mA
170
345
COM'L
S
L
205
200
365
325
IND
S
L
___
___
___
___
___
___
180
335
COM'L
S
L
65
65
110
90
50
50
90
70
40
40
85
60
IND
S
L
___
___
___
___
___
___
50
85
40
100
CE"A" = V IL and CE"B" = VIH(5)
Active Port Outputs Disabled,
f=fMAX(3)
SEMR = SEML = VIH
COM'L
S
L
130
130
245
215
115
115
215
185
105
105
200
170
IND
S
L
___
___
___
___
___
___
115
220
105
230
Both Ports CEL and
CER > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
SEMR = SEML > VCC - 0.2V
COM'L
S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
IND
S
L
___
___
___
___
___
___
0.2
10
1.0
30
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
SEMR = SEML > VCC - 0.2V
VIN > VCC - 0.2V or V IN < 0.2V
Active Port Outputs Disabled
f = fMAX(3)
COM'L
S
L
120
120
220
190
110
110
190
160
100
100
170
145
IND
S
L
___
___
___
___
___
___
110
195
100
200
CE = V IL, Outputs Disabled
SEM = VIH
f = fMAX(3)
CEL = CER = VIH
SEMR = SEML = VIH
f = fMAX(3)
___
___
___
___
___
___
mA
___
mA
___
mA
___
mA
___
3199 tbl 10a
7027X35
Com'l Only
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Dynamic Operating Current
(Both Ports Active)
Standby Current
(Both Ports - TTL Level
Inputs)
Standby Current
(One Port - TTL Level
Inputs)
Full Standby Current
(Both Ports - All CMOS
Level Inputs)
Full Standby Current
(One Port - All CMOS
Level Inputs)
Test Condition
Version
7027X55
Com'l Only
Typ. (2)
Max.
Typ.(2)
Max.
Unit
mA
COM'L
S
L
160
160
295
255
150
150
270
230
IND
S
L
___
___
___
___
___
___
___
___
COM'L
S
L
30
30
85
60
20
20
85
60
IND
S
L
___
___
___
___
___
___
___
___
CE"A" = VIL and CE"B" = VIH(5)
Active Port Outputs Disabled,
f=fMAX(3)
SEMR = SEML = VIH
COM'L
S
L
95
95
185
155
85
85
165
135
IND
S
L
___
___
___
___
___
___
___
___
Both Ports CEL and
CER > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
SEMR = SEML > VCC - 0.2V
COM'L
S
L
1.0
0.2
15
5
1.0
0.2
15
5
IND
S
L
___
___
___
___
___
___
___
___
COM'L
S
L
90
90
160
135
80
80
135
110
IND
S
L
___
___
___
___
___
___
___
___
CE = VIL, Outputs Disabled
SEM = VIH
f = fMAX(3)
CEL = CER = VIH
SEMR = SEML = VIH
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
SEMR = SEML > VCC - 0.2V
VIN > VCC - 0.2V or V IN < 0.2V
Active Port Outputs Disabled
f = fMAX(3)
mA
mA
mA
mA
3199 tbl 10b
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
2. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions” of input
levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6. Refer to Chip Enable Truth Table.
6
6.42
7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions
dInput Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns Max.
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
Figures 1 and 2
3199 tbl 11
5V
5V
893Ω
DATAOUT
BUSY
INT
893Ω
DATAOUT
30pF
347Ω
5pF*
347Ω
3199 drw 04
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
*Including scope and jig.
Figure 1. AC Output Test Load
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Ranges(4)
7027X15
Com'l Only
Symbol
Parameter
7027X20
Com'l
& Ind
7027X25
Com'l
& Ind
7027X35
Com'l Only
7027X55
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
15
____
20
____
25
____
35
____
55
____
ns
tAA
Address Access Time
____
15
____
20
____
25
____
35
____
55
ns
tACE
Chip Enable Access Time (4)
____
15
____
20
____
25
____
35
____
55
ns
tAOE
Output Enable Access Time
____
10
____
12
____
13
____
20
____
30
ns
tOH
Output Hold from Address Change
ns
tLZ
Output Low-Z Time
3
____
3
____
3
____
3
____
3
____
(1,2)
3
____
3
____
3
____
3
____
3
____
ns
(1,2)
____
10
____
12
____
15
____
15
____
25
ns
0
____
0
____
0
____
0
____
0
____
ns
tHZ
Output High-Z Time
tPU
Chip Enable to Power Up Time (2,5)
tPD
Chip Disable to Power Down Time (2,5)
____
15
____
20
____
25
____
35
____
50
ns
tSOP
Semaphore Flag Update Pulse (OE or SEM)
10
____
10
____
12
____
15
____
15
____
ns
tSAA
Semaphore Address Access Time
____
15
____
20
____
25
____
35
____
55
ns
NOTES:.
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE= VIH and SEM = VIL.
4. 'X' in part numbers indicates power rating (S or L).
5. Refer to Chip Enable Truth Table.
7
6.42
3199 tbl 12
7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Read Cycles(5)
tRC
ADDR
(4)
tAA
(4)
tACE
(6)
CE
tAOE
(4)
OE
tABE (4)
UB, LB
R/W
tLZ
tOH
(1)
DATAOUT
VALID DATA
(4)
tHZ
(2)
BUSYOUT
tBDD
(3,4)
3199 drw 05
Timing of Power-Up Power-Down
CE (6)
ICC
tPU
tPD
50%
50%
ISB
3199 drw 06
.
NOTES:
1. Timing depends on which signal is asserted last, CE, OE, LB, or UB.
2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6. Refer to Chip Enable Truth Table.
8
6.42
7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(5)
7027X15
Com'l Only
7027X20
Com'l
& Ind
7027X25
Com'l
& Ind
7027X35
Com'l Only
7027X55
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
15
____
20
____
25
____
35
____
55
____
ns
tEW
Chip Enable to End-of-Write
(3)
12
____
15
____
20
____
30
____
45
____
ns
tAW
Address Valid to End-of-Write
12
____
15
____
20
____
30
____
45
____
ns
tAS
Address Set-up Time (3)
0
____
0
____
0
____
0
____
0
____
ns
tWP
Write Pulse Width
12
____
15
____
20
____
25
____
40
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
0
____
0
____
ns
tDW
Data Valid to End-of-Write
10
____
15
____
15
____
15
____
30
____
ns
____
10
____
12
____
15
____
15
____
25
ns
0
____
0
____
0
____
0
____
0
____
ns
(1,2)
____
10
____
12
____
15
____
15
____
25
ns
(1,2,5)
0
____
0
____
0
____
0
____
0
____
ns
Symbol
Parameter
WRITE CYCLE
tWC
Write Cycle Time
tHZ
Output High-Z Time
tDH
Data Hold Time (5)
tWZ
(1,2)
Write Enable to Output in High-Z
tOW
Output Active from End-of-Write
tSWRD
SEM Flag Write to Read Time
5
____
5
____
5
____
5
____
5
____
ns
tSPS
SEM Flag Contention Window
5
____
5
____
5
____
5
____
5
____
ns
3199 tbl 13
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. Refer to Chip Enable
Truth Table.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part numbers indicates power rating (S or L).
9
6.42
7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC
ADDRESS
tHZ
(7)
OE
tAW
(9,10)
CE or SEM
(9)
UB or LB
tAS (6)
tWP
(2)
tWR
(3)
R/W
tWZ (7)
tOW
(4)
DATAOUT
(4)
tDW
tDH
DATAIN
3199 drw 07
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)
tWC
ADDRESS
tAW
CE or SEM
(9,10)
(6)
tAS
tWR(3)
tEW (2)
UB or LB(9)
R/W
tDW
tDH
DATAIN
3199 drw 08
NOTES:
1. R/W or CE or UB and LB = VIH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure
2).
8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
10. Refer to Chip Enable Truth Table.
10
6.42
7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tOH
tSAA
VALID ADDRESS
A0-A2
tAW
VALID ADDRESS
tWR
tACE
tEW
SEM
tSOP
tDW
DATAIN
VALID
I/O0
tAS
tWP
DATAOUT
VALID(2)
tDH
R/W
tSWRD
tAOE
OE
Write Cycle
Read Cycle
3199 drw 09
NOTES:
1. CE = VIH or UB and LB = VIH for the duration of the above timing (both write and read cycle), refer to Chip Enable Truth Table.
2. "DATAOUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
(2)
SIDE
"A"
MATCH
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
(2)
SIDE
"B"
MATCH
R/W"B"
SEM"B"
3199 drw 10
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH (refer to Chip Enable Truth Table).
2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.
11
6.42
7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6)
7027X15
Com'l Only
Symbol
Parameter
7027X20
Com'l
& Ind
7027X25
Com'l
& Ind
7027X35
Com'l Only
7027X55
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S=VIH)
tBAA
BUSY Access Time from Address Match
____
15
____
20
____
20
____
20
____
45
ns
tBDA
BUSY Disable Time from Address Not Matched
____
15
____
20
____
20
____
20
____
40
ns
tBAC
BUSY Access Time from Chip Enable Low
____
15
____
20
____
20
____
20
____
40
ns
tBDC
BUSY Access Time from Chip Enable High
____
15
____
17
____
17
____
20
____
35
ns
tAPS
Arbitration Priority Set-up Time (2)
5
____
5
____
5
____
5
____
5
____
ns
____
15
____
20
____
25
____
35
____
55
ns
12
____
15
____
17
____
25
____
25
____
ns
tBDD
tWH
(3)
BUSY Disable to Valid Data
(5)
Write Hold After BUSY
BUSY TIMING (M/S=VIL)
tWB
BUSY Input to Write(4)
0
____
0
____
0
____
0
____
0
____
ns
tWH
Write Hold After BUSY(5)
12
____
15
____
17
____
25
____
25
____
ns
____
30
____
45
____
50
____
60
____
80
ns
____
25
____
30
____
35
____
45
____
65
ns
PORT-TO-PORT DELAY TIMING
tWDD
tDDD
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay
(1)
3199 tbl 14
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
12
6.42
7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)(2,4,5)
tWC
MATCH
ADDR"A"
tWP
R/W"A"
tDW
tDH
VALID
DATAIN "A"
tAPS
(1)
MATCH
ADDR"B"
tBAA
tBDA
tBDD
BUSY"B"
tWDD
DATAOUT "B"
VALID
tDDD
(3)
3199 drw 11
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).
2. CEL = CER = VIL (refer to Chip Enable Truth Table).
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform of Write with BUSY (M/S = VIL)
tWP
R/W"A"
(3)
tWB
BUSY"B"
tWH
R/W"B"
(1)
.
(2)
3199 drw 12
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the "Slave" version.
13
6.42
7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)(1,3)
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"
tAPS (2)
CE"B"
tBAC
tBDC
BUSY"B"
3199 drw 13
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing (M/S = VIH)(1)
ADDR"A"
ADDRESS "N"
tAPS
(2)
ADDR"B"
MATCHING ADDRESS "N"
tBAA
tBDA
BUSY"B"
3199 drw 14
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
3. Refer to Chip Enable Truth Table.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1)
7027X15
Com'l Only
Symbol
Parameter
7027X20
Com'l
& Ind
7027X25
Com'l
& Ind
7027X35
Com'l Only
7027X55
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
____
0
____
0
____
0
____
0
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
0
____
0
____
ns
tINS
Interrupt Set Time
____
15
____
20
____
20
____
25
____
40
ns
tINR
Interrupt Reset Time
____
15
____
20
____
20
____
25
____
40
ns
3199 tbl 15
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
14
6.42
7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1,5)
tWC
ADDR"A"
INTERRUPT SET ADDRESS
(2)
tAS (3)
tWR
(4)
CE"A"
R/W"A"
tINS
(3)
INT"B"
3199 drw 15
tRC
INTERRUPT CLEAR ADDRESS
ADDR"B"
tAS
(2)
(3)
CE"B"
OE"B"
tINR
(3)
INT"B"
3199 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See the Interrupt Truth Table IV.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
5. Refer to Chip Enable Truth Table.
Truth Table IV — Interrupt Flag(1,4)
Left Port
R/WL
L
X
X
X
CEL
L
X
X
L
OEL
X
X
X
L
Right Port
A14L-A0L
7FFF
INTL
X
R/WR
X
CER
X
OER
X
A14R-A0R
X
INTR
Function
(2)
Set Right INTR Flag
(3)
Reset Right INTR Flag
L
X
X
X
L
L
7FFF
H
X
(3)
L
L
X
7FFE
X
Set Left INTL Flag
(2)
X
X
X
X
X
Reset Left INTL Flag
7FFE
L
H
3199 tbl 16
NOTES:
1. Assumes BUSYL = BUSYR =VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. Refer to Chip Enable Truth Table.
15
6.42
7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table V —
Address Bus Arbitration(4)
Inputs
Outputs
CEL
CER
AOL-A14L
AOR-A14R
BUSYL(1)
BUSYR(1)
Function
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write
Inhibit(3)
3199 tbl 17
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT7027 are
push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of the actual logic level on the pin. Writes to the right port are internally
ignored when BUSYR outputs are driving LOW regardless of the actual logic level on the pin.
4. Refer to Chip Enable Truth Table.
Truth Table VI — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0 - D15 Left
D0 - D15 Right
Status
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7027.
2. There are eight semaphore flags written to via I/O0 and read from all the I/O's (I/O0-I/O15). These eight semaphores are addressed by A0-A2.
3. CE = VIH, SEM = VIL, to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
3199 tbl 18
Functional Description
The IDT7027 provides two ports with separate control, address and
I/O pins that permit independent access for reads or writes to any location
in memory. The IDT7027 has an automatic power down feature controlled
by CE0 and CE1. The CE0 and CE1 control the on-chip power down
circuitry that permits the respective port to go into a standby mode when
not selected (CE = VIH). When a port is enabled, access to the entire
memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(INTL) is asserted when the right port writes to memory location 7FFE
(HEX), where a write is defined as CER = R/WR = VIL per Truth Table
IV. The left port clears the interrupt through access of address location
7FFE when CEL= OEL= VIL, R/W is a "don't care". Likewise, the right port
interrupt flag (INTR) is asserted when the left port writes to memory location
7FFF (HEX) and to clear the interrupt flag (INTR), the right port must read
the memory location 7FFF. The message (16 bits) at 7FFE or 7FFF is
user-defined since it is an addressable SRAM location. If the interrupt
function is not used, address locations 7FFE and 7FFF are not used as
mail-boxes by ignoring the interrupt, but as part of the random access
memory. Refer to Truth Table IV for the interrupt operation.
16
6.42
7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “Busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a BUSY indication, the write signal is gated internally
to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of busy logic is not
desirable, the BUSY logic can be disabled by placing the part in slave mode
with the M/S pin. Once in slave mode the BUSY pin operates solely as a
write inhibit input pin. Normal operation can be programmed by tying the
BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT7027 RAM in master mode, are pushpull type outputs and do not require pull up resistors to operate. If these
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.
A15
CE0
MASTER
Dual Port RAM
BUSYL
BUSYR
CE1
MASTER
Dual Port RAM
BUSYL
BUSYL
BUSYR
CE0
SLAVE
Dual Port RAM
BUSYL
BUSYR
CE1
SLAVE
Dual Port RAM
BUSYL
BUSYR
BUSYR
.
3199 drw 17
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT7027 RAMs.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an IDT7027 RAM array in width while using BUSY
logic, one master part is used to decide which side of the RAM array
will receive a BUSY indication, and to output that indication. Any number
of slaves to be addressed in the same address range as the master, use
the BUSY signal as a write inhibit signal. Thus on the IDT7027 RAM the
BUSY pin is an output if the part is used as a Master (M/S pin = VIH), and
the BUSY pin is an input if the part used as a Slave (M/S pin = VIL) as shown
in Figure 3.
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating BUSY on one side of the
array and another master indicating BUSY on one other side of the array.
This would inhibit the write operations from one port for part of a word and
inhibit the write operations from the other port for the other part of the word.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual write
pulse can be initiated with either the R/W signal or the byte enables. Failure
to observe this timing can result in a glitched internal write inhibit signal and
corrupted data in the slave.
Semaphores
The IDT7027 is a fast Dual-Port 32K x 16 CMOS Static RAM with an
additional 8 address locations dedicated to binary semaphore flags. These
flags allow either processor on the left or right side of the Dual-Port SRAM
to claim a privilege over the other processor for functions defined by the
system designer’s software. As an example, the semaphore can be used
by one processor to inhibit the other from accessing a portion of the DualPort SRAM or any other shared resource.
The Dual-Port SRAM features a fast access time, and both ports are
completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be read from,
or written to, at the same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of, a nonsemaphore location. Semaphores are protected against such ambiguous
situations and may be used by the system program to avoid any conflicts
in the non-semaphore portion of the Dual-Port SRAM. These devices
have an automatic power-down feature controlled by CE the Dual-Port
SRAM enable, and SEM, the semaphore enable. The CE and SEM pins
control on-chip power down circuitry that permits the respective port to go
into standby mode when not selected. This is the condition which is shown
in Truth Table II where CE and SEM = VIH.
Systems which can best use the IDT7027 contain multiple processors
or controllers and are typically very high-speed systems which are
software controlled or software intensive. These systems can benefit
from a performance increase offered by the IDT7027's hardware
semaphores, which provide a lockout mechanism without requiring
complex programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in varying
configurations. The IDT7027 does not use its semaphore flags to control
any resources through hardware, thus allowing the system designer total
flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred in
either processor. This can prove to be a major advantage in very highspeed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are independent
of the Dual-Port SRAM. These latches can be used to pass a flag, or token,
from one port to the other to indicate that a shared resource is in use. The
semaphores provide a hardware assist for a use assignment method
called “Token Passing Allocation.” In this method, the state of a semaphore
latch is used as a token indicating that shared resource is in use. If the left
processor wants to use this resource, it requests the token by setting the
latch. This processor then verifies its success in setting the latch by reading
it. If it was successful, it proceeds to assume control over the shared
resource. If it was not successful in setting the latch, it determines that the
right side processor has set the latch first, has the token and is using the
shared resource. The left processor can then either repeatedly request
that semaphore’s status or remove its request for that semaphore to
17
6.42
7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
perform another task and occasionally attempt again to gain control of the
token via the set and test sequence. Once the right side has relinquished
the token, the left side should succeed in gaining control.
The semaphore flags are active low. A token is requested by writing
a zero into a semaphore latch and is released when the same side writes
a one to that latch.
The eight semaphore flags reside within the IDT7027 in a separate
memory space from the Dual-Port SRAM. This address space is accessed
by placing a low input on the SEM pin (which acts as a chip select for the
semaphore flags) and using the other control pins (Address, OE, and
R/W) as they would be used in accessing a standard Static RAM. Each
of the flags has a unique address which can be accessed by either side
through address pins A0 – A2. When accessing the semaphores, none of
the other address pins has any effect.
When writing to a semaphore, only data pin D0 is used. If a LOW level
is written into an unused semaphore location, that flag will be set to a zero
on that side and a one on the other side (see Truth Table VI). That
semaphore can now only be modified by the side showing the zero. When
a one is written into the same location from the same side, the flag will be
set to a one for both sides (unless a semaphore request from the other side
is pending) and then can be written to by both sides. The fact that the side
which is able to write a zero into a semaphore subsequently locks out writes
from the other side is what makes semaphore flags useful in interprocessor
communications. (A thorough discussion on the use of this feature follows
shortly.) A zero written into the same location from the other side will be
stored in the semaphore request latch for that side until the semaphore is
freed by the first side.
When a semaphore flag is read, its value is spread into all data bits so
that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros. The read value is latched into one side’s output
register when that side's semaphore select (SEM) and output enable (OE)
signals go active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the other side.
Because of this latch, a repeated read of a semaphore in a test loop must
cause either signal (SEM or OE) to go inactive or the output will never
change.
A sequence WRITE/READ must be used by the semaphore in order
to guarantee that no system level contention will occur. A processor
requests access to shared resources by attempting to write a zero into a
semaphore location. If the semaphore is already in use, the semaphore
request latch will contain a zero, yet the semaphore flag will appear as one,
a fact which the processor will verify by the subsequent read (see Truth
Table VI). As an example, assume a processor writes a zero to the left port
at a free semaphore location. On a subsequent read, the processor will
verify that it has written successfully to that location and will assume control
over the resource in question. Meanwhile, if a processor on the right side
attempts to write a zero to the same semaphore flag it will fail, as will be
verified by the fact that a one will be read from that semaphore on the right
side during subsequent read. Had a sequence of READ/WRITE been
used instead, system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must be followed
by either repeated reads or by writing a one into the same location. The
reason for this is easily understood by looking at the simple logic diagram
of the semaphore flag in Figure 4. Two semaphore request latches feed
into a semaphore flag. Whichever latch is first to present a zero to the
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
D0
D
Q
SEMAPHORE
REQUEST FLIP FLOP
Q
D
WRITE
D0
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
.
Figure 4. IDT7027 Semaphore Logic
3199 drw 18
semaphore flag will force its side of the semaphore flag LOW and the other
side HIGH. This condition will continue until a one is written to the same
semaphore request latch. Should the other side’s semaphore request latch
have been written to a zero in the meantime, the semaphore flag will flip
over to the other side as soon as a one is written into the first side’s request
latch. The second side’s flag will now stay LOW until its semaphore request
latch is written to a one. From this it is easy to understand that, if a semaphore
is requested and the processor which requested it no longer needs the
resource, the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides request a
single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives
the token. If one side is earlier than the other in making the request, the
first side to make the request will receive the token. If both requests
arrive at the same time, the assignment will be arbitrarily made to one port
or the other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is secure.
As with any powerful programming technique, if semaphores are misused
or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be handled
via the initialization program at power-up. Since any semaphore request
flag which contains a zero must be reset to a one, all semaphores on both
sides should have a one written into them at initialization from both sides
to assure that they will be free when needed.
18
6.42
7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
XXXXX
A
999
A
Device
Type
Power
Speed
Package
A
A
A
Process/
Temperature
Range
Blank
8
Tray
Tape and Reel
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to + 85°C)
G(2)
Green
PF
G
100-pin TQFP (PNG100)
108-pin PGA (GU108)
15
20
25
35
55
Commercial Only
Industrial Only
Commercial Only
Commercial Only
Commercial Only
S
L
Standard Power
Low Power
7027
512K (32K x 16) Dual-Port RAM
Speed in nanoseconds
3199 drw 19
NOTES:
1. Contact your local sales office for industrial temp range for other speeds, packages and powers.
2. Green parts available. For specific speeds, packages and powers contact your local sales office
LEAD FINISH (SnPb) parts are Obsolete. Product Discontinuation Notice - PDN# SP-17-02
Note that information regarding recently obsoleted parts is included in this datasheet for customer convenience.
Orderable Part Information
Speed
(ns)
Orderable Part ID
Pkg.
Code
Pkg.
Type
Temp.
Grade
Speed
(ns)
Orderable Part ID
Pkg.
Code
Pkg.
Type
Temp.
Grade
15
7027L15PFG
PNG100
TQFP
C
25
7027S25G
GU108
PGA
C
7027L15PFG8
PNG100
TQFP
C
35
7027S35G
GU108
PGA
C
20
7027L20PFGI
PNG100
TQFP
I
55
7027S55G
GU108
PGA
C
7027L20PFGI8
PNG100
TQFP
I
25
7027L25G
GU108
PGA
C
35
7027L35G
GU108
PGA
C
55
7027L55G
GU108
PGA
C
19
6.42
7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Datasheet Document History
01/15/99:
05/19/99:
06/03/99:
11/10/99:
05/22/00:
07/23/04:
01/29/09:
08/04/15:
06/08/18:
06/03/19:
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Pages 2 and 3 Added additional notes to pin configurations
Pages 4 and 16 Fixed typographical errors
Changed drawing format
Page 1 Corrected DSC number
Replaced IDT logo
Page 5 Increased storage temperature parameter
Clarified TA parameter
Page 6 DC Electrical parameters–changed wording from "open" to "disabled"
Changed ±200mV to 0mV in notes
Page 2 & 3 Added date revision for pin configurations
Page 5 Updated Capacitance table
Page 6 Added 15ns commercial speed grade to the DC Electrical Characteristics
Added 20ns Industrial temp for low power to DC Electrical Characteristics
Removed military temp range for 25/35/55ns from DC Electrical Characteristics
Page 7, 9, 12 & 14 Added 15ns commercial speed grade to AC Electrical Characteristics
Added 20ns Industrial temp for low power to AC Electrical Characteristics for Read, Write, Busy and Interrupt
Removed military temp range for 25/35/55ns from AC Electrical Characteristics
Page 19 Added Commercial speed grade for 15ns and Industrial temp to 20ns in ordering information
Page 1 & 19 Replaced old TM logo with new TM logo
Page 19 Removed "IDT" from orderable part number
Page 1 In Features: Added text: “Green parts available, see ordering information”
Page 2 Removed IDT in reference to fabrication
Page 2 & 5 Removed all of the military information
Page 2 & 3 Removed date from all of the pin configurations 100-pin TQFP & 108-pin PGA configurations
Page 2, 3 & 17 The package code PN100-1 and G108-1 changed to PN100 and G108 respectively to
match standard package codes
Page 7 Added annotation for footnote 5 to Chip Enable & Chip Disable Parameters in the AC Elec Chars table
Page 17 Removed overbar for CE1 in figure 3
Page 19 Added T&R and Green, removed military temp range and updated footnotes for ordering information
Product Discontinuation Notice - PDN# SP-17-02
Last time buy expires June 15, 2018
Page 1 & 19 Updated Industrial speed grade offering in Features and Ordering Information
Page 2 Changed diagram for the PNG100 pin configuration by rotating package pin labels and pin numbers 90 degrees
counter clockwise to refect pin 1 orientation and added pin 1 dot at pin 1
Aligned the top and bottom pin labels in the standard direction
Added IDT logo to the PNG100 pin configuration and changed the text to be in alignment with new diagram marking specs
Updated footnote reference for PNG100
Page 2, 3 & 19 The package codes for PN100 changed to PNG100 and for G108 changed to GU108 respectively to
match standard package codes
Page 19 Revised LEAD FINISH note to indicate Obsolete
Page 19 Added Orderable Part Information
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
20
6.42
for Tech Support:
408-284-2794
DualPortHelp@idt.com
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