HIGH-SPEED 3.3V
32/16K x 16
SYNCHRONOUS
DUAL-PORT STATIC RAM
Features:
◆
◆
◆
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 7.5/9ns (max.)
– Industrial: 7.5ns (max.)
Low-power operation
– IDT70V9279/69L
Active: 429mW (typ.)
Standby: 1.32mW (typ.)
Flow-through or Pipelined output mode on either port via
the FT/PIPE pin
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
◆
◆
◆
◆
◆
◆
70V9279/69S/L
Full synchronous operation on both ports
– 4ns setup to clock and 1ns hold on all control, data,
and address inputs
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 10ns cycle time, 100MHz operation in Pipelined output mode
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
LVTTL- compatible, single 3.3V (±0.3V) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
Available in a 128-pin Thin Quad Flatpack (TQFP) package
Green parts available, see ordering information
Functional Block Diagram
R/WL
R/WR
UBL
UBR
CE0L
CE0R
1
0
0/1
1
0
CE1L
0/1
CE1R
LBL
OEL
LBR
OER
FT/PIPEL
0/1
1b 0bb
a
1a 0a
0a 1a
a
0b 1b
b
0/1
FT/PIPER
,
I/O8L-I/O15L
I/O8R-I/O15R
I/O
Control
I/O
Control
I/O0L-I/O7L
I/O0R-I/O7R
A14R(1)
A14L(1)
A0L
CLKL
ADSL
CNTEN L
Counter/
Address
Reg.
MEMORY
ARRAY
CNTRSTL
Counter/
Address
Reg.
A0R
CLKR
ADSR
CNTENR
CNTRSTR
3743 drw 01
NOTE:
1. A14X is a NC for IDT70V9269.
AUGUST 2019
1
©2019 Integrated Device Technology, Inc.
DSC 3743/13
70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Description:
Industrial and Commercial Temperature Ranges
The IDT70V9279/69 is a high-speed 32/16K x 16 bit synchronous
Dual-Port RAM. The memory array utilizes Dual-Port memory cells to
allow simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold times.
The timing latitude provided by this approach allows systems to be
designed with very short cycle times.
With an input data register, the IDT70V9279/69 has been optimized for
applications having unidirectional or bidirectional data flow in bursts. An
automatic power down feature, controlled by CE0 and CE1, permits the
on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using CMOS high-performance technology, these devices
typically operate on only 429mW of power.
70V9279/69
PKG128(5)
128-Pin TQFP
Top View(6)
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
A14L(1)
N/C
N/C
N/C
LBL
UBL
CE0L
CE1L
CNTRSTL
VDD
VSS
R/WL
OEL
FT/PIPEL
VSS
I/O15L
I/O14L
I/O13L
I/O12L
VDD
VSS
I/O11L
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
A10L
A11L
A12L
A13L
N/C
N/C
N/C
N/C
A9R
A8R
A7R
A6R
A5R
A4R
A3R
A2R
A1R
A0R
N/C
CNTENR
CLKR
ADSR
VSS
VDD
ADSL
CLKL
CNTENL
N/C
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
N/C
N/C
N/C
N/C
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
A10R
A11R
A12R
A13R
A14R(1)
N/C
N/C
N/C
LBR
UBR
CE0R
CE1R
CNTRSTR
VDD
VSS
R/WR
OER
FT/PIPER
Vss
I/O15R
I/O14R
I/O13R
I/O12R
VDD
VDD
I/O11R
Pin Configuration(2,3,4)
NOTES:
1. A14X is a NC for IDT70V9269.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground.
4. Package body is approximately 14mm x 20mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
2
I/O10R
I/O9R
VSS
N/C
I/O8R
N/C
N/C
I/O7R
VDD
I/O6R
I/O5R
I/O4R
VSS
I/O3R
VDD
I/O2R
I/O1R
I/O0R
VSS
VDD
I/O0L
I/O1L
VSS
I/O2L
I/O3L
VSS
I/O4L
I/O5L
I/O6L
I/O7L
VDD
N/C
N/C
I/O8L
N/C
VDD
I/O9L
I/O10L
3743 drw 02
70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
Names
CE0L, CE1L
CE0R, CE1R
Chip Enables (3)
R/WL
R/WR
Read/Write Enable
OEL
OER
Output Enable
A0L - A14L(1)
A0R - A14R(1)
Address
I/O0L - I/O15L
I/O0R - I/O15R
Data Input/Output
CLKL
CLKR
Clock
UBL
UBR
Upper Byte Select(2)
LBL
LBR
Lower Byte Select(2)
ADSL
ADSR
Address Strobe Enable
CNTENL
CNTENR
Counter Enable
CNTRSTL
CNTRSTR
Counter Reset
FT/PIPEL
FT/PIPER
Flow-Through / Pipeline
VDD
Power (3.3V)
VSS
Ground (0V)
NOTES:
1. Address A14X is a NC for IDT70V9269.
2. LB and UB are single buffered regardless of state of FT/PIPE.
3. CE0 and CE1 are single buffered when FT/PIPE = VIL,
CE0 and CE1 are double buffered when FT/PIPE = VIH,
i.e. the signals take two cycles to deselect.
3743 tbl 01
Truth Table I—Read/Write and Enable Control(1,2,3)
UB(4)
LB(4)
R/W
Upper Byte
I/O8-15
Lower Byte
I/O0-7
X
X
X
X
High-Z
High-Z
Deselected–Power Down
X
L
X
X
X
High-Z
High-Z
Deselected–Power Down
↑
L
H
H
H
X
High-Z
High-Z
Both Bytes Deselected
↑
L
H
L
H
L
DIN
High-Z
Write to Upper Byte Only
X
↑
L
H
H
L
L
High-Z
DATAIN
Write to Lower Byte Only
X
↑
L
H
L
L
L
DATA IN
DATAIN
Write to Both Bytes
L
↑
L
H
L
H
H
DATAOUT
High-Z
Read Upper Byte Only
L
↑
L
H
H
L
H
High-Z
DATAOUT
Read Lower Byte Only
L
↑
L
H
L
L
H
DATAOUT
DATAOUT
Read Both Bytes
H
↑
L
H
L
L
X
High-Z
High-Z
Outputs Disabled
OE
CLK
CE0(5)
X
↑
H
X
↑
X
X
(5)
CE1
MODE
3743 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
4 LB and UB are single buffered regardless of state of FT/PIPE.
5. CEo and CE1 are single buffered when FT/PIPE = VIL. CEo and CE1 are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect.
6.42
3
70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Truth Table II—Address Counter Control(1,2,3)
External
Address
Previous
Internal
Address
Internal
Address
Used
CLK
An
X
An
↑
ADS
CNTEN
CNTRST
I/O(3)
X
H
DI/O (n)
L(4)
(5)
MODE
External Address Used
X
An
An + 1
↑
H
L
H
DI/O(n+1)
Counter Enabled—Internal Address generation
X
An + 1
An + 1
↑
H
H
H
DI/O(n+1)
External Address Blocked—Counter disabled (An + 1 reused)
X
X
A0
↑
X
X
L(4)
DI/O(0)
Counter Reset to Address 0
3743 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. CE0, LB, UB, and OE = VIL; CE1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS and CNTRST are independent of all other signals including CE0, CE1, UB and LB.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB.
Recommended Operating
Temperature and Supply Voltage(1,2)
Grade
Commercial
Industrial
Symbol
Ambient
Temperature
GND
VDD
0OC to +70OC
0V
3.3V + 0.3V
-40OC to +85OC
0V
3.3V + 0.3V
3743 tbl 04
NOTES:
1. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
2. This is the parameter TA. This is the "instant on" case temperature.
Rating
Commercial
& Industrial
Unit
Terminal Voltage
with Respect to
GND
-0.5 to +4.6
V
TBIAS(3)
Temperature Under Bias
-55 to +125
o
TSTG
StorageTemperature
-65 to +150
o
C
TJN
Junction Temperature
+150
o
C
IOUT
DC Output Current
VTERM(2)
Min.
Typ.
Max.
Unit
3.0
3.3
3.6
V
0
0
0
V
VDD
Supply Voltage
VSS
Ground
VIH
Input High Voltage
2.2
____
VDD+0.3V(2)
V
VIL
Input Low Voltage
-0.3(1)
____
0.8
V
3743 tbl 05
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VDD + 0.3V.
(TA = +25°C, f = 1.0MHZ)
Symbol
CIN
COUT
C
Parameter
Input Capacitance
(2)
50
Parameter
Capacitance(1)
Absolute Maximum Ratings(1)
Symbol
Recommended DC Operating
Conditions
Output Capacitance
Conditions
Max.
Unit
VIN = 0V
9
pF
VOUT = 0V
10
pF
3743 tbl 07
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. COUT also references CI/O.
mA
3743 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD + 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VDD + 0.3V.
3. Ambient Temperature Under DC Bias. No AC Conditions. Chip Deselected.
6.42
4
70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V)
70V9279/69S
Symbol
Parameter
Test Conditions
(1)
70V9279/69L
Min.
Max.
Min.
Max.
Unit
|ILI|
Input Leakage Current
VDD = 3.6V, VIN = 0V to VDD
___
10
___
5
µA
|ILO|
Output Leakage Current
CE0 = VIH or CE1 = VIL, VOUT = 0V to VDD
___
10
___
5
µA
VOL
Output Low Voltage
IOL = +4mA
___
0.4
___
0.4
V
VOH
Output High Voltage
IOH = -4mA
2.4
___
2.4
___
V
3743 tbl 08
NOTE:
1. At VDD < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range(3,6) (VDD = 3.3V ± 0.3V)
70V9279/69X6
Com'l Only
Symbol
IDD
ISB1
ISB2
ISB3
ISB4
Parameter
Test Condition
Dynamic
Operating
Current (Both
Ports Active)
CEL and CER= VIL,
Outputs Disabled,
f = fMAX(1)
Standby
Current (Both
Ports - TTL
Level Inputs)
CEL = CER = VIH
f = fMAX(1)
Version
70V9279/69X7
Com'l
& Ind
70V9279/69X9
Com'l Only
Typ.(4)
Max.
Typ.(4)
Max.
Typ.(4)
Max.
Unit
mA
COM'L
S
L
220
220
395
350
200
200
335
290
180
180
260
225
IND
S
L
____
____
370
335
____
____
200
200
____
____
____
____
COM'L
S
L
70
70
145
130
60
60
115
100
50
50
75
65
IND
S
L
____
____
130
115
____
____
60
60
____
____
____
____
Standby
Current (One
Port - TTL
Level Inputs)
COM'L
CE"A" = VIL and
CE"B" = VIH(5)
Active Port Outputs Disabled,
IND
f=fMAX(1)
S
L
150
150
280
250
130
130
240
210
110
110
170
150
S
L
____
____
265
240
____
____
130
130
____
____
____
____
Full Standby
Current (Both
Ports - CMOS
Level Inputs)
Both Ports CEL and
CER > VDD - 0.2V,
VIN > VDD - 0.2V or
VIN < 0.2V, f = 0(2)
COM'L
S
L
1.0
0.4
5
3
1.0
0.4
5
3
1.0
0.4
5
3
IND
S
L
____
____
20
15
____
____
1.0
0.4
____
____
____
____
Full Standby
Current (One
Port - CMOS
Level Inputs)
CE"A" < 0.2V and
CE"B" > VDD - 0.2V(5)
VIN > VDD - 0.2V or
VIN < 0.2V, Active Port,
Outputs Disabled, f = fMAX(1)
COM'L
S
L
140
140
270
240
120
120
230
200
100
100
160
140
IND
S
L
____
____
255
230
____
____
120
120
____
____
____
____
mA
mA
mA
mA
3743 tbl 09a
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of VSS to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 90mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V
CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X < 0.2V
'X' represents "L" for left port or "R" for right port.
6. 'X' in part numbers indicate power rating (S or L).
6.42
5
70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range(3,6) (VDD = 3.3V ± 0.3V)(Cont'd)
70V9279/69X12
Com'l Only
Symbol
IDD
ISB1
ISB2
ISB3
ISB4
Parameter
Test Condition
Dynamic
Operating
Current (Both
Ports Active)
CEL and CER= VIL,
Outputs Disabled,
f = fMAX(1)
Standby
Current (Both
Ports - TTL
Level Inputs)
CEL = CER = VIH
f = fMAX(1)
Version
70V9279/69X15
Com'l Only
Typ.(4)
Max.
Typ.(4)
Max.
Unit
mA
COM'L
S
L
150
150
240
205
130
130
220
185
IND
S
L
____
____
____
____
____
____
____
____
COM'L
S
L
40
40
65
50
30
30
55
35
IND
S
L
____
____
____
____
____
____
____
____
Standby
Current (One
Port - TTL
Level Inputs)
COM'L
CE"A" = VIL and
CE"B" = VIH(5)
Active Port Outputs Disabled,
IND
f=fMAX(1)
S
L
100
100
160
140
90
90
150
130
S
L
____
____
____
____
____
____
____
____
Full Standby
Current (Both
Ports - CMOS
Level Inputs)
Both Ports CEL and
CER > VDD - 0.2V,
VIN > VDD - 0.2V or
VIN < 0.2V, f = 0(2)
COM'L
S
L
1.0
0.4
5
3
1.0
0.4
5
3
IND
S
L
____
____
____
____
____
____
____
____
Full Standby
Current (One
Port - CMOS
Level Inputs)
CE"A" < 0.2V and
CE"B" > VDD - 0.2V(5)
VIN > VDD - 0.2V or
VIN < 0.2V, Active Port,
Outputs Disabled, f = fMAX(1)
COM'L
S
L
90
90
150
130
80
80
140
120
IND
S
L
____
____
____
____
____
____
____
____
mA
mA
mA
mA
3743 tbl 09b
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of VSS to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 90mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V
CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X < 0.2V
'X' represents "L" for left port or "R" for right port.
6. 'X' in part numbers indicate power rating (S or L).
6.42
6
70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
Figures 1, 2, and 3
7343 tbl 10
3.3V
3.3V
590Ω
590Ω
DATAOUT
DATAOUT
30pF
435Ω
435Ω
3743 drw 03
3743 drw 04
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
Figure 1. AC Output Test load.
8
7
10pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
6
5
tCD1,
tCD2
(Typical, ns)
4
3
2
1
0
-1
5pF*
20 40 60 80 100 120 140 160 180 200
Capacitance (pF)
3743 drw 05
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.42
7
70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3,4) (VDD = 3.3V ± 0.3V, TA = 0°C to +70°C)
Symbol
tCYC1
Parameter
Clock Cycle Time (Flow-Through)
(2)
(2)
70V9279/69X6
Com'l Only
70V9279/69X7
Com'l
& Ind
70V9279/69X9
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Unit
19
____
22
____
25
____
ns
ns
tCYC2
Clock Cycle Time (Pipelined)
10
____
12
____
15
____
tCH1
Clock High Time (Flow-Through)(2)
6.5
____
7.5
____
12
____
ns
tCL1
(2)
tCH2
Clock Low Time (Flow-Through)
6.5
____
7.5
____
12
____
ns
(2)
4
____
5
____
6
____
ns
(2)
4
____
5
____
6
____
ns
Clock High Time (Pipelined)
tCL2
Clock Low Time (Pipelined)
tR
Clock Rise Time
____
3
____
3
____
3
ns
tF
Clock Fall Time
____
3
____
3
____
3
ns
tSA
Address Setup Time
3.5
____
4
____
4
____
ns
tHA
Address Hold Time
0
____
0
____
1
____
ns
tSC
Chip Enable Setup Time
3.5
____
4
____
4
____
ns
tHC
Chip Enable Hold Time
0
____
0
____
1
____
ns
tSW
R/W Setup Time
3.5
____
4
____
4
____
ns
tHW
R/W Hold Time
0
____
0
____
1
____
ns
tSD
Input Data Setup Time
3.5
____
4
____
4
____
ns
tHD
Input Data Hold Time
0
____
0
____
1
____
ns
ADS Setup Time
3.5
____
4
____
4
____
ns
ADS Hold Time
0
____
0
____
1
____
ns
____
4
____
4
____
ns
tSAD
tHAD
tSCN
CNTEN Setup Time
3.5
tHCN
CNTEN Hold Time
0
____
0
____
1
____
ns
tSRST
CNTRST Setup Time
3.5
____
4
____
4
____
ns
tHRST
CNTRST Hold Time
tOE
Output Enable to Data Valid
tOLZ
(1)
Output Enable to Output Low-Z
(1)
0
____
0
____
1
____
ns
____
6.5
____
7.5
____
9
ns
2
____
2
____
2
____
ns
tOHZ
Output Enable to Output High-Z
1
7
1
7
1
7
ns
tCD1
Clock to Data Valid (Flow-Through)(2)
____
15
____
18
____
20
ns
tCD2
Clock to Data Valid (Pipelined)(2)
____
6.5
____
7.5
____
9
ns
tDC
Data Output Hold After Clock High
2
____
2
____
2
____
ns
tCKHZ
tCKLZ
(1)
2
9
2
9
2
9
ns
(1)
2
____
2
____
2
____
ns
ns
Clock High to Output High-Z
Clock High to Output Low-Z
Port-to-Port Delay
tCWDD
Write Port Clock High to Read Data Delay
____
24
____
28
____
35
tCCS
Clock-to-Clock Setup Time
____
9
____
10
____
15
ns
3743 tbl 11a
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characterization, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply when
FT/PIPE = VIL for that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a
DC signal, i.e. steady state during operation.
4. 'X' in part number indicates power rating (S or L).
6.42
8
70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3,4) (VDD = 3.3V ± 0.3V, TA = 0°C to +70°C)(Cont'd)
Symbol
tCYC1
tCYC2
tCH1
Parameter
Clock Cycle Time (Flow-Through)
Clock Cycle Time (Pipelined)
(2)
(2)
Clock High Time (Flow-Through)
(2)
(2)
70V9279/69X12
Com'l Only
70V9279/69X15
Com'l Only
Min.
Max.
Min.
Max.
Unit
30
____
35
____
ns
20
____
25
____
ns
12
____
12
____
ns
12
____
ns
10
____
ns
tCL1
Clock Low Time (Flow-Through)
12
____
tCH2
Clock High Time (Pipelined)(2)
8
____
(2)
tCL2
Clock Low Time (Pipelined)
8
____
10
____
ns
Clock Rise Time
____
3
____
tR
3
ns
tF
Clock Fall Time
____
3
____
3
ns
tSA
Address Setup Time
4
____
4
____
ns
tHA
Address Hold Time
1
____
1
____
ns
tSC
Chip Enable Setup Time
4
____
4
____
ns
tHC
Chip Enable Hold Time
1
____
1
____
ns
tSW
R/W Setup Time
4
____
4
____
ns
tHW
R/W Hold Time
1
____
1
____
ns
tSD
Input Data Setup Time
4
____
4
____
ns
tHD
Input Data Hold Time
1
____
1
____
ns
ADS Setup Time
4
____
4
____
ns
ADS Hold Time
1
____
1
____
ns
ns
tSAD
tHAD
tSCN
CNTEN Setup Time
4
____
4
____
tHCN
CNTEN Hold Time
1
____
1
____
ns
tSRST
CNTRST Setup Time
4
____
4
____
ns
tHRST
CNTRST Hold Time
tOE
Output Enable to Data Valid
tOLZ
(1)
Output Enable to Output Low-Z
(1)
1
____
1
____
ns
____
12
____
15
ns
2
____
2
____
ns
tOHZ
Output Enable to Output High-Z
1
7
1
7
ns
tCD1
Clock to Data Valid (Flow-Through)(2)
____
25
____
30
ns
tCD2
Clock to Data Valid (Pipelined)(2)
____
12
____
15
ns
tDC
Data Output Hold After Clock High
2
____
2
____
ns
2
9
2
9
ns
2
____
2
____
ns
ns
tCKHZ
tCKLZ
(1)
Clock High to Output High-Z
(1)
Clock High to Output Low-Z
Port-to-Port Delay
tCWDD
Write Port Clock High to Read Data Delay
____
40
____
50
tCCS
Clock-to-Clock Setup Time
____
15
____
20
ns
3743 tbl 11b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characterization, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply when
FT/PIPE = VIL for that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a
DC signal, i.e. steady state during operation.
4. 'X' in part number indicates power rating (S or L).
6.42
9
70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Flow-through Output
(FT/PIPE"X" = VIL)(3,7)
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
tSB
tHB
tSC
tHC
tSB
tHB
CE1
UB, LB
R/W
tSW tHW
tSA
(5)
ADDRESS
tHA
An
An + 1
tCD1
tCKLZ
An + 3
tCKHZ (1)
Qn
DATAOUT
OE
An + 2
tDC
Qn + 1
Qn + 2
(1)
(1)
tOHZ
tOLZ
tDC
(1)
(2)
tOE
3743 drw 06
Timing Waveform of Read Cycle for Pipelined Output
(FT/PIPE"X" = VIH)(3,7)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tSC
tHC
tHC
(4)
CE1
tSB
tSB
tHB
tHB
(6)
UB, LB
R/W
(5)
ADDRESS
tSW
tHW
tSA
tHA
An
An + 1
(1 Latency)
An + 2
tDC
tCD2
DATAOUT
Qn
(1)
tCKLZ
OE
An + 3
Qn + 2(6)
Qn + 1
tOHZ(1)
tOLZ(1)
(2)
tOE
NOTES:
3743 drw 07
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
3. ADS = VIL, CNTEN and CNTRST = VIH.
4. The output is disabled (High-Impedance state) by CE 0 = V IH or CE 1 = V IL following the next rising edge of the clock. Refer to Truth Table 1.
5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
6. If UB or LB was HIGH, then the Upper Byte and/or Lower Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
7. "X" denotes Left or Right port. The diagram is with respect to that port.
6.42
10
70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of a Bank Select Pipelined Read(1,2)
tCH2
tCYC2
tCL2
CLK
tSA
tHA
A0
ADDRESS(B1)
tSC
tHC
CE0(B1)
tSC
tHC
Q0
DATAOUT(B1)
tCD2
Q3
Q1
tDC
tDC
tSA
tCKHZ(3)
tCD2
tCD2
tCKLZ
(3)
tCKHZ(3)
tHA
A0
ADDRESS(B2)
A6
A5
A4
A3
A2
A1
A6
A5
A4
A3
A2
A1
tSC tHC
CE0(B2)
tSC
tHC
tCD2
DATAOUT(B2)
tCKLZ(3)
tCKHZ
(3)
tCD2
Q2
Q4
tCKLZ (3)
3743 drw 08
Timing Waveform of a Bank Select Flow-Through Read(6)
tCH1
tCYC1
tCL1
CLK
tSA
A0
ADDRESS(B1)
CE0(B1)
tHA
tSC
tHC
tSC
tCD1
tHC
tCD1
tCKHZ
D0
DATAOUT(B1)
tSC
tCD1
D3
tCKLZ
tDC
A1
(1)
D5
tCKHZ (1)
tCKLZ
(1)
A6
A5
A4
A3
A2
tSC
CE0(B2)
tCD1
tHA
A0
ADDRESS(B2)
(1)
D1
tDC
tSA
A6
A5
A4
A3
A2
A1
tHC
tHC
tCD1
DATAOUT(B2)
tCKLZ
(1)
tCKHZ
(1)
tCD1
D2
tCKLZ
(1)
tCKHZ
(1)
D4
3743 drw 08a
NOTES:
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT70V9279/69 for this waveform, and are setup for depth expansion in this
example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
6.42
11
70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform with Port-to-Port Flow-Through Read(1,2,3,5)
CLK "A"
tSW
tHW
tSA
tHA
R/W "A"
ADDRESS "A"
NO
MATCH
MATCH
tSD
DATAIN "A"
tHD
VALID
tCCS
(4)
CLK "B"
tCD1
R/W "B"
ADDRESS "B"
tSW
tHW
tSA
tHA
NO
MATCH
MATCH
tCWDD (4)
tCD1
DATAOUT "B"
VALID
VALID
tDC
tDC
3743 drw 09
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
3. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
4. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
5. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
Timing Waveform of Left Port Write to Pipelined Right Port Read(1,2,4)
CLK"A"
tSW
tHW
tSA
tHA
R/W"A
"
ADDRESS"A"
tSD
DATAIN"A"
NO
MATCH
MATCH
tHD
VALID
tCO(3)
CLK"B"
tCD2
R/W"B"
ADDRESS"B"
tSW
tHW
tSA
tHA
NO
MATCH
MATCH
DATAOUT"B"
VALID
tDC
,
3743 drw 10
NOTES:
1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2. OE = VIL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be
tCO + 2 tCYC2 + tCD2). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port
will be tCO + tCYC2 + tCD2).
4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
6.42
12
70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)
tCYC2
tCH2
tCL2
CLK
CE0
tSC tHC
CE1
tSB
tHB
UB, LB
tSW tHW
R/W
(4)
ADDRESS
tSW tHW
An
tSA tHA
An +1
An + 2
An + 4
An + 3
An + 2
tSD tHD
DATAIN
Dn + 2
tCD2
(2)
(1)
(1)
tCD2
tCKLZ
tCKHZ
Qn + 3
Qn
DATAOUT
(5)
READ
NOP
WRITE
READ
,
3743 drw 11
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
tCH2
tCYC2
tCL2
CLK
CE0
tSC tHC
CE1
tSB
tHB
UB, LB
tSW tHW
R/W
(4)
ADDRESS
tSW tHW
An
tSA tHA
An +1
An + 2
An + 3
An + 4
An + 5
tSD tHD
DATAIN
Dn + 3
Dn + 2
tCD2
(2)
tCKLZ(1)
tCD2
Qn
DATAOUT
Qn + 4
tOHZ(1)
OE
READ
WRITE
READ
3743 drw 12
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be rewritten to guarantee data integrity.
6.42
13
,
70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3)
tCH1
tCYC1
tCL1
CLK
CE0
tSC tHC
CE1
tSB
tHB
UB, LB
tSW tHW
R/W
tSW tHW
(4)
An
tSA tHA
ADDRESS
An +1
An + 2
An + 4
An + 3
An + 2
tSD tHD
DATAIN
Dn + 2
tCD1
(2)
tCD1
Qn
DATAOUT
tCD1
tCD1
Qn + 1
tDC
tCKHZ
READ
NOP
(1)
Qn + 3
tDC
(1)
tCKLZ
(5)
READ
WRITE
,
3743 drw 13
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(3)
tCYC1
tCH1
tCL1
CLK
CE0
tSC tHC
CE1
tSB
tHB
UB, LB
tSW tHW
tSW tHW
R/W
(4)
An
tSA tHA
ADDRESS
An +1
DATAIN
(2)
DATAOUT
An + 2
tSD tHD
An + 3
Dn + 2
Dn + 3
tDC
tCD1
Qn
An + 4
tOE
tCD1
(1)
tCKLZ
tOHZ(1)
An + 5
tCD1
Qn + 4
tDC
OE
READ
WRITE
READ
,
3743 drw 14
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be rewritten to guarantee data integrity.
6.42
14
70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance(1)
tCYC2
tCH2
tCL2
CLK
tSA
ADDRESS
tHA
An
tSAD tHAD
ADS
tSAD tHAD
CNTEN
tSCN tHCN
tCD2
DATAOUT
Qx - 1(2)
,
Qn + 2(2)
Qn + 1
Qn
Qx
Qn + 3
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
3743 drw 15
Timing Waveform of Flow-Through Read with Address Counter Advance(1)
tCYC1
tCH1
tCL1
CLK
tSA
ADDRESS
tHA
An
tSAD tHAD
ADS
tSAD tHAD
tSCN tHCN
CNTEN
tCD1
DATAOUT
Qx(2)
Qn
Qn + 1
Qn + 2
Qn + 3(2)
,
Qn + 4
tDC
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
READ
WITH
COUNTER
3743 drw 16
NOTES:
1. CE0, OE, UB, and LB = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data
output remains constant for subsequent clocks.
6.42
15
70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-Through or Pipelined Outputs)(1)
tCH2
tCYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 2
An + 1
An + 4
An + 3
tSAD tHAD
ADS
CNTEN(7)
tSD tHD
Dn + 1
Dn
DATAIN
WRITE
EXTERNAL
ADDRESS
Dn + 1
Dn + 4
Dn + 3
Dn + 2
WRITE
WRITE
WITH COUNTER COUNTER HOLD
WRITE WITH COUNTER
3743 drw 17
,
Timing Waveform of Counter Reset (Pipelined Outputs)(2)
tCYC2
tCH2
tCL2
CLK
tSA tHA
(4)
An
ADDRESS
INTERNAL(3)
ADDRESS
Ax(6)
0
1
An + 2
An + 1
An
An + 1
tSW tHW
R/W
ADS
tSA
tHAD
D
CNTEN
tSCN tHCN
tSRST tHRST
CNTRST
tSD tHD
D0
DATAIN
(5)
Q1
Q0
DATAOUT
COUNTER
RESET
(6)
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
READ
ADDRESS n
READ
ADDRESS n+1
Qn
,
3743 drw 18
NOTES:
1. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH.
2. CE0, UB, LB = VIL; CE1 = VIH.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. ADDR0 will be accessed. Extra cycles
are shown here simply for clarification.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance.
The ‘An +1’Address is written to during this cycle.
6.42
16
70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Functional Description
Depth and Width Expansion
The IDT70V9279/69 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold times
on address, data, and all critical control inputs. All internal registers are
clocked on the rising edge of the clock signal, however, the self-timed
internal write pulse is independent of the LOW to HIGH transition of the clock
signal.
An asynchronous output enable is provided to ease asynchronous
bus interfacing. Counter enable inputs are also provided to staff the
operation of the address counters for fast interleaved memory applications.
A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down
the internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT70V9279/69's for depth
expansion configurations. When the Pipelined output mode is enabled, two
cycles are required with CE0 LOW and CE1 HIGH to reactivate the outputs.
The IDT70V9279/69 features dual chip enables (refer to Truth Table
I) in order to facilitate rapid and simple depth expansion with no requirements for external logic. Figure 4 illustrates how to control the various chip
enables in order to expand two devices in depth.
The IDT70V9279/69 can also be used in applications requiring
expanded width, as indicated in Figure 4. Since the banks are allocated
at the discretion of the user, the external controller can be set up to drive
the input signals for the various devices as required to allow for 32-bit or
wider applications.
A15/A14(1)
IDT70V9279/69
IDT70V9279/69
CE0
CE1
VDD
Control Inputs
IDT70V9279/69
CE0
CE1
VDD
Control Inputs
IDT70V9279/69
CE1
CE0
CE1
CE0
Control Inputs
Control Inputs
3743 drw 19
Figure 4. Depth and Width Expansion with IDT70V9279/69
NOTE:
1. A15 is for IDT70V9279. A14 is for IDT70V9269.
6.42
17
,
CNTRST
CLK
ADS
CNTEN
R/W
LB, UB
OE
70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
XXXXX
A
99
A
Device
Type
Power
Speed
Package
A
A
A
Process/
Temperature
Range
Blank
8
Tray
Tape and Reel
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G
Green
PRF
128-pin TQFP (PKG128)
7
9
Commercial & Industrial
Commercial Only
L
Low Power
70V9279
70V9269
512K (32K x 16-Bit) Synchronous Dual-Port RAM
256K (16K x 16-Bit) Synchronous Dual-Port RAM
Speed in nanoseconds
3743 drw 20
NOTES:
1. Contact your local sales office for industrial temp. range for other speeds, packages and powers.
LEAD FINISH (SnPb) parts are Obsolete. Product Discontinuation Notice - PDN# SP-17-02
Note that information regarding recently obsoleted parts are included in this datasheet for customer convenience.
Ordering Information for Flow-through Devices
Old Flow-through Part
New Combined Part
70V927S/L25
70V9279L7
70V927S/L30
70V9279L9
3743 tbl 12
IDT Clock Solution for IDT70V9279/69 Dual-Port
Dual-Port I/O Specitications
IDT Dual-Port
Part Number
Voltage
70V9279/69
3.3
Clock Specifications
I/O
Input
Capacitance
Input Duty
Cycle
Requirement
Maximum
Frequency
Jitter
Tolerance
LVTTL
9pF
40%
100
150ps
IDT
PLL
Clock Device
IDT
Non-PLL Clock
Device
2305
2308
2309
49FCT3805
49FCT3805D/E
74FCT3807
74FCT3807D/E
3743 tbl 13
Orderable Part Information
Speed
(ns)
7
Pkg.
Code
Pkg.
Type
Temp.
Grade
Speed
(ns)
70V9279L7PRFG
PKG128
TQFP
C
9
70V9279L7PRFG8
PKG128
TQFP
C
Orderable Part ID
70V9279L7PRFGI
PKG128
TQFP
I
70V9279L7PRFGI8
PKG128
TQFP
I
6.42
18
Pkg.
Code
Pkg.
Type
Temp.
Grade
70V9269L9PRFG
PKG128
TQFP
C
70V9269L9PRFG8
PKG128
TQFP
C
Orderable Part ID
70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Datasheet Document History
01/12/99:
06/15/99:
09/29/99:
11/10/99:
03/31/00:
01/017/01:
Page 14
Page 4
Page 7
Page 4
Page 5
02/25/04:
Page 2
Page 3
Page 4
Page 5
Page 7
Page 18
05/04/04:
10/11/04:
01/19/06:
10/23/08:
06/25/18:
08/06/19:
Page 1 & 19
Page 1 & 18
Page 5
Page 8
Page 4
Page 5
Page 8
Page 12
Page 18
Page 1
Page 18
Page18
Page 1 & 18
Page 2
Page 18
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Added additional notes to pin configurations
Added Depth & Width Expansion section
Deleted note 6 for Table II
Corrected typo in heading
Replaced IDT logo
Combined Pipelined 70V9279/69 family and Flow-through 70V927 family offerings into one data sheet
Changed ±200mV in waveform notes to 0mV
Added corresponding part chart with ordering information
Changed information in Truth Table II
Increased storage temperature parameters
Clarified TA parameter
DC Electrical parameters–changed wording from "open" to "disabled"
Removed Preliminary status
Consolidated multiple devices into one datasheet
Changed naming conventions from VCC to VDD and from GND to Vss
Added date revision for pin configuration
Added footnotes for UB, LB, CE0 and CE1 buffer conditions when FT or PIPE
Added junction temperature to Absolute Maximum Ratings Table
Added Ambient Temperature footnote
Added I-temp numbers for 9ns speed to DC Electrical Characteristics Table
Added 6ns speed DC power numbers to the DC Electrical Characteristics Table
Added I-temp for 9ns speed to AC Electrical CharacteristicsTable
Added 6ns speed AC timing numbers to the AC Electrical Characteristics Table
Added 6ns speed grade and 9ns I-temp to ordering information
Added IDT Clock Solution Table
Updated IDT logo, replaced IDTTM logo with IDT® logo
Added 7ns speed grade to ordering information
Added 7ns speed DC power numbers to the DC Electrical Characteristics Table
Added 7ns speed AC timing numbers to the AC Electrical Characteristics Table
Updated Capacitance table
Added 7ns I-temp and removed 9ns I-temp DC power numbers from the DC Electrical Characteristics table
Added 7ns I-temp and removed 9ns I-temp from the AC Electrical Characteristics table
Added Timing Waveform of Left Port Write to Pipelined Right Port Read
Added 7ns I-temp and removed 9ns I-temp from ordering information
Added green availability to features
Added green indicator to ordering information
Removed "IDT" from orderable part number
Added Tape & Reel to Ordering Information
Product Discontinuation Notice - PDN# SP-17-02
Last time buy expires June 15, 2018
Deleted obsolete Commercial speed grades 6/12/15ns
Updated package code PK-128 to PKG128
Added Orderable Part Information table
CORPORATE HEADQUARTERS
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for SALES:
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The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
19
for Tech Support:
408-284-2794
DualPortHelp@idt.com
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