7132SA/LA
7142SA/LA
HIGH SPEED
2K x 8 DUAL PORT
STATIC RAM
Features
◆
◆
◆
High-speed access
– Commercial: 20/35/55/100ns (max.)
– Industrial: 25/55ns (max.)
– Military: 25/35/55/100ns (max.)
Low-power operation
– IDT7132/42SA
Active: 325mW (typ.)
Standby: 5mW (typ.)
– IDT7132/42LA
Active: 325mW (typ.)
Standby: 1mW (typ.)
◆
◆
◆
◆
◆
◆
◆
◆
MASTER IDT7132 easily expands data bus width to 16-or-more
bits using SLAVE IDT7142
On-chip port arbitration logic (IDT7132 only)
BUSY output flag on IDT7132; BUSY input on IDT7142
Battery backup operation —2V data retention (LA only)
TTL-compatible, single 5V ±10% power supply
Available in 48-pin DIP, LCC and Flatpack, and 52-pin PLCC
packages
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available for
selected speeds
Green parts available, see ordering information
Functional Block Diagram
OEL
OER
CEL
R/WL
CER
R/WR
I/OOL-I/O7L
I/O
Control
I/OOR-I/O7R
I/O
Control
m
BUSYL(1,2)
A10L
A0L
BUSYR(1,2)
Address
Decoder
MEMORY
ARRAY
11
CEL
OEL
R/WL
A10R
Address
Decoder
A0R
11
ARBITRATION
LOGIC
CER
OER
R/WR
2692 drw 01
NOTES:
1. IDT7132 (MASTER): BUSY is open drain output and requires pullup resistor of 270Ω.
IDT7142 (SLAVE): BUSY is input.
2. Open drain output: requires pullup resistor of 270Ω.
1
May.27.21
7132SA/LA and 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Description
The IDT7132/IDT7142 are high-speed 2K x 8 Dual-Port Static RAMs.
The IDT7132 is designed to be used as a stand-alone 8-bit Dual-Port RAM
or as a “MASTER” Dual-Port RAM together with the IDT7142 “SLAVE”
Dual-Port in 16-bit-or-more word width systems. Using the IDT MASTER/
SLAVE Dual-Port RAM approach in 16-or-more-bit memory system
applications results in full-speed, error-free operation without the need for
additional discrete logic.
Both devices provide two independent ports with separate control,
address, and l/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature, controlled by CE permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using CMOS high-performance technology, these
devices typically operate on only 325mW of power. Low-power (LA)
versions offer battery backup data retention capability, with each DualPort typically consuming 200µW from a 2V battery.
The IDT7132/7142 devices are packaged in a 48-pin sidebraze or
plastic DIPs, 48-pin LCCs, 52-pin PLCCs, and 48-lead flatpacks.
Military grade product is manufactured in compliance with the latest
revision of MIL-PRF-38535 QML, making it ideally suited to military
temperature applications demanding the highest level of performance
and reliability.
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
I/O7R
I/O6R
Pin Configurations(1,2,3)
1
48-Pin Flatpack
Top View
27
26
25
24
23
22
21
4
20
5
19
6
7 8 9 10 11 12 13 14 15 16 17 18
2
3
2692 drw 03F
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
GND
I/O0R
I/O1R
I/O2R
I/O3R
2
May.27.21
18 17 16 15 14 13 12 11 10 9 8 7
6
19
20
5
4
21
22
3
7132/42
23
2
LC48(4)
1
24
48-Pin LCC
48
25
Top View
26
47
46
27
45
28
44
29
43
30
31 32 33 34 35 36 37 38 39 40 41 42
I/O6R
NOTES:
1. All VCC pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. LC48 package body is approximately .57 in x .57 in x .68 in.
FP48 package body is approximately .75 in x .75 in x .11 in.
4. This package code is used to reference the package diagram.
I/O4R
I/O5R
A5L
A4L
A3L
A2L
A1L
INDEX
7132/42
FP48(4)
I/O5R
I/O4R
I/O3R
I/O2R
I/O1R
I/O0R
GND
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
A3R
A2R
A1R
A0R
OEL
A0L
29
28
I/O2L
I/O1L
I/O0L
A9L
A8L
A7L
A6L
R/WL
BUSYL
A10L
44
45
46
47
48
I/O7R
A9R
A8R
A7R
A6R
A5R
A4R
R/WR
CER
VCC
CEL
42 41 40 39 38 37 36 35 34 33 32 31
43
30
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
OER
A10R
BUSYR
A0L
OEL
A10L
BUSYL
R/WL
CEL
VCC
CER
R/WR
BUSYR
A10R
OER
2692 drw 03L
7132SA/LA and 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
CEL
R/WL
BUSYL
A10L
OEL
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
GND
1
48
2
47
46
3
7132 45
4
7142
44
5
43
6
7 PDG48(4) 42
41
8
or
9 SB48(4) 40
39
10
38
11
37
12 48-Pin
DIP
13 Top 36
14 View(5) 35
34
15
33
16
32
17
31
18
30
19
29
20
28
21
27
22
26
23
25
24
VCC
CER
R/WR
BUSYR
A10R
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
I/O7R
I/O6R
I/O5R
I/O4R
I/O3R
I/O2R
I/O1R
I/O0R
NOTES:
1. All VCC pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. PDG48 package body is approximately .55 in x 2.43 in x .18 in.
SB48 package body is approximately .62 in x 2.43 in x .15 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
,
I/O3L
I/O2L
I/O1L
I/O0L
A9L
A8L
A7L
A6L
A5L
A4L
A3L
A2L
A1L
2692 drw 02a
I/O4L
I/O5L
I/O6L
I/O7L
N/C
GND
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
20 19 18 17 16 15 14 13 12 11 10 9 8
21
7
6
22
23
5
4
24
3
25
7132/42
2
26
PLG52(4)
1
27
52-Pin PLCC
Top View
52
28
51
29
30
50
49
31
32
48
33
47
34 35 36 37 38 39 40 41 42 43 44 45 46
A0L
OEL
A10L
N/C
BUSYL
R/WL
CEL
VCC
CER
R/WR
BUSYR
N/C
A10R
NOTES:
1. All VCC pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. PLG52 package body is approximately .75 in x .75 in x .17 in.
4. This package code is used to reference the package diagram.
3
6.42
May.27.21
A0R
OER
A6R
A5R
A4R
A3R
A2R
A1R
I/O7R
N/C
A9R
A8R
A7R
2692 drw 04a
7132SA/LA and 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Recommended DC Operating
Recommended Operating
(1,2) Conditions
Temperature and Supply Voltage
Grade
Military
Commercial
Industrial
Symbol
Ambient
Temperature
GND
Vcc
-55OC to+125OC
0V
5.0V + 10%
0OC to +70OC
0V
5.0V + 10%
-40OC to +85OC
0V
5.0V + 10%
Parameter
VCC
Supply Voltage
GND
Ground
VIH
Input High Voltage
VIL
Input Low Voltage
Min.
Typ.
Max.
Unit
4.5
5.0
5.5
V
0
0
0
V
2.2
____
(1)
-0.5
____
(2)
6.0
0.8
V
V
2692 tbl 02
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
NOTES:
1. VIL (min.) = -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
Absolute Maximum Ratings(1)
Capacitance(1) (TA = +25°C,f = 1.0MHz)
Commercial
& Industrial
Military
Unit
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
-0.5 to +7.0
V
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
o
C
TSTG
Storage
Temperature
-65 to +150
-65 to +150
o
C
IOUT
DC Output
Current
50
50
Symbol
VTERM(2)
Rating
Symbol
CIN
Input Capacitance
COUT
Output Capacitance
Conditions(2)
Max.
Unit
VIN = 3dV
11
pF
VOUT = 3dV
11
pF
2692 tbl 00
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV represents the interpolated capacitance when the input and output signals
switch from 3V to 0V.
mA
2692 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of the specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
4
May.27.21
Parameter
2692 tbl 03
7132SA/LA and 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,5,8) (VCC = 5.0V ± 10%)
7132X20(2)
7142X20(2)
Com'l Only
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Dynamic Operating Current
(Both Ports Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby Current (Both
Ports - All
CMOS Level Inputs)
Full Standby Current
(One Port - All
CMOS Level Inputs)
Test Condition
Version
CEL = CER = VIL,
Outputs Disabled
f = fMAX(3)
CEL = CER = VIH,
f = fMAX(3)
CE"A" = VIL and CE"B" = VIH(6)
Active Port Outputs Disabled
f=fMAX(3)
CEL and CER > VCC -0.2V
VIN > VCC -0.2V or VIN < 0.2V, f = 0(4)
CE"A" < 0.2V andCE"B" > VCC -0.2V(6)
VIN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled
f = fMAX(3)
7132X25(7)
7142X25(7)
Com'l, Ind
& Military
7132X35
7142X35
Com'l &
Military
Typ.
Max.
Typ.
Max.
Typ.
Max.
Unit
mA
COM'L
SA
LA
110
110
250
200
110
110
220
170
80
80
165
120
MIL &
IND
SA
LA
____
____
____
____
110
110
280
220
80
80
230
170
COM'L
SA
LA
30
30
65
45
30
30
65
45
25
25
65
45
MIL &
IND
SA
LA
____
____
____
____
30
30
80
60
25
25
80
60
COM'L
SA
LA
65
65
165
125
65
65
150
115
50
50
125
90
MIL &
IND
SA
LA
____
____
____
____
65
65
160
125
50
50
150
115
COM'L
SA
LA
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
4
MIL &
IND
SA
LA
____
____
____
____
1.0
0.2
30
10
1.0
0.2
30
10
COM'L
SA
LA
60
60
155
115
60
60
145
105
45
45
110
85
MIL &
IND
SA
LA
____
____
____
____
60
60
155
115
45
45
145
105
mA
mA
mA
mA
2692 tbl 04a
7132X55
7142X55
Com'l &
Military
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Test Condition
Version
7132X100
7142X100
Com'l &
Military
Typ.
Max.
Typ.
Max.
Unit
Dynamic Operating
Current
(Both Ports Active)
CEL = CER = VIL,
Outputs Disabled
f = fMAX(3)
COM'L
SA
LA
65
65
155
110
65
65
155
110
mA
MIL &
IND
SA
LA
65
65
190
140
65
65
190
140
Standby Current
(Both Ports - TTL
Level Inputs)
CEL = CER = VIH,
f = fMAX(3)
COM'L
SA
LA
20
20
65
35
20
20
55
35
MIL &
IND
SA
LA
20
20
65
45
20
20
65
45
Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and CE"B" = VIH(6)
Active Port Outputs Disabled
f=fMAX(3)
COM'L
SA
LA
40
40
110
75
40
40
110
75
MIL &
IND
SA
LA
40
40
125
90
40
40
125
90
Full Standby Current
(Both Ports - All
CMOS Level Inputs)
CEL and CER > VCC -0.2V
VIN > VCC -0.2V or VIN < 0.2V, f = 0(4)
COM'L
SA
LA
1.0
0.2
15
4
1.0
0.2
15
4
MIL &
IND
SA
LA
1.0
0.2
30
10
1.0
0.2
30
10
Full Standby Current
(One Port - All
CMOS Level Inputs)
CE"A" < 0.2V and CE"B" > VCC -0.2V(6)
VIN > VCC - 0.2V or V IN < 0.2V
Active Port Outputs Disabled
f = fMAX(3)
COM'L
SA
LA
40
40
100
70
40
40
95
70
MIL &
IND
SA
LA
40
40
110
85
40
40
110
80
mA
mA
mA
mA
2692 tbl 04b
NOTES:
1. 'X' in part numbers indicates power rating (SA or LA).
2. PLCC Package only
3. At f = fMax, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS” of input levels
of GND to 3V.
4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
5. Vcc = 5V, TA=+25°C for Typ and is not production tested. Vcc DC = 100mA (Typ)
6. Port "A" may be either left or right port. Port "B" is opposite from port "A".
7. Not available in DIP packages.
8. Industrial temperature: for specific speeds, packages and powers contact your sales office.
5
6.42
May.27.21
7132SA/LA and 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range (VCC = 5.0V ± 10%)
7132SA
7142SA
Symbol
Parameter
Test Conditions
(1)
7132LA
7142LA
Min.
Max.
Min.
Max.
Unit
µA
|ILI|
Input Leakage Current
VCC = 5.5V,
VIN = 0V to VCC
___
10
___
5
|ILO|
Output Leakage Current
VCC = 5.5V,
CE = VIH, VOUT = 0V to VCC
___
10
___
5
VOL
Output Low Voltage
IOL = 4mA
___
0.4
___
0.4
VOL
Open Drain Output
Low Voltage (BUSY)
IOL = 16mA
___
0.5
___
0.5
VOH
Output High Voltage
IOH = -4mA
2.4
___
2.4
___
µA
V
V
V
2692 tbl 05
NOTE:
1. At Vcc < 2.0V leakages are undefined.
Data Retention Characteristics (LA Version Only)
Symbol
Parameter
Test Condition
Min.
Typ.(1)
Max.
Unit
2.0
___
___
V
VDR
VCC for Data Retention
VCC = 2.0V
ICCDR
Data Retention Current
CE > VCC -0.2V
Mil. & Ind.
___
100
4000
µA
VIN > VCC -0.2V or
Com'l.
___
100
1500
µA
0
___
___
ns
tRC(2)
___
___
ns
tCDR(3)
Chip Deselect to Data Retention Time
tR(3)
Operation Recovery Time
VIN < 0.2V
2692 tbl 06
NOTES:
1. VCC = 2V, TA = +25°C, and is not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed but not production tested.
Data Retention Waveform
DATA RETENTION MODE
VCC
4.5V
VDR ≥ 2.0V
tCDR
4.5V
tR
VDR
CE
VIH
VIH
,
2692 drw 05
6
May.27.21
7132SA/LA and 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns Max.
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
Figures 1, 2, and 3
2692 tbl 07
5V
5V
1250Ω
1250Ω
DATAOUT
DATAOUT
775Ω
30pF*
775Ω
5pF*
*100pF for 55 and 100ns versions
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for tHZ, tLZ, tWZ, and tOW)
* Including scope and jig
5V
270Ω
BUSY
30pF*
*100pF for 55 and 100ns versions
Figure 3. BUSY AC Output Test Load
7
6.42
May.27.21
2692 drw 06
,
7132SA/LA and 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(3,5)
7132X20(2)
7142X20(2)
Com'l Only
Symbol
Parameter
7132X25(2)
7142X25(2)
Com'l, Ind
& Military
7132X35
7142X35
Com'l &
Military
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
20
____
25
____
35
____
ns
tAA
Address Access Time
____
20
____
25
____
35
ns
tACE
Chip Enable Access Time
____
20
____
25
____
35
ns
tAOE
Output Enable Access Time
____
11
____
12
____
20
ns
tOH
Output Hold from Address Change
3
____
3
____
3
____
ns
tLZ
Output Low-Z Time (1,4)
0
____
0
____
0
____
ns
tHZ
(1,4)
____
10
____
10
____
15
ns
0
____
0
____
0
____
ns
____
20
____
25
____
35
ns
tPU
tPD
Output High-Z Time
Chip Enable to Power Up Time
(4)
Chip Disable to Power Down Time
(4)
2692 tbl 08a
7132X55
7142X55
Com'l &
Military
Symbol
Parameter
7132X100
7142X100
Com'l &
Military
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
55
____
100
____
ns
tAA
Address Access Time
____
55
____
100
ns
tACE
Chip Enable Access Time
____
55
____
100
ns
tAOE
Output Enable Access Time
____
25
____
40
ns
tOH
Output Hold from Address Change
3
____
10
____
ns
tLZ
Output Low-Z Time (1,4)
5
____
5
____
ns
tHZ
(1,4)
____
25
____
40
ns
0
____
0
____
ns
____
50
____
50
ns
Output High-Z Time
(4)
tPU
Chip Enable to Power Up Time
tPD
Chip Disable to Power Down Time (4)
NOTES:
1. Transition is measured 0mV from Low or High-Impedance Voltage Output Test Load (Figure 2).
2. PLCC package only.
3. 'X' in part numbers indicates power rating (SA or LA).
4. This parameter is guaranteed by device characterization, but is not production tested.
5. Industrial temperature: for specific speeds, packages and powers contact your sales office.
8
May.27.21
2692 tbl 08b
7132SA/LA and 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side(1)
tRC
ADDRESS
tAA
tOH
tOH
DATAOUT
PREVIOUS DATA VALID
DATA VALID
BUSYOUT
2692 drw 07
tBDDH(2,3)
Timing Waveform of Read Cycle No. 2, Either Side(1)
tACE
CE
tAOE(3)
tHZ(5)
OE
tHZ(5)
tLZ(4)
VALID DATA
DATAOUT
tLZ(4)
ICC
CURRENT
ISS
tPD(3)
tPU
50%
50%
2692 drw 08
NOTES:
1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW.
2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations, BUSY has
no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
4. Timing depends on which signal is asserted last, OE or CE.
5. Timing depends on which signal is de-asserted first, OE or CE.
9
6.42
May.27.21
7132SA/LA and 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range(5,6)
7132X20(2)
7142X20(2)
Com'l Only
Symbol
Parameter
7132X25(2)
7142X25(2)
Com'l, Ind
& Military
7132X35
7142X35
Com'l &
Military
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
tWC
Write Cycle Time (3)
20
____
25
____
35
____
ns
tEW
Chip Enable to End-of-Write
15
____
20
____
30
____
ns
tAW
Address Valid to End-of-Write
15
____
20
____
30
____
ns
tAS
Address Set-up Time
0
____
0
____
0
____
ns
tWP
Write Pulse Width(4)
15
____
15
____
25
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
ns
tDW
Data Valid to End-of-Write
10
____
12
____
15
____
ns
____
10
____
10
____
15
ns
0
____
0
____
0
____
ns
____
10
____
10
____
15
ns
0
____
0
____
0
____
ns
tHZ
Output High-Z Time
tDH
Data Hold Time
tWZ
tOW
(1)
(1)
Write Enable to Output in High-Z
Output Active from End-of-Write
(1)
2692 tbl 09
7132X55
7142X55
Com'l &
Military
Symbol
Parameter
7132X100
7142X100
Com'l &
Military
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
tWC
Write Cycle Time (3)
55
____
100
____
ns
tEW
Chip Enable to End-of-Write
40
____
90
____
ns
tAW
Address Valid to End-of-Write
40
____
90
____
ns
tAS
Address Set-up Time
0
____
0
____
ns
ns
(4)
tWP
Write Pulse Width
30
____
55
____
tWR
Write Recovery Time
0
____
0
____
ns
tDW
Data Valid to End-of-Write
20
____
40
____
ns
tHZ
Output High-Z Time (1)
____
25
____
40
ns
tDH
Data Hold Time
0
____
0
____
ns
tWZ
Write Enable to Output in High-Z(1)
____
30
____
40
ns
0
____
0
____
tOW
Output Active from End-of-Write
(1)
ns
2692 tbl 10
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by device characterization
but is not production tested.
2. PLCC package only.
3. For Master/Slave combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA.
4. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the
bus for the required tDW. If OE is High during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
5. 'X' in part numbers indicates power rating (SA or LA).
6. Industrial temperature: for specific speeds, packages and powers contact your sales office.
10
May.27.21
7132SA/LA and 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing)(1,5,8)
tWC
ADDRESS
tHZ(7)
OE
tAW
CE
tAS(6)
tWR(3)
tWP(2)
tHZ(7)
R/W
tWZ(7)
tOW
(4)
DATA OUT
(4)
tDW
tDH
DATA IN
2692 drw 09
Timing Waveform of Write Cycle No. 2, (CE Controlled Timing)(1,5)
tWC
ADDRESS
tAW
CE
tAS(6)
tWR(3)
tEW(2)
R/W
tDW
tDH
DATA IN
2692 drw 10
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W = VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the
bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
11
6.42
May.27.21
7132SA/LA and 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(7,8)
7132X20(1)
7142X20(1)
Com'l Only
Symbol
Parameter
7132X25(2)
7142X25(2)
Com'l, Ind
& Military
7132X35
7142X35
Com'l &
Military
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY Timing (For Master IDT7132 Only)
tBAA
BUSY Access Time from Address
____
20
____
20
____
20
ns
tBDA
BUSY Disable Time from Address
____
20
____
20
____
20
ns
BUSY Access Time from Chip Enable
____
20
____
20
____
20
ns
tBDC
BUSY Disable Time from Chip Enable
____
20
____
20
____
20
ns
tWDD
Write Pulse to Data Delay (2)
____
50
____
50
____
60
ns
12
____
15
____
20
____
ns
____
35
____
35
____
35
ns
5
____
5
____
5
____
ns
____
25
____
35
____
35
ns
0
____
0
____
0
____
ns
ns
ns
tBAC
tWH
Write Hold After BUSY
(6)
tDDD
Write Data Valid to Read Data Delay
tAPS
Arbitration Priority Set-up Time (3)
tBDD
BUSY Disable to Valid Data
(2)
(4)
BUSY Timing (For Slave IDT7142 Only)
Write to BUSY Input(5)
tWB
(6)
tWH
Write Hold After BUSY
12
____
15
____
20
____
tWDD
Write Pulse to Data Delay (2)
____
40
____
50
____
60
tDDD
Write Data Valid to Read Data Delay (2)
____
30
____
35
____
35
ns
2692 tbl 11a
7132X55
7142X55
Com'l &
Military
Symbol
Parameter
7132X100
7142X100
Com'l &
Military
Min.
Max.
Min.
Max.
Unit
BUSY Access Time from Address
____
30
____
50
ns
BUSY Disable Time from Address
____
30
____
50
ns
BUSY Access Time from Chip Enable
____
30
____
50
ns
BUSY Disable Time from Chip Enable
____
30
____
50
ns
____
80
____
120
ns
ns
BUSY Timing (For Master IDT7132 Only)
tBAA
tBDA
tBAC
tBDC
tWDD
Write Pulse to Data Delay
(2)
(6)
tWH
Write Hold After BUSY
20
____
20
____
tDDD
Write Data Valid to Read Data Delay (2)
____
55
____
100
ns
tAPS
Arbitration Priority Set-up Time (3)
5
____
5
____
ns
____
50
____
65
ns
tBDD
(4)
BUSY Disable to Valid Data
BUSY Timing (For Slave IDT7142 Only)
tWB
Write to BUSY Input(5)
0
____
0
____
ns
tWH
Write Hold After BUSY(6)
20
____
20
____
ns
____
80
____
120
ns
____
55
____
100
tWDD
tDDD
Write Pulse to Data Delay
(2)
Write Data Valid to Read Data Delay
(2)
NOTES:
1. PLCC package only.
2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port -to-Port Read and BUSY.”
3. To ensure that the earlier of the two ports wins.
4. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
5. To ensure that a write cycle is inhibited on port "B" during contention on port "A".
6. To ensure that a write cycle is completed on port "B" after contention on port "A".
7. 'X' in part numbers indicates power rating (SA or LA).
8. Industrial temperature: for specific speeds, packages and powers contact your sales office.
12
May.27.21
ns
2692 tbl 11b
7132SA/LA and 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY(2,3,4)
tWC
ADDR"A"
MATCH
tWP
R/W"A"
tDW
DATAIN"A"
tDH
VALID
(1)
tAPS
MATCH
ADDR"B"
tBDD
t BDA
tBAA
BUSY"B"
tWDD
DATAOUT"B"
VALID
tDDD
2692 drw 11
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (IDT7142).
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".
Timing Waveform of Write with BUSY(4)
tWP
R/W"A"
tWB(3)
BUSY"B"
tWH(1)
R/W"B"
,
(2)
2692 drw 12
NOTES:
1. tWH must be met for both BUSY Input (IDT7142, slave) or Output (IDT7132, master).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB applies only to the slave version (IDT7142).
4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
13
6.42
May.27.21
7132SA/LA and 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)
ADDR
"A"
ADDRESSES MATCH
and "B"
CE"B"
tAPS(2)
CE"A"
tBAC
tBDC
BUSY"A"
2692 drw 13
Timing Waveform of BUSY Arbitration Controlled
by Address Match Timing(1)
tRC or tWC
ADDR"A"
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
(2)
tAPS
ADDR"B"
tBAA
tBDA
BUSY"B"
2692 drw 14
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If tAPS is not satisfied, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (7132 only).
Truth Tables
Table I. Non-Contention Read/Write Control(4)
Left or Right Port(1)
R/W
CE
OE
D0-7
Function
X
H
X
Z
Port Disabled and in Power-Down Mode, ISB2 or ISB4
X
H
X
Z
CER = CEL = VIH, Power-Down Mode, ISB1 or ISB3
L
L
X
DATAIN
H
L
L
DATAOUT
X
L
H
Z
Data on Port Written into Memory (2)
Data in Memory Output on Port(3)
High Impedance Outputs
2692 tbl 12
NOTES:
1. A0L - A10L ≠ A0R - A10R
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
14
May.27.21
7132SA/LA and 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Table II — Address BUSY
Arbitration
Outputs
CEL
CER
AOL-A10L
AOR-A10R
BUSYL(1)
BUSYR(1)
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit(3)
Function
Width Expansion with Busy Logic
Master/Slave Arrays
2692 tbl 13
NOTES:
1. Pins BUSYL and BUSYR are both outputs for IDT7132 (master). Both are inputs for
IDT7142 (slave). BUSYX outputs on the IDT7132 are open drain, not push-pull
outputs. On slaves the BUSYX input internally inhibits writes.
2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs
of this port. 'H' if the inputs to the opposite port became stable after the address and
enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will
result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW
regardless of actual logic level on the pin. Writes to the right port are internally
ignored when BUSYR outputs are driving LOW regardless of actual logic level on
the pin.
When expanding an SRAM array in width while using BUSY logic, one
master part is used to decide which side of the SRAM array will receive
a BUSY indication, and to output that indication. Any number of slaves to
be addressed in the same address range as the master, use the BUSY
signal as a write inhibit signal. Thus on the IDT7132/IDT7142 SRAMs the
BUSY pin is an output if the part is Master (IDT7132), and the BUSY pin
is an input if the part is a Slave (IDT7142) as shown in Figure 3.
5V
270Ω
MASTER
Dual Port
SRAM
BUSYL
Functional Description
The IDT7132/IDT7142 provides two ports with separate control,
address and I/O pins that permit independent access for reads or
writes to any location in memory. The IDT7132/IDT7142 has an
automatic power down feature controlled by CE. The CE controls onchip power down circuitry that permits the respective port to go into a
standby mode when not selected (CE = VIH). When a port is enabled,
access to the entire memory array is permitted.
Busy Logic
Busy Logic provides a hardware indication that both ports of the
RAM have accessed the same location at the same time. It also allows
one of the two accesses to proceed and signals the other side that the
RAM is “Busy”. The BUSY pin can then be used to stall the access until
the operation on the other side is completed. If a write operation has
been attempted from the side that receives a busy indication, the write
signal is gated internally to prevent the write from proceeding.
The use of BUSY Logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs
together and use any BUSY indication as an interrupt source to flag the
event of an illegal or illogical operation.
BUSYL
CE
BUSYR
CE
BUSYR
SLAVE
Dual Port
SRAM
BUSYL
SLAVE
Dual Port
SRAM
BUSYL
CE
BUSYR
5V
270Ω
CE
BUSYR
BUSYR
2692 drw 15
Figure 4. Busy and chip enable routing for both width and depth
expansion with IDT7132 (Master) and (Slave) IDT7142 SRAMs.
If two or more master parts were used when expanding in width, a
split decision could result with one master indicating BUSY on one side
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
The BUSY arbitration, on a Master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with either the R/W signal or the byte
enables. Failure to observe this timing can result in a glitched internal
write inhibit signal and corrupted data in the slave.
15
6.42
May.27.21
MASTER
Dual Port
SRAM
BUSYL
DECODER
Inputs
The BUSY outputs on the IDT7132 RAM master are open drain type
outputs and require open drain resistors to operate. If these RAMs are
being expanded in depth, then the BUSY indication for the resulting array
does not require the use of an external AND gate.
7132SA/LA and 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Ordering Information
XXXX
Device
Type
999
A
A
Power Speed Package
A
A
Process/
Temperature
Range
A
Blank
8
Tube
Tape and Reel
Blank
I(1)
B
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Military (-55°C to +125°C)
Compliant to MIL-PRF-38535 QML
G(2)
Green
P
C
J
L
F
48-pin Plastic DIP (PDG48)
48-pin Sidebraze DIP (SB48)
52-pin PLCC (PLG52)
48-pin LCC (LC48)
48-pin Ceramic Flatpack (FP48)
20
25
35
55
100
Commercial Only
Industrial & Military
Commercial & Military
Commercial, Industrial & Military
Commercial & Military
LA
SA
Low Power
Standard Power
7132
7142
16K (2K x 8-Bit) MASTER Dual-Port RAM
16K (2K x 8-Bit) SLAVE Dual-Port RAM
Speed in nanoseconds
2692 drw 16
NOTES:
1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office.
2. Green parts available. For specific speeds, packages and powers contact your local sales office.
LEAD FINISH (SnPb) parts are Obsolete excluding FP48, LC48 & SB48. Product Discontinuation Notice - PDN# SP-17-02
Note that information regarding recently obsoleted parts are included in this datasheet for customer convenience.
16
May.27.21
7132SA/LA and 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Orderable Part Information
Speed
(ns)
Orderable Part ID
Pkg.
Code
Pkg.
Type
Temp.
Grade
Speed
(ns)
Orderable Part ID
Pkg.
Code
Pkg.
Type
Temp.
Grade
20
7132LA20JG
PLG52
PLCC
C
25
7132SA25L48B
LC48
LCC
M
7132LA20JG8
PLG52
PLCC
C
35
7132SA35C
SB48
SB
C
25
7132LA25JGI
PLG52
PLCC
I
7132SA35CB
SB48
SB
M
7132LA25JGI8
PLG52
PLCC
I
7132SA35JG
PLG52
PLCC
C
7132SA35JG8
PLG52
PLCC
C
35
55
100
7132LA25L48B
LC48
LCC
M
7132LA35C
SB48
SB
C
7132LA35CB
SB48
SB
M
7132LA35FB
FP48
FPACK
7132LA35L48B
LC48
LCC
7132LA35PDG
PDG48
PDIP
C
7132SA55L48B
7132LA55C
SB48
SB
C
7132LA55CB
SB48
SB
M
7132LA55FB
FP48
FPACK
M
7132SA35L48B
LC48
LCC
M
7132SA55C
SB48
SB
C
M
7132SA55CB
SB48
SB
M
M
7132SA55JG
PLG52
PLCC
C
LC48
LCC
M
7132SA100C
SB48
SB
C
7132SA100CB
SB48
SB
M
7132SA100L48B
LC48
LCC
M
7132LA55L48B
LC48
LCC
M
7132LA55PDGI
PDG48
PDIP
I
7132LA100C
SB48
SB
C
7132LA100CB
SB48
SB
M
7132LA100L48B
LC48
LCC
M
7132LA100PDG
PDG48
PDIP
C
55
100
17
6.42
May.27.21
7132SA/LA and 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Orderable Part Information (con't)
Speed
(ns)
20
25
35
55
100
Pkg.
Code
Pkg.
Type
Temp.
Grade
Speed
(ns)
7142LA20JG
PLG52
PLCC
C
35
7142LA20JG8
PLG52
PLCC
C
7142LA25JGI
PLG52
PLCC
I
7142LA25JGI8
PLG52
PLCC
I
7142LA35C
SB48
SB
C
7142LA35CB
SB48
SB
M
7142LA35L48B
LC48
LCC
M
7142LA35PDG
PDG48
PDIP
C
7142LA55C
SB48
SB
C
7142LA55CB
SB48
SB
M
Orderable Part ID
7142LA55L48B
LC48
LCC
M
7142LA100C
SB48
SB
C
7142LA100CB
SB48
SB
M
7142LA100L48B
LC48
LCC
M
7142LA100PDG
PDG48
PDIP
C
55
100
Pkg.
Code
Pkg.
Type
Temp.
Grade
7142SA35C
SB48
SB
C
7142SA35CB
SB48
SB
M
7142SA35L48B
LC48
LCC
M
7142SA55C
SB48
SB
C
7142SA55CB
SB48
SB
M
7142SA55L48B
LC48
LCC
M
7142SA100C
SB48
SB
C
7142SA100CB
SB48
SB
M
7142SA100L48B
LC48
LCC
M
Orderable Part ID
Datasheet Document History
03/24/99:
Pages 2 and 3
06/08/99:
08/26/99:
11/10/99:
01/12/00:
Page 14
Pages 1 and 2
Page 1
Page 2
Page 3
Page 4
Page 6
Page 14
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Added additional notes to pin configurations
Changed drawing format
Changed Busy Logic and Width Expansion copy
Replaced IDT logo
Moved full "Description" to page 2 and adjusted page layouts
Added "(LAonly)" to paragraph
Fixed P48-1 body package description
Increased storage temperature parameters
Clarified TA parameter
DC Electrical parameters–changed wording from "open" to "disabled"
Added asteriks to Figures 1 and 3 in drw 06
Corrected part numbers
Changed ±500mV to 0mV in notes
18
May.27.21
7132SA/LA and 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Datasheet Document History (con't)
06/11/04:
01/17/06:
10/21/08:
09/20/10:
10/03/14:
Page 6
Page 4, 7, 9,
11 & 15
Page 5
Page 6
Page 1
Page 15
Page 16
Page 15
Page 14
Page 2
Page 15
Page 2, 3 & 15
Page 15
10/08/14:
11/20/15:
Page 15
Page 15
07/03/18:
05/27/21:
Pages 1 - 20
Page 2, 3 & 16
Pages 17 & 18
Corrected errors in Figure 3 by changing 1250Ω to 270Ω and removing "or Int" and Int
Clarified Industrial temp offering for 25ns
Removed INT from VOL parameter in DC Electrical Characteristics table
Updated AC Test Conditions Input Rise/Fall Times from 5ns to 3ns
Added green availability to features
Added green indicator to ordering information
Replaced IDT address with new
Removed "IDT" from orderable part number
Corrected BUSY description to indicate open drain outputs
Removed IDT in reference to fabrication
Added Tape and Reel to Ordering Information
The package codes P48-1, C48-2, J52-1, L48-1 & F48-1 changed to P48, C48, J52,
L48 & F48 respectively to match standard package codes
Add annotation (3) to 25ns speed grade to indicate that 25ns is not available in DIP
packages
Corrected a typo
Added (4) footnote annotation to the "P" package in the Ordering Information.
Added footnote 4, For “P”, Plastic DIP, when ordering green package, the suffix is “PDG”.
Updated L package in the Ordering Information to L48
Product Discontinuation Notice - PDN# SP-17-02
Last time buy expires June 15, 2018
Rebranded as Renesas datasheet
Rotated LC48 LCC, FP48 Flatpack & PLG52 PLCC pin configurations to accurately reflect
pin 1 orientation and updated package codes
Added Orderable Part Information tables
19
6.42
May.27.21
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