72413L35SO8

IDT72413 OBSOLETE PART CMOS PARALLEL FIFO WITH FLAGS 64 x 5 FEATURES: DESCRIPTION: • First-ln/First-Out Dual-Port memory—45MHz • 64 x 5 organization • Low-power consumption — Active: 200mW (typical) • RAM-based internal structure allows for fast fall-through time • Asynchronous and simultaneous read and write • Expandable by bit width • Cascadable by word depth • Half-Full and Almost-Full/Empty status flags • High-speed data communications applications • Bidirectional and rate buffer applications • High-performance CMOS technology • Available in plastic DIP and SOIC • Green parts available, see ordering information The IDT72413 is a 64 x 5, high-speed First-In/First-Out (FIFO) that loads and empties data on a first-in-first-out basis. It is expandable in bit width. All speed versions are cascad-able in depth. The FIFO has a Half-Full Flag, which signals when it has 32 or more words in memory. The Almost-Full/Empty Flag is active when there are 56 or more words in memory or when there are 8 or less words in memory. This device is pin and functionally compatible to the MMI67413. It operates at a shift rate of 45MHz. This makes it ideal for use in high-speed data buffering applications. This FIFO can be used as a rate buffer, between two digital systems of varying data rates, in high-speed tape drivers, hard disk controllers, data communications controllers anD graphics controllers. The IDT72413 is fabricated using high-performance CMOS process. This process maintains the speed and high output drive capability of TTL circuits in low-power CMOS. R T O R F A P ED E D T S N E N E L G M O I S M S B E O O EC D R EW T N O N FUNCTIONAL BLOCK DIAGRAM OUPUT ENABLE (OE) DATA IN (D 0-4 ) FIFO INPUT STAGE 64 x 5 MEMORY ARRAY FIFO OUTPUT STAGE INPUT CONTROL LOGIC REGISTER CONTROL LOGIC OUTPUT CONTROL LOGIC DATA OUT (Q 0-4 ) (MR) MASTER RESET INPUT READY SHIFT IN (SO) (IR) (SI) (OR) FLAG CONTROL LOGIC SHIFT OUT OUPUT READY HALF-FULL (HF) ALMOST-FULL/ EMPTY (AF/E) 2748 drw 01 JUNE 2012 1 DSC-2748/11 IDT72413 CMOS PARALLEL FIFO WITH FLAGS 64 x 5 COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION OE HF IR SI D0 D1 D2 D3 D4 GND ABSOLUTE MAXIMUM RATINGS(1) 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 Symbol V TERM Vcc AF/E SO OR Q0 Q1 Q2 Q3 Q4 MR Rating Terminal Voltage with Respect to GND Storage Temperature DC Output Current T STG I OUT Commercial –0.5 to +7.0 Unit V –55 to +125 °C –50 to +50 mA NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2748 drw 02 RECOMMENDED OPERATING CONDITIONS PLASTIC DIP (P20-1, ORDER CODE: P) SOIC (SO20-2, ORDER CODE: SO) TOP VIEW Symbol CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol Parameter Conditions Max. CIN Input Capacitance V IN = 0V 5 C OUT Output Capacitance V OUT = 0V 7 NOTE: 1. Characterized values, not currently tested. Min. Typ. Max. Unit V CC Supply Voltage Commercial 4.5 5.0 5.5 V GND Supply Voltage 0 0 0 V V IH Input High Voltage 2.0 — — V Input Low Voltage — — 0.8 V Operating Temperature Commercial 0 — 70 °C Unit V IL pF TA pF Parameter (1) NOTE: 1. 1.5V undershoots are allowed for 10ns once per cycle. 2748 tbl 02 DC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C) Symbol I IL IIH VOL Parameter Low-Level Input Current High-Level Input Current Low-Level Output Current V OH High-Level Output Current I OS (2) I HZ ILZ ICC(3,4) Output Short-Circuit Current HIGH Impedance Output Current LOW Impedance Output Current Active Supply Current Test Conditions V CC = Max., GND ≤ V I ≤ V CC VCC = Max., GND ≤ VI ≤ VCC V CC = Min. I OL (Q 0-4 ) I OL (IR, OR) (1) I OL (HF, AF/E) V CC = Min. I OH (Q 0-4 ) I OH (IR, OR) I OH (HF, AF/E) V CC = Max. V O = 0V V CC = Max. V O = 2.4V V CC = Max. V O = 0.4V V CC = Max., OE = HIGH Inputs LOW, f = 25MHz 24 mA 8mA 8mA –4mA –4mA –4mA Min. –10 — — IDT72413 Commercial fIN = 45, 35, 25 MHz Max. — 10 0.4 2.4 — V –20 — –20 — –110 20 — 60 mA µA µA mA NOTES: 1. Care should be taken to minimize as much as possible the DC and capactive load on IR and OR when operating at frequencies above 25MHz. 2. Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second. Guaranteed by design, but not currently tested. 3. Tested with outputs open (IOUT = 0). 4. For frequencies greater than 25MHz, ICC = 60mA + (1.5mA x [f –25MHz]) 2 Unit µA µA V IDT72413 CMOS PARALLEL FIFO WITH FLAGS 64 x 5 COMMERCIAL TEMPERATURE RANGE OPERATING CONDITIONS (Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C) Symbol tSIH(1) t SIL(1) tIDS tIDH t SOH(1) t SOL tMRW tMRS Parameter Shift in HIGH Time Shift in LOW TIme Input Data Set-up Input Data Hold Time Shift Out HIGH Time Shift Out LOW Time Master Reset Pulse Master Reset Pulse to SI IDT72413L45 Min. Max. 9 — 11 — 0 — 13 — 9 — 11 — 20 — 20 — Figure 2 2 2 2 5 5 8 8 Commercial IDT72413L35 Min. Max. 9 — 17 — 0 — 15 — 9 — 17 — 30 — 35 — IDT72413L25 Min. Max. 16 — 20 — 0 — 25 — 16 — 20 — 35 — 35 — Unit ns ns ns ns ns ns ns ns NOTE: 1. Since the FIFO is a very high-speed device, care must be excercised in the design of the hardware and timing utilized within the design. Device grounding and decoupling are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor supply decoupling and grounding. A monolithic ceramic capacitor of 0.1µF directly between VCC and GND with very short lead length is recommended. AC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C) Commercial Symbol f IN tIRL(1) tIRH(1) f OUT t ORL(1) tORH(1) tODH(1) tODS t PT tMRORL tMRIRH(3) tMRIRL(2) tMRQ t MRHF t MRAFE tIPH(3) t OPH(3) tORD(3) tAEH t AEL t AFL t AFH tHFH t HFL t PHZ(3) t PLZ (3) t PLZ (3) t PHZ(3) Parameter Shift In Rate Shift In ↑ to Input Ready LOW Shift In ↓ to Input Ready HIGH Shift Out Rate Shift Out ↓ to Output Ready LOW Shift Out ↓ to Output Ready HIGH Output Data Hold Previous Word Output Data Shift Next Word Data Throughput or "Fall-Through" Master Reset ↓ to Output Ready LOW Master Reset ↑ to Input Ready HIGH Master Reset ↓ to Input Ready LOW Master Reset ↓ to Outputs LOW Master Reset ↓ to Half-Full Flag Master Reset ↓ to AF/E Flag Input Ready Pulse HIGH Output Ready Pulse HIGH Output Ready ↑ HIGH to Valid Data Shift Out ↑ to AF/E HIGH Shift In ↑ to AF/E Shift Out ↑ to AF/E LOW Shift In ↑ to AF/E HIGH Shift In ↑ to HF HIGH Shift Out ↑ to HF LOW Output Disable Delay Output Enable Delay IDT72413L45 Min. Max. — 45 — 18 — 18 — 45 — 18 — 19 5 — — 19 — 25 — 25 — 25 — 25 — 20 — 25 — 25 5 — 5 — — 5 — 28 — 28 — 28 — 28 — 28 — 28 — 12 — 12 — 15 — 15 Figure 2 2 2 5 5 5 5 5 4, 7 8 8 8 8 8 8 4 7 5 9 9 10 10 11 11 12 12 12 12 IDT72413L35 Min. Max. — 35 — 18 — 20 — 35 — 18 — 20 5 — — 20 — 28 — 28 — 28 — 28 — 25 — 28 — 28 5 — 5 — — 5 — 28 — 28 — 28 — 28 — 28 — 28 — 12 — 12 — 15 — 15 IDT72413L25 Min. Max. — 25 — 28 — 25 — 25 — 28 — 25 5 — — 20 — 40 — 30 — 30 — 30 — 35 — 40 — 40 5 — 5 — — 7 — 40 — 40 — 40 — 40 — 40 — 40 — 15 — 15 — 20 — 20 Unit MHz ns ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES: 1. Since the FIFO is a very high-speed device, care must be taken in the design of the hardware and the timing utilized within the design. Device grounding and decoupling are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor supply decoupling and grounding. A monolithic ceramic capacitor of 0.1µF directly between VCC and GND with very short lead length is recommended. 2. If the FIFO is full, (IR = HIGH), MR ↑ forces IR to go LOW, and MR ↓ causes IR to go HIGH. 3. Guaranteed by design but not currently tested. 3 IDT72413 CMOS PARALLEL FIFO WITH FLAGS 64 x 5 COMMERCIAL TEMPERATURE RANGE AC TEST CONDITIONS Input Pulse Levels STANDARD TEST LOAD GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load DESIGN TEST LOAD 5V 5V 2K‰ R1 TEST POINT OUTPUT See Figure 1 R2 2748 tbl 07 30pF* 30pF* 2748 drw 03 or equivalent circuit *Including scope and jig RESISTOR VALUES FOR STANDARD TEST LOAD IOL R1 R2 24mA 200Ω 300Ω 12mA 390Ω 760Ω 8mA 600Ω 1200Ω Figure 1. Output Load FUNCTIONAL DESCRIPTION: DATA OUTPUT Data is shifted out on the HIGH-to-LOW transition of Shift Out (SO). This causes the internal read pointer to be advanced to the next word location. If data is present, valid data will appear on the outputs and Output Ready (OR) will go HIGH. If data is not present, OR will stay LOW indicating the FIFO is empty. The last valid word read from the FIFO will remain at the FlFOs output when it is empty. When the FIFO is not empty OR goes LOW on the LOW-to-HlGH transition of SO. The IDT72413, 65 x 5 FIFO is designed using a dual-port RAM architecture as opposed to the traditional shift register approach. This FIFO architecture has a write pointer, a read pointer and control logic, which allow simultaneous read and write operations. The write pointer is incremented by the falling edge of the Shift In (Sl) control; the read pointer is incremented by the falling edge of the Shift Out (SO). The Input Ready (IR) signals when the FIFO has an available memory location; Output Ready (OR) signals when there is valid data on the output. Output Enable (OE) provides the capability of three-stating the FIFO outputs. FALL-THROUGH MODE The FIFO operates in a Fall-Through Mode when data gets shifted into an empty FIFO. After the fall-through delay the data propagates to the output. When the data reaches the output, the Output Ready (OR) goes HIGH. A Fall-Through Mode also occurs when the FIFO is completely full. When data is shifted out of the full FIFO a location is available for new data. After a fallthrough delay, the lnput Ready goes HlGH. If Shift In is HIGH, the new data can be written to the FIFO. The fall-through delay of a RAM-based FIFO (one clock cycle) is far less than the delay of a Shift register-based FIFO. FIFO RESET The FIFO must be reset upon power up using the Master Reset (MR) signal. This causes the FIFO to enter an empty state signified by Output Ready (OR) being LOW and Input Ready (IR) being HIGH. In this state, the data outputs (Q0-4) will be LOW. DATA INPUT Data is shifted in on the LOW-to-HIGH transition of Shift In (Sl). This loads input data into the first word location of the FIFO and causes the lnput Ready (IR) to go LOW. On the HlGH-to-LOW transition of SI, the write pointer is moved to the next word position and lR goes HlGH indicating the readiness to accept new data. If the FIFO is full, IR will remain LOW until a word of data is shifted out. SIGNAL DESCRIPTIONS: INPUTS: DATA INPUT (D0-4) Data input lines. The IDT72413 has a 5-bit data input. 4 IDT72413 CMOS PARALLEL FIFO WITH FLAGS 64 x 5 COMMERCIAL TEMPERATURE RANGE CONTROLS: OUTPUT READY (OR) When Output Ready is HIGH, the output (Q0-4) contains valid data. When OR is LOW, the FIFO is unavailable for new output data. OR is also used to cascade many FIFOs together, as shown in Figure 13. SHIFT IN (SI) Shift In controls the input of the data into the FIFO. When SI is HIGH, data can be written to the FIFO via the D0-4 lines. The data has to meet set-up and hold time requirements with respect to the rising edge of SI. SHIFT OUT (SO) Shift Out controls the outputs data from the FIFO. OUTPUT ENABLE (OE) Output Enable is used to enable the FIFO outputs onto a bus. OE is active LOW. MASTER RESET (MR) Master Reset clears the FIFO of any data stored within. Upon power up, the FIFO should be cleared with a Master Reset. Master Reset is active LOW. ALMOST-FULL/EMPTY FLAG (AF/E) Almost-Full/Empty Flag signals when the FIFO is 7/8 full (56 or more words) or 1/8 from empty (8 or less words). OUTPUTS: HALF-FULL FLAG (HF) Half-Full Flag signals when the FIFO has 32 or more words in it. DATA OUTPUT (Q0-4) Data output lines, three-state. The IDT72413 has a 5-bit output. INPUT READY (IR) When Input Ready is HIGH, the FIFO is ready for new input data to be written to it. When IR is LOW, the FIFO is unavailable for new input data, IR is also used to cascade many FIFOs together, as shown in Figure 13. 1/fIN 1/fIN tSIH tSIL SI tIRH IR tIDS tIRL tIDH INPUT DATA 2748 drw 04 Figure 2. Input Timing SI (7) (2) (4) (1) INPUT DATA (5) (3) IR (6) STABLE DATA 2748 drw 05 NOTES: 1. IR HIGH indicates space is available and a SI pulse may be applied. 2. Input Data is loaded into the FIFO. 3. IR goes LOW indicating the FIFO is unavailable for new data. 4. The write pointer is incremented. 5. The FIFO is ready for the next word. 6. If the FIFO is full, then IR remains LOW. 7. SI pulses applied while IR is LOW will be ignored (see Figure 4). Figure 3. The Machanism of Shifting Data Into the FIFO 5 IDT72413 CMOS PARALLEL FIFO WITH FLAGS 64 x 5 COMMERCIAL TEMPERATURE RANGE (2) SO (3) SI (5) tIPH tPT (4) IR (1) STABLE DATA INPUT DATA 2748 drw 06 NOTES: 1. FIFO is initially full. 2. SO pulse is applied. 3. SI is held HIGH. 4. As soon as IR becomes HIGH the Input Data is loaded into the FIFO. 5. The write pointer is incremented. SI should not go LOW until (tPT + tIPH). Figure 4. Data is Shifted In Whenever Shift In and Input Ready are Both HIGH (7) (2) SO (4) (1) (5) (3) OR (6) A or B OUTPUT DATA A- DATA B- DATA 2748 drw 08 NOTES: 1. This data is loaded consecutively A, B, C. 2. Output data changes on the falling edge of SO after a valid SO sequence, i.e., OR and SO are both HIGH together. Figure 5. Output TIming 1/fOUT 1/fOUT tSOH tSOL SO (2) tORD tRH OR tODS tODH (1) OUTPUT DATA tORL A-DATA B-DATA C-DATA 2748 drw 07 NOTES: 1. OR HIGH indicates that data is available and a SO pulse may be applied. 2. SO goes HIGH causing the next step. 3. OR goes LOW. 4. Read pointer is incremented. 5. OR goes HIGH indicating that new data (B) will be available at the FIFO outputs after tORD ns. 6. If the FIFO has only one word loaded (A DATA) , OR stays LOW and the A-DATA remains unchanged at the outputs. 7. SO pulses applied when OR is LOW will be ignored. Figure 6. The Mechanism of Shifting Data Out of the FIFO 6 IDT72413 CMOS PARALLEL FIFO WITH FLAGS 64 x 5 COMMERCIAL TEMPERATURE RANGE SI SO tOPH tPT OR (1) 2748 drw 09 NOTE: 1. FIFO initailly empty. Figure 7. tPT and tOPH Specification tMRW (1) tMRIRL tMRIRH IR (1) tMRORL tMRS OR SI tMRQ DATA OUTPUTS tMRHF HF tMRAFE AF/E 2748 drw 10 NOTE: 1. FIFO is partially full. Figure 8. Master Reset Timing tSOH SO tAEH AF/E (1) tAEL tSIH SI 2748 drw 11 NOTE: 1. FIFO contains 9 words (one more than Almost-Empty). Figure 9. tAEH and tAEL Specifications 7 IDT72413 CMOS PARALLEL FIFO WITH FLAGS 64 x 5 COMMERCIAL TEMPERATURE RANGE tSIH SI tAFH AF/E (1) tAFL tSOH SO 2748 drw 12 NOTE: 1. FIFO contains 55 words (one short of Almost-Full). Figure 10. tAFH and tAFL Specifications tSIH SI tHFH HF (1) tHFL tSOH SO 2748 drw 13 NOTE: 1. FIFO contains 31 words (one short of Half-Full). Figure 11. tHFL and tHFH Specifications 3V VT OE VT 0V t PZL 4.5V (1) WAVEFORM 1 t PLZ 0.5V VT t PZH 1.5V V OL t PHZ (2) V OH 1.5V VT WAVEFORM 2 0V 0.5V 2748 drw 14 NOTES: 1. Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control. 2. Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control. Figure 12. Enable and Disable 8 IDT72413 CMOS PARALLEL FIFO WITH FLAGS 64 x 5 COMMERCIAL TEMPERATURE RANGE OUTPUT ENABLE COMPOSITE INPUT READY SHIFT IN HF IR SI D0 D1 D2 D3 D4 OE AF/E SO OR Q0 Q1 Q2 Q3 Q4 MR HF IR SI D0 D1 D2 D3 D4 OE AF/E SO OR Q0 Q1 Q2 Q3 Q4 MR HF IR SI D0 D1 D2 D3 D4 OE AF/E SO OR Q0 Q1 Q2 Q3 Q4 MR SHIFT OUT COMPOSITE OUTPUT READY MASTER RESET 2748 drw 15 NOTE: 1. FIFOs are expandable in width. However, in forming wider words two external gates are required to generate composite Input and Output Ready flags. This requirement is due to the different fall-through times of the FIFOs. Figure 13. 64 x 15 FIFO with IDT72413 8-BITS SYSTEM 1 ENBL SI 8-BITS TWO IDT72413 64 x 8 SO SI IR OR ALMOST-FULL/ EMPTY INTERRUPT HALF-FULL FLAG SYSTEM 2 IO RDY INTERRUPT 2748 drw 16 NOTE: 1. Cascading the FIFOs in word width is done by ANDing the IR and OR as shown in Figure 13. Figure 14. Application for IDT72413 for Two Asynchronous Systems 9 SHIFT IN INPUT READY SI IR D0 D1 D2 D3 D4 DATA IN OR SO Q0 Q1 Q2 Q3 Q4 SI IR D0 D1 D2 D3 D4 OR SO Q0 Q1 Q2 Q3 Q4 OUTPUT READY SHIFT OUT DATA OUT 2748 drw 17 NOTE: 1. FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the devices. Figure 15. 128 x 5 Depth Expansion ORDERING INFORMATION XXXXX X XX X Device Type Power Speed Package X X X Process / Temperature Range BLANK 8 Tube or Tray Tape and Reel BLANK Commercial (0°C to +70°C) G(2) Green P(3) SO Plastic DIP (300 mil, P20-1) Small Outline IC (300 mil, J-bend, SOIC SO20-2) 45 35 25 Commercial L Low Power 72413 64 x 5 - FIFO Shift Frequency (fS) Speed in MHz 2748 drw18 NOTES: 1. Industrial temperature range is available by special order. 2. Green parts are available, for specific speeds and packages contact your sales office. 3. For “P”, Plastic Dip, when ordering green package, the suffix is “PDG”. DATASHEET DOCUMENT HISTORY 07/10/2003 02/11/2009 06/29/2012 11/21/2014 08/08/2019 pgs. 1, 2, 3, and 10. pgs. 1 and 10. pgs. 1, 2, 9 and 10. PDN# CQ-14-08 issued. See IDT.com for PDN specifics. Datasheet changed to Obsolete Status. CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 10 for Tech Support: 408-360-1753 email: FIFOhelp@idt.com IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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