72V283L7-5PF

3.3 VOLT HIGH-DENSITY SUPERSYNC II™ NARROW BUS FIFO 512 x 18/1,024 x 9, 1,024 x 18/2,048 x 9 IDT72V223, IDT72V233 IDT72V243, IDT72V253 2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9 IDT72V263, IDT72V273 8,192 x 18/16,384 x 9, 16,384 x 18/32,768 x 9 IDT72V283, IDT72V293 32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 FEATURES: • • • • • • • • • Choose among the following memory organizations: IDT72V223 ⎯ 512 x 18/1,024 x 9 IDT72V233 ⎯ 1,024 x 18/2,048 x 9 IDT72V243 ⎯ 2,048 x 18/4,096 x 9 IDT72V253 ⎯ 4,096 x 18/8,192 x 9 IDT72V263 ⎯ 8,192 x 18/16,384 x 9 IDT72V273 ⎯ 16,384 x 18/32,768 x 9 IDT72V283 ⎯ 32,768 x 18/65,536 x 9 IDT72V293 ⎯ 65,536 x 18/131,072 x 9 Functionally compatible with the IDT72V255LA/72V265LA and IDT72V275/72V285 SuperSync FIFOs Up to 166 MHz Operation of the Clocks User selectable Asynchronous read and/or write ports (BGA Only) User selectable input and output port bus-sizing - x9 in to x9 out - x9 in to x18 out - x18 in to x9 out - x18 in to x18 out Pin to Pin compatible to the higher density of IDT72V2103/72V2113 Big-Endian/Little-Endian user selectable byte representation 5V tolerant inputs Fixed, low first word latency • • • • • • • • • • • • • • • • • Zero latency retransmit Auto power down minimizes standby power consumption Master Reset clears entire FIFO Partial Reset clears data, but retains programmable settings Empty, Full and Half-Full flags signal FIFO status Programmable Almost-Empty and Almost-Full flags, each flag can default to one of eight preselected offsets Selectable synchronous/asynchronous timing modes for AlmostEmpty and Almost-Full flags Program programmable flags by either serial or parallel means Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags) Output enable puts data outputs into high impedance state Easily expandable in depth and width JTAG port, provided for Boundary Scan function (BGA Only) Independent Read and Write Clocks (permit reading and writing simultaneously) Available in a 80-pin Thin Quad Flat Pack (TQFP) or a 100-pin Ball Grid Array (BGA) (with additional features) High-performance submicron CMOS technology Industrial temperature range (–40°°C to +85°°C) is available Green parts available, see ordering information FUNCTIONAL BLOCK DIAGRAM *Available on the BGA package only. D0 -Dn (x9 or x18) WEN INPUT REGISTER *ASYW WRITE CONTROL LOGIC RAM ARRAY 512 x 18 or 1,024 x 9 1,024 x 18 or 2,048 x 9 2,048 x 18 or 4,096 x 9 4,096 x 18 or 8,192 x 9 8,192 x 18 or 16,384 x 9 16,384 x 18 or 32,768 x 9 32,768 x 18 or 65,536 x 9 65,536 x 18 or 131,072 x 9 WRITE POINTER BE IP CONTROL LOGIC IW OW BUS CONFIGURATION MRS PRS RESET LOGIC * * ** * TCK TRST TMS TDI TDO LD SEN * WCLK/WR JTAG CONTROL (BOUNDARY SCAN) OUTPUT REGISTER OFFSET REGISTER FF/IR PAF EF/OR PAE HF FWFT/SI PFM FSEL0 FSEL1 FLAG LOGIC READ POINTER READ CONTROL LOGIC RT RM ASYR * * RCLK/RD REN * 4666 drw01 OE Q0 -Qn (x9 or x18) IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync II FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1 ©2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. MARCH 2018 DSC-4666/18 IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 DESCRIPTION: COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES • The period required by the retransmit operation is now fixed and short. • The first word data latency period, from the time the first word is written to an empty FIFO to the time it can be read, is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSync family.) • Asynchronous/Synchronous translation on the read or write ports • High density offerings up to 1 Mbit Bus-Matching SuperSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. The IDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/ 72V293 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls and a flexible Bus-Matching x9/ x18 data flow. These FIFOs offer numerous improvements over previous SuperSync FIFOs, including the following: • Flexible x9/x18 Bus-Matching on both read and write ports • The limitation of the frequency of one clock input with respect to the other has been removed. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. WCLK PRS MRS LD FWFT/SI FF/IR PAF OW FSEL0 HF FSEL1 BE IP VCC PAE PFM EF/OR RM RCLK REN PIN CONFIGURATIONS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 INDEX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 RT OE VCC Q17 Q16 GND GND Q15 Q14 VCC Q13 Q12 GND Q11 GND Q10 VCC Q9 Q8 Q7 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 WEN SEN DNC(1) VCC DNC(1) IW GND D17 VCC D16 D15 D14 D13 GND D12 D11 D10 D9 D8 VCC D7 D6 GND D5 D4 D3 D2 D1 D0 GND Q0 Q1 GND Q2 Q3 VCC Q4 Q5 GND Q6 4666 drw02 NOTE: 1. DNC = Do Not Connect. TQFP (PN80, order code: PF) TOP VIEW 2 BUS FIFO IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 8K 9/18, 2K 32K 9/18, x 9/18, 9/18,x256K 9/18, 512K64K x9 x 9/18, 128K x 9 512xx18, 18,16K 1K xx 9/18, xx 9/18, 4K64K x 9/18, 8K 128K x 9/18,x 16K 9/18, x32K x 9/18, DESCRIPTION (CONTINUED) COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES During Asynchronous operation only the RD input is used to read data from the FIFO. Data is read on a rising edge of RD, the REN input should be tied to its active state, LOW. When Asynchronous operation is selected on the output port the FIFO must be configured for Standard IDT mode, and the OE input used to provide three-state control of the outputs, Qn. The frequencies of both the RCLK and the WCLK signals may vary from 0 to fMAX with complete independence. There are no restrictions on the frequency of the one clock input with respect to the other. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode. In IDT Standard mode, the first word written to an empty FIFO will not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN and enabling a rising RCLK edge, will shift the word from internal memory to the data output lines. In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A REN does Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either an 18-bit or a 9-bit width as determined by the state of external control pins Input Width (IW) and Output Width (OW) during the Master Reset cycle. The input port can be selected as either a Synchronous (clocked) interface, or Asynchronous interface. During Synchronous operation the input port is controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data present on the Dn data inputs is written into the FIFO on every rising edge of WCLK when WEN is asserted. During Asynchronous operation only the WR input is used to write data into the FIFO. Data is written on a rising edge of WR, the WEN input should be tied to its active state, (LOW). The output port can be selected as either a Synchronous (clocked) interface, or Asynchronous interface. During Synchronous operation the output port is controlled by a Read Clock (RCLK) input and Read Enable (REN) input. Data is read from the FIFO on every rising edge of RCLK when REN is asserted. PIN CONFIGURATIONS (CONTINUED) A1 BALL PAD CORNER A WCLK PRS LD PAF FSEL0 BE ASYR PFM RM REN WEN MRS FWFT/SI OW HF FSEL1 IP PAE EF/OR RCLK ASYW SEN FF/IR VCC VCC VCC VCC VCC RT OE D17 IW VCC GND GND GND GND VCC Q16 Q17 D16 D15 VCC GND GND GND GND VCC Q14 Q15 D13 D14 VCC GND GND GND GND VCC Q13 Q12 D11 D12 VCC GND GND GND GND VCC Q11 Q10 D8 D9 D10 VCC VCC VCC VCC Q1 Q9 Q8 D6 D7 D2 D0 TMS TCK TDO Q2 Q4 Q7 D5 D4 D3 D1 TRST TDI Q0 Q3 Q5 Q6 3 4 5 6 7 8 9 10 B C D E F G H J K 1 2 4666 drw02b BGA: 1mm pitch, 11mm x 11mm (BC100, order code: BC) TOP VIEW 3 IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 DESCRIPTION (CONTINUED) COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES For serial programming, SEN together with LD on each rising edge of WCLK, are used to load the offset registers via the Serial Input (SI). For parallel programming, WEN together with LD on each rising edge of WCLK, are used to load the offset registers via Dn. REN together with LD on each rising edge of RCLK can be used to read the offsets in parallel from Qn regardless of whether serial or parallel offset loading has been selected. During Master Reset (MRS) the following events occur: the read and write pointers are set to the first location of the FIFO. The FWFT pin selects IDT Standard mode or FWFT mode. The Partial Reset (PRS) also sets the read and write pointers to the first location of the memory. However, the timing mode, programmable flag programming method, and default or programmed offset settings existing before Partial Reset remain unchanged. The flags are updated according to the timing mode and offsets in effect. PRS is useful for resetting a device in midoperation, when reprogramming programmable flags would be undesirable. It is also possible to select the timing mode of the PAE (Programmable AlmostEmpty flag) and PAF (Programmable Almost-Full flag) outputs. The timing modes can be set to be either asynchronous or synchronous for the PAE and PAF flags. If asynchronous PAE/PAF configuration is selected, the PAE is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOW- not have to be asserted for accessing the first word. However, subsequent words written to the FIFO do require a LOW on REN for access. The state of the FWFT/SI input during Master Reset determines the timing mode in use. For applications requiring more data storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e. the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required. These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready), FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and FF functions are selected in IDT Standard mode. The IR and OR functions are selected in FWFT mode. HF, PAE and PAF are always available for use, irrespective of timing mode. PAE and PAF can be programmed independently to switch at any point in memory. Programmable offsets determine the flag switching threshold and can be loaded by two methods: parallel or serial. Eight default offset settings are also provided, so that PAE can be set to switch at a predefined number of locations from the empty boundary and the PAF threshold can also be set at similar predefined values from the full boundary. The default offset values are set during Master Reset by the state of the FSEL0, FSEL1, and LD pins. PARTIAL RESET (PRS) MASTER RESET (MRS) WRITE CLOCK (WCLK/WR*) READ CLOCK (RCLK/RD*) WRITE ENABLE (WEN) READ ENABLE (REN) IDT 72V223 72V233 72V243 72V253 72V263 72V273 72V283 72V293 LOAD (LD) (x9 or x18) DATA IN (D0 - Dn) SERIAL ENABLE(SEN) FIRST WORD FALL THROUGH/ SERIAL INPUT (FWFT/SI) OUTPUT ENABLE (OE) (x9 or x18) DATA OUT (Q0 - Qn) RETRANSMIT (RT) EMPTY FLAG/OUTPUT READY (EF/OR) PROGRAMMABLE ALMOST-EMPTY (PAE) HALF-FULL FLAG (HF) BIG-ENDIAN/LITTLE-ENDIAN (BE) INTERSPERSED/ NON-INTERSPERSED PARITY (IP) FULL FLAG/INPUT READY (FF/IR) PROGRAMMABLE ALMOST-FULL (PAF) 4666 drw03 OUTPUT WIDTH (OW) BUSMATCHING (BM) INPUT WIDTH (IW) Figure 1. Single Device Configuration Signal Flow Diagram 4 BUS FIFO IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 8K 9/18, 2K 32K 9/18, x 9/18, 9/18,x256K 9/18, 512K64K x9 x 9/18, 128K x 9 512xx18, 18,16K 1K xx 9/18, xx 9/18, 4K64K x 9/18, 8K 128K x 9/18,x 16K 9/18, x32K x 9/18, COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES out of the FIFO first, followed by the least significant byte. If Little-Endian format is selected, then the least significant byte of the long word written into the FIFO will be read out first, followed by the most significant byte. The mode desired is configured during master reset by the state of the Big-Endian (BE) pin. The Interspersed/Non-Interspersed Parity (IP) bit function allows the user to select the parity bit in the word loaded into the parallel port (D0-Dn) when programming the flag offsets. If Interspersed Parity mode is selected, then the FIFO will assume that the parity bit is located in bit position D8 during the parallel programming of the flag offsets. If Non-Interspersed Parity mode is selected, then D8 is assumed to be a valid bit and D16 and D17 are ignored. IP mode is selected during Master Reset by the state of the IP input pin. This mode is relevant only when the input width is set to x18 mode. Interspersed Parity control only has an effect during parallel programming of the offset registers. It does not effect the data written to and read from the FIFO. A JTAG test port is provided, here the FIFO has fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. If, at any time, the FIFO is not actively performing an operation, the chip will automatically power down. Once in the power down state, the standby supply current consumption is minimized. Initiating any operation (by activating control inputs) will immediately take the device out of the power down state. The IDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/ 72V293 are fabricated using IDT’s high speed submicron CMOS technology. to-HIGH transition of WCLK. Similarly, the PAF is asserted LOW on the LOWto-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. If synchronous PAE/PAF configuration is selected , the PAE is asserted and updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK only and not RCLK. The mode desired is configured during master reset by the state of the Programmable Flag Mode (PFM) pin. The Retransmit function allows data to be reread from the FIFO more than once. A LOW on the RT input during a rising RCLK edge initiates a retransmit operation by setting the read pointer to the first location of the memory array. A zero-latency retransmit timing mode can be selected using the Retransmit timing Mode pin (RM). During Master Reset, a LOW on RM will select zero-latency retransmit. A HIGH on RM during Master Reset will select normal latency. If zero-latency retransmit operation is selected the first data word to be retransmitted will be placed on the output register with respect to the same RCLK edge that initiated the retransmit based on RT being LOW. Refer to Figure 11 and 12 for Retransmit Timing with normal latency. Refer to Figure 13 and 14 for Retransmit Timing with zero-latency. A Big-Endian/Little-Endian data word format is provided. This function is useful when data is written into the FIFO in long word format (x18) and read out of the FIFO in small word (x9) format. If Big-Endian mode is selected, then the most significant byte (word) of the long word written into the FIFO will be read TABLE 1 — BUS-MATCHING CONFIGURATION MODES IW OW Write Port Width Read Port Width L L x18 x18 L H x18 x9 H L x9 x18 H H x9 x9 5 IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN DESCRIPTION (TQFP & BGA PACKAGES) Symbol Name (1) BE *Big-Endian/ Little-Endian D0–D17 Data Inputs EF/OR FF/IR Empty Flag/ Output Ready Full Flag/ Input Ready FSEL0(1) Flag Select Bit 0 FSEL1(1) Flag Select Bit 1 FWFT/SI First Word Fall Through/Serial In HF Half-Full Flag (1) IP Interspersed Parity I/O Description I During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset will select Little-Endian format. I Data inputs for a 18- or 9-bit bus. When in 18-bit mode, D0–D17 are used. When in 9-bit mode, D0–D8 are used and the unused inputs, D9–D17, should be tied LOW. O In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory is empty. In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the outputs. O In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is full. In the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing to the FIFO memory. I During Master Reset, this input along with FSEL1 and the LD pin, will select the default offset values for the programmable flags PAE and PAF. There are up to eight possible settings available. I During Master Reset, this input along with FSEL0 and the LD pin will select the default offset values for the programmable flags PAE and PAF. There are up to eight possible settings available. I During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin functions as a serial input for loading offset registers. O HF indicates whether the FIFO memory is more or less than half-full. I IW(1) Input Width I LD Load I MRS Master Reset I OE OW(1) Output Enable Output Width I I PAE O PRS Programmable Almost-Empty Flag Programmable Almost-Full Flag Programmable Flag Mode Partial Reset Q0–Q17 Data Outputs O REN RCLK/ RD Read Enable Read Clock/ Read Strobe I I PAF PFM(1) O I I During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed Parity mode. Interspersed Parity control only has an effect during parallel programming of the offset registers. It does not effect the data written to and read from the FIFO. This pin selects the bus width of the write port. During Master Reset, when IW is LOW, the write port will be configured with a x18 bus width. If IW is HIGH, the write port will be a x9 bus width. This is a dual purpose pin. During Master Reset, the state of the LD input, along with FSEL0 and FSEL1, determines one of eight default offset values for the PAE and PAF flags, along with the method by which these offset registers can be programmed, parallel or serial (see Table 2). After Master Reset, this pin enables writing to and reading from the offset registers. MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master Reset, the FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations, one of eight programmable flag default settings, serial or parallel programming of the offset settings, Big-Endian/Little-Endian format, zero latency timing mode, interspersed parity, and synchronous versus asynchronous programmable flag timing modes. OE controls the output impedance of Qn. This pin selects the bus width of the read port. During Master Reset, when OW is LOW, the read port willbe configured with a x18 bus width. If OW is HIGH, the read port will be a x9 bus width. PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Empty Offset register. PAE goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n. PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in the Full Offset register. PAF goes LOW if the number of free locations in the FIFO memory is less than or equal to m. During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on PFM will select Synchronous Programmable flag timing mode. PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset, the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings are all retained. Data outputs for a 18- or 9-bit bus. When in 18-bit mode, Q0–Q17 are used and when in 9-bit mode, Q0–Q8 are used, and the unused outputs, Q9-Q17 should not be connected. Outputs are not 5V tolerant regardless of the state of OE. REN enables RCLK for reading data from the FIFO memory and offset registers. If Synchronous operation of the read port has been selected, when enabled by REN, the rising edge of RCLK reads data from the FIFO memory and offsets from the programmable registers. If LD is LOW, the values loaded into the offset registers is output on a rising edge of RCLK. If Asynchronous operation of the read port has been selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner. REN should be tied LOW. Asynchronous operation of the RCLK/RD input is only available in the BGA package. NOTE: 1. Inputs should not change state after Master Reset. 6 BUS FIFO IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 8K 9/18, 2K 32K 9/18, x 9/18, 9/18,x256K 9/18, 512K64K x9 x 9/18, 128K x 9 512xx18, 18,16K 1K xx 9/18, xx 9/18, 4K64K x 9/18, 8K 128K x 9/18,x 16K 9/18, x32K x 9/18, COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN DESCRIPTION-CONTINUED (TQFP & BGA PACKAGES) Symbol RM(1) RT Name Retransmit Timing Mode Retransmit SEN WCLK/ WR Serial Enable Write Clock/ Write Strobe WEN V CC Write Enable +3.3V Supply I/O Description I During Master Reset, a LOW on RM will select zero latency Retransmit timing Mode. A HIGH on RM will select normal latency mode. I RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to HIGH in FWFT mode) and does not disturb the write pointer, programming method, existing timing mode or programmable flag settings. RT is useful to reread data from the first physical location of the FIFO. I SEN enables serial loading of programmable flag offsets. I If Synchronous operation of the write port has been selected, when enabled by WEN, the rising edge of WCLK writes data into the FIFO. If Asynchronous operation of the write port has been selected, WR writes data into the FIFO on a rising edge in an Asynchronous manner, (WEN should be tied to its active state). Asynchronous operation of the WCLK/WR input is only available in the BGA package. I I WEN enables WCLK for writing data into the FIFO memory and offset registers. These are VCC supply inputs and must be connected to the 3.3V supply rail. NOTE: 1. Inputs should not change state after Master Reset. PIN DESCRIPTION (BGA PACKAGE ONLY) Symbol ASYR(1) ASYW(1) Name Asynchronous Read Port Asynchronous Write Port I/O Description I A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW will select Asynchronous operation. If Asynchronous is selected the FIFO must operate in IDT Standard mode. I A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW will select Asynchronous operation. TCK(2) JTAG Clock I Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND. TDI(2) JTAG Test Data Input I One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected. TDO(2) JTAG Test Data Output O One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register, ID Register and Bypass Register. This output is high impedance except when shifting, while in SHIFT-DR and SHIFT-IR controller states. TMS(2) JTAG Mode Select I TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected. TRST(2) JTAG Reset I TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not automatically reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles. If the TAP controller is not properly reset then the FIFO outputs will always be in high-impedance. If the JTAG function is used but the user does not want to use TRST, then TRST can be tied with MRS to ensure proper FIFO operation. If the JTAG function is not used then this signal needs to be tied to GND. NOTES: 1. Inputs should not change state after Master Reset. 2. These pins are for the JTAG port. Please refer to pages 41-44 and Figures 31-33. 7 IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 ABSOLUTE MAXIMUM RATINGS Symbol VTERM (2) TSTG IOUT Rating Com'l & Ind'l Unit Terminal Voltage with respect to GND –0.5 to +4.5 V Storage Temperature –55 to +125 DC Output Current –50 to +50 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES RECOMMENDED DC OPERATING CONDITIONS Symbol °C mA NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminal only. Min. Typ. Max. Unit VCC(1) Supply Voltage (Com'l & Ind'l) Parameter 3.15 3.3 3.45 V GND Supply Voltage (Com'l & Ind'l) 0 0 0 V (2) VIH Input High Voltage (Com'l & Ind'l) 2.0 — 5.5 V VIL(3) Input Low Voltage (Com'l & Ind'l) — — 0.8 V TA Operating Temperature Commercial 0 — +70 °C TA Operating Temperature Industrial -40 — +85 °C NOTES: 1. VCC=3.3V ± 0.15V, JEDEC JESD8-A compliant. 2. Outputs are not 5V tolerant. 3. 1.5V undershoots are allowed for 10ns once per cycle. DC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant) IDT72V223L IDT72V233L IDT72V243L IDT72V253L IDT72V263L IDT72V273L IDT72V283L IDT72V293L Commercial and Industrial(1) tCLK = 6, 7-5, 10, 15 ns Symbol ILI(2) ILO(3) VOH VOL ICC1(4,5,6) ICC1(4,5,6) ICC2(4,7) Parameter Input Leakage Current Output Leakage Current Output Logic “1” Voltage, IOH = –2 mA Output Logic “0” Voltage, IOL = 8 mA Active Power Supply Current (x9 Input to x9 Output) Active Power Supply Current (x18 Input to x18 Output) Standby Current Min. Max. Unit –1 –10 2.4 — — — — 1 10 — 0.4 30 35 15 μA μA V V mA mA mA NOTES: 1. Industrial temperature range product for 7-5ns and 10ns (IDT72V263/72V273/72V283/72V293 only) are available as standard device. All other speed grades are available by special order. 2. Measurements with 0.4 ≤ VIN ≤ VCC. 3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC. 4. Tested with outputs open (IOUT = 0). 5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz. 6. For x 18 bus widths, typical ICC1 = 5 + fS + 0.002*CL*fS (in mA); for x 9 bus widths, typical ICC1 = 5 + 0.775*fS + 0.002*CL*fS (in mA). These equations are valid under the following conditions: VCC = 3.3V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF). 7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz. CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol CIN(2) COUT(1,2) Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V Max. 10 Unit pF VOUT = 0V 10 pF NOTES: 1. With output deselected, (OE ≥ VIH). 2. Characterized values, not currently tested. 8 BUS FIFO IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 8K 9/18, 2K 32K 9/18, x 9/18, 9/18,x256K 9/18, 512K64K x9 x 9/18, 128K x 9 512xx18, 18,16K 1K xx 9/18, xx 9/18, 4K64K x 9/18, 8K 128K x 9/18,x 16K 9/18, x32K x 9/18, COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS(1) (Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant) Symbol fS tA tCLK tCLKH tCLKL tDS tDH tENS tENH tLDS tLDH tRS tRSS tRSR tRSF tRTS tOLZ tOE tOHZ tWFF tREF tPAFA tPAFS tPAEA tPAES tHF tSKEW1 tSKEW2 Parameter Clock Cycle Frequency Data Access Time(5) Clock Cycle Time Clock High Time Clock Low Time Data Setup Time Data Hold Time Enable Setup Time Enable Hold Time Load Setup Time Load Hold Time Reset Pulse Width(3) Reset Setup Time Reset Recovery Time Reset to Flag and Output Time Retransmit Setup Time Output Enable to Output in Low Z(4) Output Enable to Output Valid(5) Output Enable to Output in High Z(4,5) Write Clock to FF or IR Read Clock to EF or OR Clock to Asynchronous Programmable Almost-Full Flag Write Clock to Synchronous Programmable Almost-Full Flag Clock to Asynchronous Programmable Almost-Empty Flag Read Clock to Synchronous Programmable Almost-Empty Flag Clock to HF Skew time between RCLK and WCLK for EF/OR and FF/IR Skew time between RCLK and WCLK for PAE and PAF Commercial BGA & TQFP IDT72V223L6 IDT72V233L6 IDT72V243L6 IDT72V253L6 IDT72V263L6 IDT72V273L6 IDT72V283L6 IDT72V293L6 Min. Max. — 166 1 4 6 — 2.7 — 2.7 — 2 — 0.5 — 2 — 0.5 — 3 — 0.5 — 10 — 15 — 10 — — 15 3 — 0 — 1 4 1 4 — 4 — 4 — 10 — 4 — 10 — 4 — 10 4 — 5 — Com’l & Ind’l(2) BGA & TQFP IDT72V223L7-5 IDT72V233L7-5 IDT72V243L7-5 IDT72V253L7-5 IDT72V263L7-5 IDT72V273L7-5 IDT72V283L7-5 IDT72V293L7-5 Min. Max. — 133.3 1(5) 5 7.5 — 3.5 — 3.5 — 2.5 — 0.5 — 2.5 — 0.5 — 3.5 — 0.5 — 10 — 15 — 10 — — 15 3.5 — 0 — 1(5) 6 1(5) 6 — 5 — 5 — 12.5 — 5 — 12.5 — 5 — 12.5 5 — 7 — Com’l & Ind’l(2) TQFP Only Commercial TQFP Only IDT72V263L10 IDT72V273L10 IDT72V283L10 IDT72V293L10 Min. Max. — 100 1(5) 6.5 10 — 4.5 — 4.5 — 3.5 — 0.5 — 3.5 — 0.5 — 3.5 — 0.5 — 10 — 15 — 10 — — 15 3.5 — 0 — 1(5) 6 1(5) 6 — 6.5 — 6.5 — 16 — 6.5 — 16 — 6.5 — 16 7 — 10 — IDT72V263L15 IDT72V273L15 IDT72V283L15 IDT72V293L15 Min. Max. — 66.7 1(5) 10 15 — 6 — 6 — 4 — 1 — 4 — 1 — 4 — 1 — 15 — 15 — 15 — — 15 4 — 0 — 1(5) 8 1(5) 8 — 10 — 10 — 20 — 10 — 20 — 10 — 20 9 — 14 — Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES: 1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode. 2. Industrial temperature range product for 7-5ns and 10ns (IDT72V263/72V273/72V283/72V293 only) are available as standard device. All other speed grades are available by special order. 3. Pulse widths less than minimum values are not allowed. 4. Values guaranteed by design, not currently tested. 5. TQFP package only: for speed grades 7-8-105ns, 10ns and 15ns the minimum for tA, tOE, and tOHZ is 2ns. 6. The IDT72V223/72V233/72V243/72V253 are only available in 6ns and 7-5ns speed grades. 9 IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS(1) — ASYNCHRONOUS TIMING (Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant) Symbol fA(4) tAA(4) tCYC(4) tCYH(4) tCYL(4) tRPE(4) tFFA(4) tEFA(4) tPAFA(4) tPAEA(4) Parameter Cycle Frequency (Asynchronous mode) Data Access Time Cycle Time Cycle HIGH Time Cycle LOW Time Read Pulse after EF HIGH Clock to Asynchronous FF Clock to Asynchronous EF Clock to Asynchronous Programmable Almost-Full Flag Clock to Asynchronous Programmable Almost-Empty Flag NOTES: 1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode. 2. Pulse widths less than minimum values are not allowed. 3. Values guaranteed by design, not currently tested. 4. Parameters apply to the BGA package only. 10 Commercial Com'l & Ind'l IDT72V223L6 IDT72V233L6 IDT72V243L6 IDT72V253L6 IDT72V263L6 IDT72V273L6 IDT72V283L6 IDT72V293L6 Min. Max. — 100 0.6 8 10 — 4.5 — 4.5 — 8 — — 8 — 8 — 8 — 8 IDT72V223L7-5 IDT72V233L7-5 IDT72V243L7-5 IDT72V253L7-5 IDT72V263L7-5 IDT72V273L7-5 IDT72V283L7-5 IDT72V293L7-5 Min. Max. — 83 0.6 10 12 — 5 — 5 — 10 — — 10 — 10 — 10 — 10 Unit MHz ns ns ns ns ns ns ns ns ns BUS FIFO IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 8K 9/18, 2K 32K 9/18, x 9/18, 9/18,x256K 9/18, 512K64K x9 x 9/18, 128K x 9 512xx18, 18,16K 1K xx 9/18, xx 9/18, 4K64K x 9/18, 8K 128K x 9/18,x 16K 9/18, x32K x 9/18, AC TEST CONDITIONS COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES AC TEST LOADS - 6ns, 7.5ns Speed Grade Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load for tCLK = 10ns, 15 ns Output Load for tCLK = 6ns, 7.5ns GND to 3.0V 3ns(1) 1.5V 1.5V See Figure 2a See Figure 2b & 2c 1.5V 50Ω Z0 = 50Ω I/O 4666 drw04a NOTE: 1. For 166Mhz and 133MHz operation input rise/fall times are 1.5ns. Figure 2b. AC Test Load AC TEST LOADS - 10ns, 15ns Speed Grades 6 tCD (Typical, ns) 5 3.3V 330Ω 4 3 2 1 D.U.T. 20 30 50 30pF* 510Ω 80 100 Capacitance (pF) 200 4666 drw04b 4666 drw04 Figure 2c. Lumped Capacitive Load, Typical Derating Figure 2a. Output Load * Includes jig and scope capacitances. OUTPUT ENABLE & DISABLE TIMING Output Enable Output Disable VIH OE VIL tOE & tOLZ Output VCC Normally 2 LOW Output Normally VCC 2 HIGH tOHZ VCC 2 100mV 100mV VOL VOH 100mV 100mV VCC 2 4666 drw04c NOTE: 1. REN is HIGH. 11 IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 FUNCTIONAL DESCRIPTION COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES writes for the IDT72V293. The offset “m” is the full offset value. The default setting for these values are stated in the footnote of Table 2. This parameter is also user programmable. See section on Programmable Flag Offset Loading. When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further write operations. If no reads are performed after a reset, FF will go LOW after D writes to the FIFO. If the x18 Input or x18 Output bus Width is selected, D = 512 writes for the IDT72V223, 1,024 writes for the IDT72V233, 2,048 writes for the IDT72V243, 4,096 writes for the IDT72V253, 8,192 writes for the IDT72V263, 16,384 writes for the IDT72V273, 32,768 writes for the IDT72V283 and 65,536 writes for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, D = 1024 writes for the IDT72V223, 2,048 writes for the IDT72V233, 4,096 writes for the IDT72V243, 8,192 writes for the IDT72V253, 16,384 writes for the IDT72V263, 32,768 writes for the IDT72V273, 65,536 writes for the IDT72V283 and 131,072 writes for the IDT72V293, respectively. If the FIFO is full, the first read operation will cause FF to go HIGH. Subsequent read operations will cause PAF and HF to go HIGH at the conditions described in Table 3. If further read operations occur, without write operations, PAE will go LOW when there are n words in the FIFO, where n is the empty offset value. Continuing read operations will cause the FIFO to become empty. When the last word has been read from the FIFO, the EF will go LOW inhibiting further read operations. REN is ignored when the FIFO is empty. When configured in IDT Standard mode, the EF and FF outputs are double register-buffered outputs. Relevant timing diagrams for IDT Standard mode can be found in Figure 7, 8 and 11. TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH (FWFT) MODE The IDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/ 72V293 support two different timing modes of operation: IDT Standard mode or First Word Fall Through (FWFT) mode. The selection of which mode will operate is determined during Master Reset, by the state of the FWFT/SI input. If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode will be selected. This mode uses the Empty Flag (EF) to indicate whether or not there are any words present in the FIFO. It also uses the Full Flag function (FF) to indicate whether or not the FIFO has any free space for writing. In IDT Standard mode, every word read from the FIFO, including the first, must be requested using the Read Enable (REN) and RCLK. If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be selected. This mode uses Output Ready (OR) to indicate whether or not there is valid data at the data outputs (Qn). It also uses Input Ready (IR) to indicate whether or not the FIFO has any free space for writing. In the FWFT mode, the first word written to an empty FIFO goes directly to Qn after three RCLK rising edges, REN = LOW is not necessary. Subsequent words must be accessed using the Read Enable (REN) and RCLK. Various signals, both input and output signals operate differently depending on which timing mode is in effect. IDT STANDARD MODE In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the manner outlined in Table 3. To write data into to the FIFO, Write Enable (WEN) must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO on subsequent transitions of the Write Clock (WCLK). After the first write is performed, the Empty Flag (EF) will go HIGH. Subsequent writes will continue to fill up the FIFO. The Programmable Almost-Empty flag (PAE) will go HIGH after n + 1 words have been loaded into the FIFO, where n is the empty offset value. The default setting for these values are stated in the footnote of Table 2. This parameter is also user programmable. See section on Programmable Flag Offset Loading. If one continued to write data into the FIFO, and we assumed no read operations were taking place, the Half-Full flag (HF) would toggle to LOW once (D/2 + 1) words were written into the FIFO. If x18 Input or x18 Output bus Width is selected, (D/2 + 1) = the 257th word for the IDT72V223, 513rd word for IDT72V233, 1,025th word for the IDT72V243, 2,049th word for the IDT72V253, 4,097th word for the IDT72V263, 8,193th word for IDT72V273, 16,385th word for the IDT72V283 and 32,769th word for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, (D/2 + 1) = the 513rd word for the IDT72V223, 1,025th word for IDT72V233, 2,049th word for the IDT72V243, 4,097th word for the IDT72V253, 8,193rd word for the IDT72V263, 16,385th word for IDT72V273, 32,769th word for the IDT72V283 and 65,537th word for the IDT72V293. Continuing to write data into the FIFO will cause the Programmable Almost-Full flag (PAF) to go LOW. Again, if no reads are performed, the PAF will go LOW after (D-m) writes to the FIFO. If x18 Input or x18 Output bus Width is selected, (D-m) = (512-m) writes for the IDT72V223, (1,024-m) writes for the IDT72V233, (2,048-m) writes for the IDT72V243 and (4,096-m) writes for the IDT72V253, (8,192-m) writes for the IDT72V263, (16,384-m) writes for the IDT72V273, (32,768-m) writes for the IDT72V283 and (65,536-m) writes for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, (D-m) = (1,024-m) writes for the IDT72V223, (2,048-m) writes for the IDT72V233, (4,096-m) writes for the IDT72V243, (8,192-m) writes for the IDT72V253, (16,384-m) writes for the IDT72V263, (32,768-m) writes for the IDT72V273, (65,536-m) writes for the IDT72V283 and (131,072-m) FIRST WORD FALL THROUGH MODE (FWFT) In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the manner outlined in Table 4. To write data into the FIFO, WEN must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO on subsequent transitions of WCLK. After the first write is performed, the Output Ready (OR) flag will go LOW. Subsequent writes will continue to fill up the FIFO. PAE will go HIGH after n+2 words have been loaded into the FIFO, where n is the empty offset value. The default setting for these values are stated in the footnote of Table 2. This parameter is also user programmable. See section on Programmable Flag Offset Loading. If one continued to write data into the FIFO, and we assumed no read operations were taking place, the HF would toggle to LOW once the (D/2 + 2) words were written into the FIFO. If x18 Input or x18 Output bus Width is selected, (D/2 + 2) = the 258th word for the IDT72V223, 514th word for IDT72V233, 1,026th word for the IDT72V243, 2,050th word for the IDT72V253, 4,098th word for the IDT72V263, 8,194th word for IDT72V273, 16,386th word for the IDT72V283 and 32,770th word for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, (D/2 + 2) = the 514th word for the IDT72V223, 1,026th word for IDT72V233, 2,050th word for the IDT72V243, 4,098th word for the IDT72V253, 8,194th word for the IDT72V263, 16,386th word for IDT72V273, 32,770th word for the IDT72V283 and 65,538th word for the IDT72V293. Continuing to write data into the FIFO will cause the PAF to go LOW. Again, if no reads are performed, the PAF will go LOW after (D-m) writes to the FIFO. If x18 Input or x18 Output bus Width is selected, (D-m) = (513-m) writes for the IDT72V223, (1,025-m) writes for the IDT72V233, (2,049-m) writes for the IDT72V243, (4,097-m) writes for the IDT72V253, (8,193-m) writes for the IDT72V263, (16,385-m) writes for the IDT72V273, (32,769-m) writes for the IDT72V283 and (65,537-m) writes for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, (D-m) = (1,025-m) writes for the IDT72V223, (2,049-m) writes for the IDT72V233, (4,097-m) writes for the IDT72V243, (8,193-m) writes for the IDT72V253, (16,385-m) writes for the IDT72V263, 12 BUS FIFO IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 8K 9/18, 2K 32K 9/18, x 9/18, 9/18,x256K 9/18, 512K64K x9 x 9/18, 128K x 9 512xx18, 18,16K 1K xx 9/18, xx 9/18, 4K64K x 9/18, 8K 128K x 9/18,x 16K 9/18, x32K x 9/18, (32,769-m) writes for the IDT72V273, (65,537-m) writes for the IDT72V283 and (131,073-m) writes for the IDT72V293. The offset m is the full offset value. The default setting for these values are stated in the footnote of Table 2. When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting further write operations. If no reads are performed after a reset, IR will go HIGH after D writes to the FIFO. If x18 Input or x18 Output bus Width is selected, D = 513 writes for the IDT72V223, 1,025 writes for the IDT72V233, 2,049 writes for the IDT72V243, 4,097 writes for the IDT72V253, 8,193 writes for the IDT72V263, 16,385 writes for the IDT72V273, 32,769 writes for the IDT72V283 and 65,537 writes for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, D = 1,025 writes for the IDT72V223, 2,049 writes for the IDT72V233, 4,097 writes for the IDT72V243, 8,193 writes for the IDT72V253, 16,385 writes for the IDT72V263, 32,769 writes for the IDT72V273, 65,537 writes for the IDT72V283 and 131,073 writes for the IDT72V293, respectively. Note that the additional word in FWFT mode is due to the capacity of the memory plus output register. If the FIFO is full, the first read operation will cause the IR flag to go LOW. Subsequent read operations will cause the PAF and HF to go HIGH at the conditions described in Table 4. If further read operations occur, without write operations, the PAE will go LOW when there are n+1 words in the FIFO, where n is the empty offset value. Continuing read operations will cause the FIFO to become empty. When the last word has been read from the FIFO, OR will go HIGH inhibiting further read operations. REN is ignored when the FIFO is empty. When configured in FWFT mode, the OR flag output is triple registerbuffered, and the IR flag output is double register-buffered. Relevant timing diagrams for FWFT mode can be found in Figure 9, 10 and 12. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES be programmed into the FIFO in one of two ways; serial or parallel loading method. The selection of the loading method is done using the LD (Load) pin. During Master Reset, the state of the LD input determines whether serial or parallel flag offset programming is enabled. A HIGH on LD during Master Reset selects serial loading of offset values. A LOW on LD during Master Reset selects parallel loading of offset values. In addition to loading offset values into the FIFO, it is also possible to read the current offset values. Offset values can be read via the parallel output port Q0-Qn, regardless of the programming mode selected (serial or parallel). It is not possible to read the offset values in serial fashion. Figure 3, Programmable Flag Offset Programming Sequence, summaries the control pins and sequence for both serial and parallel programming modes. For a more detailed description, see discussion that follows. The offset registers may be programmed (and reprogrammed) any time after Master Reset, regardless of whether serial or parallel programming has been selected. Valid programming ranges are from 0 to D-1. SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG TIMING SELECTION The IDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/ 72V293 can be configured during the Master Reset cycle with either synchronous or asynchronous timing for PAF and PAE flags by use of the PFM pin. If synchronous PAF/PAE configuration is selected (PFM, HIGH during MRS), the PAF is asserted and updated on the rising edge of WCLK only and not RCLK. Similarly, PAE is asserted and updated on the rising edge of RCLK only and not WCLK. For detail timing diagrams, see Figure 18 for synchronous PAF timing and Figure 19 for synchronous PAE timing. If asynchronous PAF/PAE configuration is selected (PFM, LOW during MRS), the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. Similarly, PAE is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition of WCLK. For detail timing diagrams, see Figure 20 for asynchronous PAF timing and Figure 21 for asynchronous PAE timing. PROGRAMMING FLAG OFFSETS Full and Empty Flag offset values are user programmable. The IDT72V223/ 72V233/72V243/72V253/72V263/72V273/72V283/72V293 has internal registers for these offsets. There are eight default offset values selectable during Master Reset. These offset values are shown in Table 2. Offset values can also TABLE 2 ⎯ DEFAULT PROGRAMMABLE FLAG OFFSETS IDT72V253 IDT72V263 IDT72V273 Offsets n,m IDT72V223 IDT72V233 Offsets n,m LD L L L H H H H L H L FSEL0 FSEL1 L H H L H H L H L L H L H H L L X X X X IDT72V243 Offsets n,m All Other x9 to x9 All Modes Modes Mode 511 511 511 255 255 255 63 63 63 15 15 31 31 31 1,023 7 7 15 3 3 7 127 127 127 Serial Programming Mode(3) Parallel Programming Mode(4) All Modes 511 255 63 31 1,023 15 7 127 IDT72V283 Offsets n,m All Other x9 to x9 Modes Mode 511 16,383 255 8,191 63 4,095 31 2,047 1,023 1,023 15 511 7 255 127 127 NOTES: 1. n = empty offset for PAE. 2. m = full offset for PAF. 3. As well as selecting serial programming mode, one of the default values will also be loaded depending on the state of FSEL0 & FSEL1. 4. As well as selecting parallel programming mode, one of the default values will also be loaded depending on the state of FSEL0 & FSEL1. 13 IDT72V293 Offsets n,m All Modes 16,383 8,191 4,095 2,047 1,023 511 255 127 IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES TABLE 3 ⎯ STATUS FLAGS FOR IDT STANDARD MODE IW = OW = x9 IW ≠ OW or IW = OW = x18 IDT72V223 IDT72V223 IDT72V233 IDT72V243 IDT72V233 IDT72V243 IDT72V253 0 1 to n Number of Words in (2) FIFO 0 1 to n 0 0 1 to n 1 to n H L L H H L H (n+1) to 512 (n+1) to 1,024 (n+1) to 2,048 H H H H H 1,025 to (2,048-(m+1)) 2,049 to (4,096-(m+1)) H H L H H (512-m) to 511 (1,024-m) to 1,023 (2,048-m) to 2,047 H L L H H L L L H H 1,024 2,048 (4,096-m) to 4,095 4,096 IDT72V253 IDT72V263 IDT72V273 IDT72V283 IW ≠ OW or IW = OW = x18 IDT72V263 IDT72V273 IDT72V283 IDT72V293 0 0 1 to n FIFO H H 513 to (1,024-(m+1)) (n+1) to 256 IW = OW = x9 (2) H 257 to (512-(m+1)) 512 Number of Words in FF PAF HF PAE EF FF PAF HF PAE EF 0 0 1 to n IDT72V293 0 1 to n 1 to n 1 to n H H H L L H H H L H (n+1) to 4,096 (n+1) to 8,192 (n+1) to 16,384 (n+1) to 32,768 (n+1) to 65,536 H H H H H 4,097 to (8,192-(m+1)) 8,193 to (16,384-(m+1)) 16,385 to (32,768-(m+1)) 32,769 to (65,536-(m+1)) 65,537 to (131,072-(m+1)) H H L H H (16,384-m) to 16,383 (32,768-m) to 32,767 (65,536-m) to 65,535 16,384 32,768 65,536 (8,192-m) to 8,191 8,192 (131,072-m) to 131,071 131,072 H L L H H L L L H H NOTE: 1. See Table 2 for values for n, m. TABLE 4 ⎯ STATUS FLAGS FOR FWFT MODE IW = OW = x9 IW ≠ OW or IW = OW = x18 Number of Words in FIFO(2) IDT72V223 IDT72V223 IDT72V233 IDT72V243 IDT72V233 IDT72V243 IDT72V253 IR 0 0 0 0 L H H L H 1 to n+1 1 to n+1 1 to n+1 1 to n+1 L H H L L L (n+2) to 513 (n+2) to 1,025 (n+2) to 2,049 L H H H 258 to (513-(m+1)) 514 to (1,025-(m+1)) 1,026 to (2,049-(m+1)) 2,050 to (4,097-(m+1)) L H L H L (513-m) to 512 (1,025-m) to 1,024 (2,049-m) to 2,048 L L L H L H L L H L (n+2) to 257 513 1,025 2,049 (4,097-m) to 4,096 4,097 IW = OW = x9 IDT72V253 IDT72V263 IDT72V273 IDT72V283 IW ≠ OW or IW = OW = x18 IDT72V263 IDT72V273 IDT72V283 IDT72V293 Number of Words in (2) FIFO PAF HF PAE OR IDT72V293 IR PAF HF PAE OR 0 0 0 0 0 L H H L H 1 to n+1 1 to n+1 1 to n+1 1 to n+1 1 to n+1 L H H L L (n+2) to 4,097 (n+2) to 8,193 (n+2) to 16,385 (n+2) to 32,769 (n+2) to 65,537 L H H H L 4,098 to (8,193-(m+1)) 8,194 to (16,385-(m+1)) 16,386 to (32,769-(m+1)) 32,770 to (65,537-(m+1)) 65,538 to (131,073-(m+1)) L H L H L (16,385-m) to 16,384 (32,769-m) to 32,768 (65,537-m) to 65,536 (131,073-m) to 131,072 L L L H L 16,385 32,769 65,537 H L L H (8,193-m) to 8,192 8,193 131,073 L 4666 drw05 NOTE: 1. See Table 2 for values for n, m. 2. Number of Words in FIFO = FIFO Depth + Output Register 14 BUS FIFO IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 8K 9/18, 2K 32K 9/18, x 9/18, 9/18,x256K 9/18, 512K64K x9 x 9/18, 128K x 9 512xx18, 18,16K 1K xx 9/18, xx 9/18, 4K64K x 9/18, 8K 128K x 9/18,x 16K 9/18, x32K x 9/18, 1st Parallel Offset Write/Read Cycle 1st Parallel Offset Write/Read Cycle D/Q8 D/Q8 D/Q0 D/Q0 EMPTY OFFSET REGISTER EMPTY OFFSET REGISTER 8 7 6 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 5 4 3 2 8 1 7 6 5 4 3 2 1 2nd Parallel Offset Write/Read Cycle D/Q8 D/Q0 EMPTY OFFSET REGISTER 2nd Parallel Offset Write/Read Cycle D/Q8 D/Q0 16 15 14 13 12 11 10 9 EMPTY OFFSET REGISTER 16 15 14 13 12 11 10 3rd Parallel Offset Write/Read Cycle 9 D/Q8 D/Q0 EMPTY OFFSET REGISTER 19 3rd Parallel Offset Write/Read Cycle D/Q8 18 17 D/Q0 4th Parallel Offset Write/Read Cycle FULL OFFSET REGISTER 8 7 6 5 4 D/Q8 3 2 D/Q0 FULL OFFSET REGISTER 1 8 D/Q8 13 4 3 2 1 D/Q0 FULL OFFSET REGISTER FULL OFFSET REGISTER 14 5 D/Q8 D/Q0 1 5 6 5th Parallel Offset Write/Read Cycle 4th Parallel Offset Write/Read Cycle 16 7 12 11 10 16 9 15 14 13 12 11 10 9 6th Parallel Offset Write/Read Cycle D/Q8 IDT72V223/72V233/72V243/72V253/72V263/ 72V273/72V283/72V293(2)⎯ x9 Bus Width D/Q0 FULL OFFSET REGISTER 17 1st Parallel Offset Write/Read Cycle D/Q17 D/Q16 Data Inputs/Outputs EMPTY OFFSET REGISTER 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 16 15 14 13 12 11 10 9 D/Q8 IDT72V293(2)⎯ x9 Bus Width D/Q0 # of Bits Used Non-Interspersed Parity Interspersed Parity 2nd Parallel Offset Write/Read Cycle D/Q17 D/Q16 Data Inputs/Outputs D/Q0 FULL OFFSET REGISTER 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D/Q8 x9 to x9 Mode All Other Modes # of Bits Used: 10 bits for the IDT72V223 11 bits for the IDT72V233 12 bits for the IDT72V243 13 bits for the IDT72V253 14 bits for the IDT72V263 15 bits for the IDT72V273 16 bits for the IDT72V283 17 bits for the IDT72V293 # of Bits Used: 9 bits for the IDT72V223 10 bits for the IDT72V233 11 bits for the IDT72V243 12 bits for the IDT72V253 13 bits for the IDT72V263 14 bits for the IDT72V273 15 bits for the IDT72V283 16 bits for the IDT72V293 Note: All unused bits of the LSB & MSB are don't care Note: All unused bits of the LSB & MSB are don't care IDT72V223/72V233/72V243/72V253/72V263/72V273/ 72V283/72V293⎯ x18 Bus Width 4666 drw06 NOTES: 1. When programming the IDT72V293 with an input bus width of x9 and output bus width of x18, 4 write cycles will be required. When Reading the IDT72V293 with an output bus width of x9 and input bus width of x18, 4 read cycles will be required. 2. A total of 6 program/ read cycles will be required for x9 bus width if both the input and output bus widths are set to x9. Figure 3. Programmable Flag Offset Programming Sequence 15 IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 LD WEN REN SEN WCLK 0 0 1 1 0 1 0 1 IDT72V223, IDT72V233 IDT72V243, IDT72V253 IDT72V263, IDT72V273 IDT72V283, IDT72V293 RCLK Parallel write to registers: Empty Offset (LSB) Empty Offset (MSB) Full Offset (LSB) Full Offset (MSB) Parallel read from registers: Empty Offset (LSB) Empty Offset (MSB) Full Offset (LSB) Full Offset (MSB) X X 0 1 1 0 X X 1 1 1 1 0 X X 1 X 0 X X 1 1 1 X X X COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES x9 to x9 Mode Serial shift into registers: 20 bits for the IDT72V223 22 bits for the IDT72V233 24 bits for the IDT72V243 26 bits for the IDT72V253 28 bits for the IDT72V263 30 bits for the IDT72V273 32 bits for the IDT72V283 34 bits for the IDT72V293 1 bit for each rising WCLK edge Starting with Empty Offset (LSB) Ending with Full Offset (MSB) All Other Modes Serial shift into registers: 18 bits for the IDT72V223 20 bits for the IDT72V233 22 bits for the IDT72V243 24 bits for the IDT72V253 26 bits for the IDT72V263 28 bits for the IDT72V273 30 bits for the IDT72V283 32 bits for the IDT72V293 1 bit for each rising WCLK edge Starting with Empty Offset (LSB) Ending with Full Offset (MSB) X No Operation X Write Memory Read Memory X No Operation NOTES: 1. The programming method can only be selected at Master Reset. 2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected. 3. The programming sequence applies to both IDT Standard and FWFT modes. Figure 3. Programmable Flag Offset Programming Sequence (Continued) 16 4666 drw06a BUS FIFO IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 8K 9/18, 2K 32K 9/18, x 9/18, 9/18,x256K 9/18, 512K64K x9 x 9/18, 128K x 9 512xx18, 18,16K 1K xx 9/18, xx 9/18, 4K64K x 9/18, 8K 128K x 9/18,x 16K 9/18, x32K x 9/18, COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES LOW-to-HIGH transition of WCLK. Upon the second LOW-to-HIGH transition of WCLK, data are written into the MSB of the Empty Offset Register. On the third LOW-to-HIGH transition of WCLK, data are written into the LSB of the Full Offset Register. On the fourth LOW-to-HIGH transition of WCLK, data are written into the MSB of the Full Offset Register. The fifth LOW-to-HIGH transition of WCLK, data are written, once again to the Empty Offset Register. Note that for x9 bus width, one extra Write cycle is required for both the Empty Offset Register and Full Offset Register. See Figure 16, Parallel Loading of Programmable Flag Registers, for the timing diagram for this mode. The act of writing offsets in parallel employs a dedicated write offset register pointer. The act of reading offsets employs a dedicated read offset register pointer. The two pointers operate independently; however, a read and a write should not be performed simultaneously to the offset registers. A Master Reset initializes both pointers to the Empty Offset (LSB) register. A Partial Reset has no effect on the position of these pointers. Refer to Figure 3, Programmable Flag Offset Programming Sequence, for a detailed diagram of the data input lines D0-Dn used during parallel programming. Write operations to the FIFO are allowed before and during the parallel programming sequence. In this case, the programming of all offset registers does not have to occur at one time. One, two or more offset registers can be written and then by bringing LD HIGH, write operations can be redirected to the FIFO memory. When LD is set LOW again, and WEN is LOW, the next offset register in sequence is written to. As an alternative to holding WEN LOW and toggling LD, parallel programming can also be interrupted by setting LD LOW and toggling WEN. Note that the status of a programmable flag (PAE or PAF) output is invalid during the programming process. From the time parallel programming has begun, a programmable flag output will not be valid until the appropriate offset word has been written to the register(s) pertaining to that flag. Measuring from the rising WCLK edge that achieves the above criteria; PAF will be valid after two more rising WCLK edges plus tPAF, PAE will be valid after the next two rising RCLK edges plus tPAE plus tSKEW2. The act of reading the offset registers employs a dedicated read offset register pointer. The contents of the offset registers can be read on the Q0-Qn pins when LD is set LOW and REN is set LOW. If the FIFO is configured for an input bus width and output bus width both set to x9, then the total number of read operations required to read the offset registers is 4 for the IDT72V223/72V233/ 72V243/72V253/72V263/72V273/72V283 or 6 for the IDT72V293. Refer to Figure 3, Programmable Flag Offset Programming Sequence, for a detailed diagram of the data input lines D0-Dn used during parallel programming. If the FIFO is configured for an input to output bus width of x9 to x18, x18 to x9 or x18 to x18, then the following number of read operations are required: for an output bus width of x18 a total of 2 read operations will be required to read the offset registers for the IDT72V223/72V233/72V243/72V253/72V263/72V273/ 72V283/72V293. For an output bus width of x9 a total of 4 read operations will be required to read the offset registers for the IDT72V223/72V233/72V243/ 72V253/72V263/72V273/72V283/72V293. Refer to Figure 3, Programmable Flag Offset Programming Sequence, for a detailed diagram. For example, reading PAE and PAF on the IDT72V293 configured for x18 bus width proceeds as follows: data are read via Qn from the Empty Offset Register on the first and second LOW-to-HIGH transition of RCLK. Upon the third and fourth LOW-to-HIGH transition of RCLK, data are read from the Full Offset Register. The fifth and sixth transition of RCLK reads, once again, from the Empty Offset Register. Note that for a x9 bus width, one extra Read cycle is required for both the Empty Offset Register and Full Offset Register. See Figure 17, Parallel Read of Programmable Flag Registers, for the timing diagram for this mode. SERIAL PROGRAMMING MODE If Serial Programming mode has been selected, as described above, then programming of PAE and PAF values can be achieved by using a combination of the LD, SEN, WCLK and SI input pins. Programming PAE and PAF proceeds as follows: when LD and SEN are set LOW, data on the SI input are written, one bit for each WCLK rising edge, starting with the Empty Offset LSB and ending with the Full Offset MSB. If x9 to x9 mode is selected, a total of 20 bits for the IDT72V223, 22 bits for the IDT72V233, 24 bits for the IDT72V243, 26 bits for the IDT72V253, 28 bits for the IDT72V263, 30 bits for the IDT72V273, 32 bits for the IDT72V283 and 34 bits for the IDT72V293. For any other mode of operation (that includes x18 bus width on either the Input or Output), minus 2 bits from the values above. So, a total of 18 bits for the IDT72V223, 20 bits for the IDT72V233, 22 bits for the IDT72V243, 24 bits for the IDT72V253, 26 bits for the IDT72V263, 28 bits for the IDT72V273, 30 bits for the IDT72V283 and 32 bits for the IDT72V293. See Figure 15, Serial Loading of Programmable Flag Registers, for the timing diagram for this mode. Using the serial method, individual registers cannot be programmed selectively. PAE and PAF can show a valid status only after the complete set of bits (for all offset registers) has been entered. The registers can be reprogrammed as long as the complete set of new offset bits is entered. When LD is LOW and SEN is HIGH, no serial write to the registers can occur. Write operations to the FIFO are allowed before and during the serial programming sequence. In this case, the programming of all offset bits does not have to occur at once. A select number of bits can be written to the SI input and then, by bringing LD and SEN HIGH, data can be written to FIFO memory via Dn by toggling WEN. When WEN is brought HIGH with LD and SEN restored to a LOW, the next offset bit in sequence is written to the registers via SI. If an interruption of serial programming is desired, it is sufficient either to set LD LOW and deactivate SEN or to set SEN LOW and deactivate LD. Once LD and SEN are both restored to a LOW level, serial offset programming continues. From the time serial programming has begun, neither programmable flag will be valid until the full set of bits required to fill all the offset registers has been written. Measuring from the rising WCLK edge that achieves the above criteria; PAF will be valid after two more rising WCLK edges plus tPAF, PAE will be valid after the next two rising RCLK edges plus tPAE plus tSKEW2. It is not possible to read the flag offset values in a serial mode. PARALLEL PROGRAMMING MODE If Parallel Programming mode has been selected, as described above, then programming of PAE and PAF values can be achieved by using a combination of the LD, WCLK , WEN and Dn input pins. If the FIFO is configured for an input bus width and output bus width both set to x9, then the total number of write operations required to program the offset registers is 4 for the IDT72V223/ 72V233/72V243/72V253/72V263/72V273/72V283 or 6 for the IDT72V293. Refer to Figure 3, Programmable Flag Offset Programming Sequence, for a detailed diagram of the data input lines D0-Dn used during parallel programming. If the FIFO is configured for an input to output bus width of x9 to x18, x18 to x9 or x18 to x18, then the following number of write operations are required. For an input bus width of x18 a total of 2 write operations will be required to program the offset registers for the IDT72V223/72V233/72V243/72V253/ 72V263/72V273/72V283/72V293. For an input bus width of x9 a total of 4 write operations will be required to program the offset registers for the IDT72V223/ 72V233/72V243/72V253/72V263/72V273/72V283/72V293. Refer to Figure 3, Programmable Flag Offset Programming Sequence, for a detailed diagram. For example, programming PAE and PAF on the IDT72V293 configured for x18 bus width proceeds as follows: when LD and WEN are set LOW, data on the inputs Dn are written into the LSB of the Empty Offset Register on the first 17 IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 It is permissible to interrupt the offset register read sequence with reads or writes to the FIFO. The interruption is accomplished by deasserting REN, LD, or both together. When REN and LD are restored to a LOW level, reading of the offset registers continues where it left off. It should be noted, and care should be taken from the fact that when a parallel read of the flag offsets is performed, the data word that was present on the output lines Qn will be overwritten. Parallel reading of the offset registers is always permitted regardless of which timing mode (IDT Standard or FWFT modes) has been selected. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V253, 16,385 for the IDT72V263, 32,769 for the IDT72V273, 65,537 for the IDT72V283 and 131,073 for the IDT72V293. If IDT Standard mode is selected, the FIFO will mark the beginning of the Retransmit setup by setting EF LOW. The change in level will only be noticeable if EF was HIGH before setup. During this period, the internal read pointer is initialized to the first location of the RAM array. When EF goes HIGH, Retransmit setup is complete and read operations may begin starting with the first location in memory. Since IDT Standard mode is selected, every word read including the first word following Retransmit setup requires a LOW on REN to enable the rising edge of RCLK. See Figure 11, Retransmit Timing (IDT Standard Mode), for the relevant timing diagram. If FWFT mode is selected, the FIFO will mark the beginning of the Retransmit setup by setting OR HIGH. During this period, the internal read pointer is set to the first location of the RAM array. When OR goes LOW, Retransmit setup is complete; at the same time, the contents of the first location appear on the outputs. Since FWFT mode is selected, the first word appears on the outputs, no LOW on REN is necessary. Reading all subsequent words requires a LOW on REN to enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT Mode), for the relevant timing diagram. For either IDT Standard mode or FWFT mode, updating of the PAE, HF and PAF flags begin with the rising edge of RCLK that the RT is setup on. PAE is synchronized to RCLK, thus on the second rising edge of RCLK after RT is setup, the PAE flag will be updated. HF is asynchronous, thus the rising edge of RCLK that RT is setup will update HF. PAF is synchronized to WCLK, thus the second rising edge of WCLK that occurs tSKEW after the rising edge of RCLK that RT is setup will update PAF. RT is synchronized to RCLK. The Retransmit function has the option of 2 modes of operation, either "normal latency" or "zero latency". Figure 11 and Figure 12 mentioned previously, relate to "normal latency". Figure 13 and Figure 14 show "zero latency" retransmit operation. Zero latency basically means that the first data word to be retransmitted, is placed onto the output register with respect to the RCLK pulse that initiated the retransmit. RETRANSMIT OPERATION The Retransmit operation allows data that has already been read to be accessed again. There are 2 modes of Retransmit operation, normal latency and zero latency. There are two stages to Retransmit: first, a setup procedure that resets the read pointer to the first location of memory, then the actual retransmit, which consists of reading out the memory contents, starting at the beginning of memory. Retransmit setup is initiated by holding RT LOW during a rising RCLK edge. REN and WEN must be HIGH before bringing RT LOW. When zero latency is utilized, REN does not need to be HIGH before bringing RT LOW. At least two words, but no more than D - 2 words should have been written into the FIFO, and read from the FIFO, between Reset (Master or Partial) and the time of Retransmit setup. If x18 Input or x18 Output bus Width is selected, D = 512 for the IDT72V223, 1,024 for the IDT72V233, 2,048 for the IDT72V243, 4,096 for the IDT72V253, 8,192 for the IDT72V263, 16,384 for the IDT72V273, 32,768 for the IDT72V283 and 65,536 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, D = 1,024 for the IDT72V223, 2,048 for the IDT72V233, 4,096 for the IDT72V243, 8,192 for the IDT72V253, 16,384 for the IDT72V263, 32,768 for the IDT72V273, 65,536 for the IDT72V283 and 131,072 for the IDT72V293. In FWFT mode, if x18 Input or x18 Output bus Width is selected, D = 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263, 16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, D = 1,025 for the IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the 18 BUS FIFO IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 8K 9/18, 2K 32K 9/18, x 9/18, 9/18,x256K 9/18, 512K64K x9 x 9/18, 128K x 9 512xx18, 18,16K 1K xx 9/18, xx 9/18, 4K64K x 9/18, 8K 128K x 9/18,x 16K 9/18, x32K x 9/18, SIGNAL DESCRIPTION INPUTS: COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Asynchronous operation of the read port will be selected. During Asynchronous operation of the read port the RCLK input becomes RD input, this is the Asynchronous read strobe input. A rising edge on RD will read data from the FIFO via the output register and Qn port. (REN must be tied LOW during Asynchronous operation of the read port). The OE input provides three-state control of the Qn output bus, in an asynchronous manner. When the read port is configured for Asynchronous operation the device must be operating on IDT standard mode, FWFT mode is not permissible if the read port is Asynchronous. The Empty Flag (EF) operates in an Asynchronous manner, that is, the empty flag will be updated based on both a read operation and a write operation. Refer to figures 25, 26, 27 and 28 for relevant timing and operational waveforms. DATA IN (D0 - Dn) Data inputs for 18-bit wide data (D0-D17) or data inputs for 9-bit wide data (D0-D8). CONTROLS: MASTER RESET (MRS) A Master Reset is accomplished whenever the MRS input is taken to a LOW state. This operation sets the internal read and write pointers to the first location of the RAM array. PAE will go LOW, PAF will go HIGH, and HF will go HIGH. If FWFT/SI is LOW during Master Reset then the IDT Standard mode, along with EF and FF are selected. EF will go LOW and FF will go HIGH. If FWFT/ SI is HIGH, then the First Word Fall Through mode (FWFT), along with IR and OR, are selected. OR will go HIGH and IR will go LOW. All control settings such as OW, IW, BE, RM, PFM and IP are defined during the Master Reset cycle. During a Master Reset, the output register is initialized to all zeroes. A Master Reset is required after power up, before a write operation can take place. MRS is asynchronous. See Figure 5, Master Reset Timing, for the relevant timing diagram. RETRANSMIT (RT) The Retransmit operation allows data that has already been read to be accessed again. There are 2 modes of Retransmit operation, normal latency and zero latency. There are two stages to Retransmit: first, a setup procedure that resets the read pointer to the first location of memory, then the actual retransmit, which consists of reading out the memory contents, starting at the beginning of the memory. Retransmit setup is initiated by holding RT LOW during a rising RCLK edge. REN and WEN must be HIGH before bringing RT LOW. When zero latency is utilized, REN does not need to be HIGH before bringing RT LOW. If IDT Standard mode is selected, the FIFO will mark the beginning of the Retransmit setup by setting EF LOW. The change in level will only be noticeable if EF was HIGH before setup. During this period, the internal read pointer is initialized to the first location of the RAM array. When EF goes HIGH, Retransmit setup is complete and read operations may begin starting with the first location in memory. Since IDT Standard mode is selected, every word read including the first word following Retransmit setup requires a LOW on REN to enable the rising edge of RCLK. See Figure 11, Retransmit Timing (IDT Standard Mode), for the relevant timing diagram. If FWFT mode is selected, the FIFO will mark the beginning of the Retransmit setup by setting OR HIGH. During this period, the internal read pointer is set to the first location of the RAM array. When OR goes LOW, Retransmit setup is complete; at the same time, the contents of the first location appear on the outputs. Since FWFT mode is selected, the first word appears on the outputs, no LOW on REN is necessary. Reading all subsequent words requires a LOW on REN to enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT Mode), for the relevant timing diagram. In Retransmit operation, zero-latency mode can be selected using the Retransmit Mode (RM) pin during a Master Reset. This can be applied to both IDT Standard mode and FWFT mode. PARTIAL RESET (PRS) A Partial Reset is accomplished whenever the PRS input is taken to a LOW state. As in the case of the Master Reset, the internal read and write pointers are set to the first location of the RAM array, PAE goes LOW, PAF goes HIGH, and HF goes HIGH. Whichever mode is active at the time of Partial Reset, IDT Standard mode or First Word Fall Through, that mode will remain selected. If the IDT Standard mode is active, then FF will go HIGH and EF will go LOW. If the First Word Fall Through mode is active, then OR will go HIGH, and IR will go LOW. Following Partial Reset, all values held in the offset registers remain unchanged. The programming method (parallel or serial) currently active at the time of Partial Reset is also retained. The output register is initialized to all zeroes. PRS is asynchronous. A Partial Reset is useful for resetting the device during the course of operation, when reprogramming programmable flag offset settings may not be convenient. See Figure 6, Partial Reset Timing, for the relevant timing diagram. ASYNCHRONOUS WRITE (ASYW) The write port can be configured for either Synchronous or Asynchronous mode of operation. If during Master Reset the ASYW input is LOW, then Asynchronous operation of the write port will be selected. During Asynchronous operation of the write port the WCLK input becomes WR input, this is the Asynchronous write strobe input. A rising edge on WR will write data present on the Dn inputs into the FIFO. (WEN must be tied LOW when using the write port in Asynchronous mode). When the write port is configured for Asynchronous operation the full flag (FF) operates in an asynchronous manner, that is, the full flag will be updated based in both a write operation and read operation. Note, if Asynchronous mode is selected, FWFT is not permissable. Refer to Figures 23, 24, 27 and 28 for relevant timing and operational waveforms. RETRANSMIT LATENCY MODE (RM) A zero-latency retransmit timing mode can be selected using the Retransmit timing Mode pin (RM). During Master Reset, a LOW on RM will select zerolatency retransmit. A HIGH on RM during Master Reset will select normal latency. If zero-latency retransmit operation is selected the first data word to be retransmitted will be placed on the output register with respect to the same RCLK edge that initiated the retransmit based on RT being LOW. Refer to Figure 13 for Retransmit Timing with zero latency (IDT Standard Mode). Refer to Figure 14 for Retransmit Timing with zero latency (FWFT Mode). ASYNCHRONOUS READ (ASYR) The read port can be configured for either Synchronous or Asynchronous mode of operation. If during a Master Reset the ASYR input is LOW, then 19 IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI) This is a dual purpose pin. During Master Reset, the state of the FWFT/ SI input determines whether the device will operate in IDT Standard mode or First Word Fall Through (FWFT) mode. If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode will be selected. This mode uses the Empty Flag (EF) to indicate whether or not there are any words present in the FIFO memory. It also uses the Full Flag function (FF) to indicate whether or not the FIFO memory has any free space for writing. In IDT Standard mode, every word read from the FIFO, including the first, must be requested using the Read Enable (REN) and RCLK. If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be selected. This mode uses Output Ready (OR) to indicate whether or not there is valid data at the data outputs (Qn). It also uses Input Ready (IR) to indicate whether or not the FIFO memory has any free space for writing. In the FWFT mode, the first word written to an empty FIFO goes directly to Qn after three RCLK rising edges, REN = LOW is not necessary. Subsequent words must be accessed using the Read Enable (REN) and RCLK. After Master Reset, FWFT/SI acts as a serial input for loading PAE and PAF offsets into the programmable registers. The serial input function can only be used when the serial loading method has been selected during Master Reset. Serial programming using the FWFT/SI pin functions the same way in both IDT Standard and FWFT modes. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES It is permissible to stop the RCLK. Note that while RCLK is idle, the EF/OR, PAE and HF flags will not be updated. (Note that RCLK is only capable of updating the HF flag to HIGH). The Write and Read Clocks can be independent or coincident. If Asynchronous operation has been selected this input is RD (Read Strobe) . Data is Asynchronously read from the FIFO via the output register whenever there is a rising edge on RD. In this mode the REN input must be tied LOW. The OE input is used to provide Asynchronous control of the threestate Qn outputs. READ ENABLE (REN) When Read Enable is LOW, data is loaded from the RAM array into the output register on the rising edge of every RCLK cycle if the device is not empty. When the REN input is HIGH, the output register holds the previous data and no new data is loaded into the output register. The data outputs Q0-Qn maintain the previous data value. In the IDT Standard mode, every word accessed at Qn, including the first word written to an empty FIFO, must be requested using REN. When the last word has been read from the FIFO, the Empty Flag (EF) will go LOW, inhibiting further read operations. REN is ignored when the FIFO is empty. Once a write is performed, EF will go HIGH allowing a read to occur. The EF flag is updated by two RCLK cycles + tSKEW after the valid WCLK cycle. In the FWFT mode, the first word written to an empty FIFO automatically goes to the outputs Qn, on the third valid LOW to HIGH transition of RCLK + tSKEW after the first write. REN does not need to be asserted LOW. In order to access all other words, a read must be executed using REN. The RCLK LOW to HIGH transition after the last word has been read from the FIFO, Output Ready (OR) will go HIGH with a true read (RCLK with REN = LOW), inhibiting further read operations. REN is ignored when the FIFO is empty. If Asynchronous operation of the Read port has been selected, then REN must be held active, (tied LOW). WRITE STROBE & WRITE CLOCK (WR/WCLK) If Synchronous operation of the write port has been selected via ASYW, this input behaves as WCLK. A write cycle is initiated on the rising edge of the WCLK input. Data setup and hold times must be met with respect to the LOW-to-HIGH transition of the WCLK. It is permissible to stop the WCLK. Note that while WCLK is idle, the FF/ IR, PAF and HF flags will not be updated. (Note that WCLK is only capable of updating HF flag to LOW). The Write and Read Clocks can either be independent or coincident. If Asynchronous operation has been selected this input is WR (write strobe). Data is Asynchronously written into the FIFO via the Dn inputs whenever there is a rising edge on WR. In this mode the WEN input must be tied LOW. SERIAL ENABLE (SEN) The SEN input is an enable used only for serial programming of the offset registers. The serial programming method must be selected during Master Reset. SEN is always used in conjunction with LD. When these lines are both LOW, data at the SI input can be loaded into the program register one bit for each LOW-to-HIGH transition of WCLK. When SEN is HIGH, the programmable registers retains the previous settings and no offsets are loaded. SEN functions the same way in both IDT Standard and FWFT modes. WRITE ENABLE (WEN) When the WEN input is LOW, data may be loaded into the FIFO RAM array on the rising edge of every WCLK cycle if the device is not full. Data is stored in the RAM array sequentially and independently of any ongoing read operation. When WEN is HIGH, no new data is written in the RAM array on each WCLK cycle. To prevent data overflow in the IDT Standard mode, FF will go LOW, inhibiting further write operations. Upon the completion of a valid read cycle, FF will go HIGH allowing a write to occur. The FF is updated by two WCLK cycles + tSKEW after the RCLK cycle. To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting further write operations. Upon the completion of a valid read cycle, IR will go LOW allowing a write to occur. The IR flag is updated by two WCLK cycles + tSKEW after the valid RCLK cycle. WEN is ignored when the FIFO is full in either FWFT or IDT Standard mode. If Asynchronous operation of the Read port has been selected, then WEN must be held active, (tied LOW). OUTPUT ENABLE (OE) When Output Enable is enabled (LOW), the parallel output buffers receive data from the output register. When OE is HIGH, the output data bus (Qn) goes into a high impedance state. LOAD (LD) This is a dual purpose pin. During Master Reset, the state of the LD input, along with FSEL0 and FSEL1, determines one of eight default offset values for the PAE and PAF flags, along with the method by which these offset registers can be programmed, parallel or serial (see Table 2). After Master Reset, LD enables write operations to and read operations from the offset registers. Only the offset loading method currently selected can be used to write to the registers. Offset registers can be read only in parallel. After Master Reset, the LD pin is used to activate the programming process of the flag offset values PAE and PAF. Pulling LD LOW will begin a serial loading or parallel load or read of these offset values. READ STROBE & READ CLOCK (RD/RCLK) If Synchronous operation of the read port has been selected via ASYR, this input behaves as RCLK. A read cycle is initiated on the rising edge of the RCLK input. Data can be read on the outputs, on the rising edge of the RCLK input. 20 BUS FIFO IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 8K 9/18, 2K 32K 9/18, x 9/18, 9/18,x256K 9/18, 512K64K x9 x 9/18, 128K x 9 512xx18, 18,16K 1K xx 9/18, xx 9/18, 4K64K x 9/18, 8K 128K x 9/18,x 16K 9/18, x32K x 9/18, BUS-MATCHING (IW, OW) The pins IW and OW are used to define the input and output bus widths. During Master Reset, the state of these pins is used to configure the device bus sizes. See Table 1 for control settings. All flags will operate based on the word/ byte size boundary as defined by the selection of the widest input or output bus width. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1,024 for the IDT72V233, 2,048 for the IDT72V243, 4,096 for the IDT72V253, 8,192 for the IDT72V263, 16,384 for the IDT72V273, 32,768 for the IDT72V283 and 65,536 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, D = 1,024 for the IDT72V223, 2,048 for the IDT72V233, 4,096 for the IDT72V243, 8,192 for the IDT72V253, 16,384 for the IDT72V263, 32,768 for the IDT72V273, 65,536 for the IDT72V283 and 131,072 for the IDT72V293. See Figure 7, Write Cycle and Full Flag Timing (IDT Standard Mode), for the relevant timing information. In FWFT mode, the Input Ready (IR) function is selected. IR goes LOW when memory space is available for writing in data. When there is no longer any free space left, IR goes HIGH, inhibiting further write operations. If no reads are performed after a reset (either MRS or PRS), IR will go HIGH after D writes to the FIFO. If x18 Input or x18 Output bus Width is selected, D = 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263, 16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, D = 1,025 for the IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the IDT72V253, 16,385 for the IDT72V263, 32,769 for the IDT72V273, 65,537 for the IDT72V283 and 131,073 for the IDT72V293. See Figure 9, Write Timing (FWFT Mode), for the relevant timing information. The IR status not only measures the contents of the FIFO memory, but also counts the presence of a word in the output register. Thus, in FWFT mode, the total number of writes necessary to deassert IR is one greater than needed to assert FF in IDT Standard mode. FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR are double register-buffered outputs. BIG-ENDIAN/LITTLE-ENDIAN (BE) During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset will select Little-Endian format. This function is useful when data is written into the FIFO in word format (x18) and read out of the FIFO in word format (x18) or byte format (x9). If Big-Endian mode is selected, then the most significant byte of the word written into the FIFO will be read out of the FIFO first, followed by the least significant byte. If Little-Endian format is selected, then the least significant byte of the word written into the FIFO will be read out first, followed by the most significant byte. The mode desired is configured during master reset by the state of the Big-Endian (BE) pin. Refer to Figure 4, BusMatching Byte Arrangement, for a diagram showing the byte arrangement. PROGRAMMABLE FLAG MODE (PFM) During Master Reset During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on PFM will select Synchronous Programmable flag timing mode. If asynchronous PAF/PAE configuration is selected (PFM, LOW during MRS), the PAE is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOW-toHIGH transition of WCLK. Similarly, the PAF is asserted LOW on the LOW-toHIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. If synchronous PAE/PAF configuration is selected (PFM, HIGH during MRS) , the PAE is asserted and updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK only and not RCLK. The mode desired is configured during master reset by the state of the Programmable Flag Mode (PFM) pin. EMPTY FLAG (EF/OR) This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (EF) function is selected. When the FIFO is empty, EF will go LOW, inhibiting further read operations. When EF is HIGH, the FIFO is not empty. See Figure 8, Read Cycle, Empty Flag and First Word Latency Timing (IDT Standard Mode), for the relevant timing information. In FWFT mode, the Output Ready (OR) function is selected. OR goes LOW at the same time that the first word written to an empty FIFO appears valid on the outputs. OR stays LOW after the RCLK LOW to HIGH transition that shifts the last word from the FIFO memory to the outputs. OR goes HIGH only with a true read (RCLK with REN = LOW). The previous data stays at the outputs, indicating the last word was read. Further data reads are inhibited until OR goes LOW again. See Figure 10, Read Timing (FWFT Mode), for the relevant timing information. EF/OR is synchronous and updated on the rising edge of RCLK. In IDT Standard mode, EF is a double register-buffered output. In FWFT mode, OR is a triple register-buffered output. INTERSPERSED PARITY (IP) During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed Parity mode. The IP bit function allows the user to select the parity bit in the word loaded into the parallel port (D0-Dn) when programming the flag offsets. If Interspersed Parity mode is selected, then the FIFO will assume that the parity bit is located in bit position D8 and D17 during the parallel programming of the flag offsets, and will therefore ignore D8 when loading the offset register in parallel mode. This is also applied to the output register when reading the value of the offset register. If Interspersed Parity is selected then output Q8 will be invalid. If Non-Interspersed Parity mode is selected, then D16 and D17 are the parity bits and are ignored during parallel programming of the offsets. (D8 becomes a valid bit). Additionally, output Q8 will become a valid bit when performing a read of the offset register. IP mode is selected during Master Reset by the state of the IP input pin. Interspersed Parity control only has an effect during parallel programming of the offset registers. It does not effect the data written to and read from the FIFO. PROGRAMMABLE ALMOST-FULL FLAG (PAF) The Programmable Almost-Full flag (PAF) will go LOW when the FIFO reaches the almost-full condition. In IDT Standard mode, if no reads are performed after reset (MRS), PAF will go LOW after (D-m) words are written to the FIFO. If x18 Input or x18 Output bus Width is selected, (D-m) = (512-m) writes for the IDT72V223, (1,024-m) writes for the IDT72V233, (2,048-m) writes for the IDT72V243, (4,096-m) writes for the IDT72V253, (8,192-m) writes for the IDT72V263, (16,384-m) writes for the IDT72V273, (32,768-m) writes for the IDT72V283 and (65,536-m) writes for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, (D-m) = (1,024-m) writes for the IDT72V223, (2,048-m) writes for the IDT72V233, (4,096-m) writes for the IDT72V243, (8,192-m) writes for the IDT72V253, (16,384-m) writes for the OUTPUTS: FULL FLAG (FF/IR) This is a dual purpose pin. In IDT Standard mode, the Full Flag (FF) function is selected. When the FIFO is full, FF will go LOW, inhibiting further write operations. When FF is HIGH, the FIFO is not full. If no reads are performed after a reset (either MRS or PRS), FF will go LOW after D writes to the FIFO. If x18 Input or x18 Output bus Width is selected, D = 512 for the IDT72V223, 21 IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES configuration is selected, the PAE is updated on the rising edge of RCLK. See Figure 21, Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Mode), for the relevant timing information. IDT72V263, (32,768-m) writes for the IDT72V273, (65,536-m) writes for the IDT72V283 and (131,072-m) writes for the IDT72V293. The offset “m” is the full offset value. The default setting for this value is stated in Table 2. In FWFT mode, if x18 Input or x18 Output bus Width is selected, the PAF will go LOW after (513-m) writes for the IDT72V223, (1,025-m) writes for the IDT72V233, (2,049-m) writes for the IDT72V243, (4,097-m) writes for the IDT72V253, (8,193-m) writes for the IDT72V263, (16,385-m) writes for the IDT72V273, (32,769-m) writes for the IDT72V283 and (65,537-m) writes for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, the PAF will go LOW after (1,025-m) writes for the IDT72V223, (2,049-m) writes for the IDT72V233, (4,097-m) writes for the IDT72V243, (8,193-m) writes for the IDT72V253, (16,385-m) writes for the IDT72V263, (32,769-m) writes for the IDT72V273, (65,537-m) writes for the IDT72V283 and (131,073-m) writes for the IDT72V293. The offset m is the full offset value. The default setting for this value is stated in Table 2. See Figure 18, Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Mode), for the relevant timing information. If asynchronous PAF configuration is selected, the PAF is asserted LOW on the LOW-to-HIGH transition of the Write Clock (WCLK). PAF is reset to HIGH on the LOW-to-HIGH transition of the Read Clock (RCLK). If synchronous PAF configuration is selected, the PAF is updated on the rising edge of WCLK. See Figure 20 for Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Mode). HALF-FULL FLAG (HF) This output indicates a half-full FIFO. The rising WCLK edge that fills the FIFO beyond half-full sets HF LOW. The flag remains LOW until the difference between the write and read pointers becomes less than or equal to half of the total depth of the device; the rising RCLK edge that accomplishes this condition sets HF HIGH. In IDT Standard mode, if no reads are performed after reset (MRS or PRS), HF will go LOW after (D/2 + 1) writes to the FIFO. If x18 Input or x18 Output bus Width is selected, D = 512 for the IDT72V223, 1,024 for the IDT72V233, 2,048 for the IDT72V243, 4,096 for the IDT72V253, 8,192 for the IDT72V263, 16,384 for the IDT72V273, 32,768 for the IDT72V283 and 65,536 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, D = 1,024 for the IDT72V223, 2,048 for the IDT72V233, 4,096 for the IDT72V243, 8,192 for the IDT72V253, 16,384 for the IDT72V263, 32,768 for the IDT72V273, 65,536 for the IDT72V283 and 131,072 for the IDT72V293. In FWFT mode, if no reads are performed after reset (MRS or PRS), HF will go LOW after (D-1/2 + 2) writes to the FIFO. If x18 Input or x18 Output bus Width is selected, D = 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263, 16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, D = 1,025 for the IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the IDT72V253, 16,385 for the IDT72V263, 32,769 for the IDT72V273, 65,537 for the IDT72V283 and 131,073 for the IDT72V293. See Figure 22, Half-Full Flag Timing (IDT Standard and FWFT Mode), for the relevant timing information. Because HF is updated by both RCLK and WCLK, it is considered asynchronous. PROGRAMMABLE ALMOST-EMPTY FLAG (PAE) The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO reaches the almost-empty condition. In IDT Standard mode, PAE will go LOW when there are n words or less in the FIFO. The offset “n” is the empty offset value. The default setting for this value is stated in Table 2. In FWFT mode, the PAE will go LOW when there are n+1 words or less in the FIFO. The default setting for this value is stated in Table 2. See Figure 19, Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Mode), for the relevant timing information. If asynchronous PAE configuration is selected, the PAE is asserted LOW on the LOW-to-HIGH transition of the Read Clock (RCLK). PAE is reset to HIGH on the LOW-to-HIGH transition of the Write Clock (WCLK). If synchronous PAE DATA OUTPUTS (Q0-Qn) (Q0 - Q17) data outputs for 18-bit wide data or (Q0 - Q8) data outputs for 9bit wide data. 22 BUS FIFO IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 8K 9/18, 2K 32K 9/18, x 9/18, 9/18,x256K 9/18, 512K64K x9 x 9/18, 128K x 9 512xx18, 18,16K 1K xx 9/18, xx 9/18, 4K64K x 9/18, 8K 128K x 9/18,x 16K 9/18, x32K x 9/18, BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT: BE IW OW L L L BE IW OW H L L D17-D9 D8-D0 A B Q17-Q9 Q8-Q0 A B COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Write to FIFO Read from FIFO (a) x18 INPUT to x18 OUTPUT - BIG ENDIAN Q17-Q9 Q8-Q0 B A Read from FIFO (b) x18 INPUT to x18 OUTPUT - LITTLE ENDIAN Q17-Q9 BE IW OW L L H Q8-Q0 A Q17-Q9 1st: Read from FIFO Q8-Q0 B 2nd: Read from FIFO (c) x18 INPUT to x9 OUTPUT - BIG ENDIAN Q17-Q9 BE IW OW H L H Q8-Q0 B Q17-Q9 1st: Read from FIFO Q8-Q0 A 2nd: Read from FIFO (d) x18 INPUT to x9 OUTPUT - LITTLE ENDIAN BYTE ORDER ON INPUT PORT: D17-D9 D8-D0 A D17-Q9 D8-Q0 B BYTE ORDER ON OUTPUT PORT: BE IW OW L H L 1st: Write to FIFO Q17-Q9 Q8-Q0 A B 2nd: Write to FIFO Read from FIFO (a) x9 INPUT to x18 OUTPUT - BIG ENDIAN BE IW OW H H L Q17-Q9 Q8-Q0 B A Read from FIFO (a) x9 INPUT to x18 OUTPUT - LITTLE ENDIAN 4666 drw07 Figure 4. Bus-Matching Byte Arrangement 23 IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES tRS MRS tRSS tRSR tRSS tRSR tRSS tRSR tRSS tRSR REN WEN FWFT/SI LD tRSS ASYW, ASYR tRSS FSEL0, FSEL1 tRSS OW, IW tRSS BE tRSS RM tRSS PFM tRSS IP tRSS RT tRSS SEN tRSF If FWFT = HIGH, OR = HIGH EF/OR If FWFT = LOW, EF = LOW tRSF If FWFT = LOW, FF = HIGH FF/IR If FWFT = HIGH, IR = LOW tRSF PAE tRSF PAF, HF tRSF OE = HIGH Q0 - Qn OE = LOW Figure 5. Master Reset Timing 24 4666 drw 08 BUS FIFO IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 8K 9/18, 2K 32K 9/18, x 9/18, 9/18,x256K 9/18, 512K64K x9 x 9/18, 128K x 9 512xx18, 18,16K 1K xx 9/18, xx 9/18, 4K64K x 9/18, 8K 128K x 9/18,x 16K 9/18, x32K x 9/18, COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES tRS PRS tRSS tRSR REN tRSS tRSR WEN tRSS RT tRSS SEN If FWFT = HIGH, OR = HIGH tRSF EF/OR If FWFT = LOW, EF = LOW If FWFT = LOW, FF = HIGH tRSF FF/IR If FWFT = HIGH, IR = LOW tRSF PAE tRSF PAF, HF tRSF OE = HIGH Q0 - Qn OE = LOW Figure 6. Partial Reset Timing 25 4666 drw09 IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES tCLK tCLKH NO WRITE WCLK tCLKL NO WRITE 2 1 1 tSKEW1(1) tDS D0 - Dn tDH 2 tSKEW1(1) tDH tDS DX DX+1 tWFF tWFF tWFF tWFF FF WEN RCLK tENS tENS tENH tENH REN tA tA Q0 - Qn DATA IN OUTPUT REGISTER NEXT DATA READ DATA READ 4666 drw10 NOTES: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus tWFF). If the time between the rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle. 2. LD = HIGH, EF = HIGH Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode) tCLK tCLKH RCLK 1 tENS tCLKL 2 tENS tENH REN tENH tENS tENH NO OPERATION NO OPERATION tREF tREF tREF EF tA tA Q0 - Qn LAST WORD tOLZ LAST WORD D1 tOLZ tOHZ tOE tA D0 OE tSKEW1(1) WCLK tENS tENH tENS tDHS tDS tENH WEN tDS D0 - Dn D0 tDH D1 4666 drw11 NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle. 2. LD = HIGH. 3. First data word latency: tSKEW1 + 1*TRCLK + tREF. Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode) 26 27 tDS tENS W1 W2 2 DATA IN OUTPUT REGISTER 1 tSKEW1(1) tDH W3 3 tREF tA W4 tDS W1 W[n +2] W[n+3] 1 tSKEW2 (2) 2 tPAES W[n+4] W[ D-1 ] tDS W[ D-1 ] tHF W[ D-1 ] W[D-m-2] tDS W[D-m-1] W[D-m] 1 W[D-m+1] 2 tPAFS W[D-m+2] W[D-1] WD 4666 drw12 tWFF tENH Figure 9. Write Timing and First Data Word Latency Timing (First Word Fall Through Mode) NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that OR will go LOW after two RCLK cycles plus tREF. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then OR assertion may be delayed one extra RCLK cycle. 2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH after one RCLK cycle plus tPAES. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle. 3. LD = HIGH, OE = LOW 4. n = PAE offset, m = PAF offset and D = maximum FIFO depth. 5. If x18 Input or x18 Output bus Width is selected, D = 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263, 16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, D = 1,025 for the IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the IDT72V253, 16,385 for the IDT72V263, 32,769 for the IDT72V273, 65,537 for the IDT72V283 and 131,073 for the IDT72V293. 6. First data word latency: tSKEW1 + 2*TRCLK + tREF. IR PAF HF PAE OR Q0 - Q17 REN RCLK D0 - D17 WEN WCLK BUS FIFO IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 8K 9/18, 2K 32K 9/18, x 9/18, 9/18,x256K 9/18, 512K64K x9 x 9/18, 128K x 9 512xx18, 18,16K 1K xx 9/18, xx 9/18, 4K64K x 9/18, 8K 128K x 9/18,x 16K 9/18, x32K x 9/18, COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 28 tDS tENS W1 tOHZ WD tENS tWFF tDH tENH W1 tOE tA W2 1 (1) tSKEW1 tA 2 tWFF W3 (2) Wm+2 tSKEW2 W[m+3] tA tPAFS W[m+4] W[ D-1 ] tHF W[ tA D-1 ] W[D-n-1] tA W[D-n] 1 W[D-n+1] 2 tPAES W[D-n+2] W[D-1] tA tENS WD 4666 drw13 tREF Figure 10. Read Timing (First Word Fall Through Mode) NOTES: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that IR will go LOW after one WCLK cycle plus tWFF. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then the IR assertion may be delayed one extra WCLK cycle. 2. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH after one WCLK cycle plus tPAFS. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion may be delayed one extra WCLK cycle. 3. LD = HIGH 4. n = PAE Offset, m = PAF offset and D = maximum FIFO depth. 5. If x18 Input or x18 Output bus Width is selected, D = 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263, 16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, D = 1,025 for the IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the IDT72V253, 16,385 for the IDT72V263, 32,769 for the IDT72V273, 65,537 for the IDT72V283 and 131,073 for the IDT72V293. IR PAF HF PAE OR Q0 - Q17 OE REN RCLK D0 - D17 WEN WCLK IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES BUS FIFO IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 8K 9/18, 2K 32K 9/18, x 9/18, 9/18,x256K 9/18, 512K64K x9 x 9/18, 128K x 9 512xx18, 18,16K 1K xx 9/18, xx 9/18, 4K64K x 9/18, 8K 128K x 9/18,x 16K 9/18, x32K x 9/18, 2 1 RCLK tENS tENH COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES tENS tRTS tENH REN tA Q0 - Qn tA Wx tA W1(3) Wx+1 W2(3) tSKEW2 1 WCLK 2 tRTS WEN tENS tENH RT tREF tREF EF tPAES PAE tHF HF tPAFS PAF 4666 drw14 NOTES: 1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin. 2. OE = LOW. 3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset. 4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure. If x18 Input or x18 Output bus Width is selected, D = 512 for the IDT72V223, 1,024 for the IDT72V233, 2,048 for the IDT72V243, 4,096 for the IDT72V253, 8,192 for the IDT72V263, 16,384 for the IDT72V273, 32,768 for the IDT72V283 and 65,536 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, D = 1,024 for the IDT72V223, 2,048 for the IDT72V233, 4,096 for the IDT72V243, 8,192 for the IDT72V253, 16,384 for the IDT72V263, 32,768 for the IDT72V273, 65,536 for the IDT72V283 and 131,072 for the IDT72V293. 5. There must be at least two words written to and two words read from the FIFO before a Retransmit operation can be invoked. 6. RM is set HIGH during MRS. Figure 11. Retransmit Timing (IDT Standard Mode) 29 IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 1 RCLK tENH tENS COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 3 2 4 tENH tENS tRTS REN tA Q0 - Qn tA tA (4) Wx+1 Wx W1 W2 (4) tA W3(4) W4 tSKEW2 1 WCLK 2 tRTS WEN tENS tENH RT tREF tREF OR tPAES PAE tHF HF tPAFS PAF 4666 drw15 NOTES: 1. Retransmit setup is complete after OR returns LOW. 2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure. If x18 Input or x18 Output bus Width is selected, D = 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263, 16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, D = 1,025 for the IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the IDT72V253, 16,385 for the IDT72V263, 32,769 for the IDT72V273, 65,537 for the IDT72V283 and 131,073 for the IDT72V293. 3. OE = LOW 4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset. 5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked. 6. RM is set HIGH during MRS. Figure 12. Retransmit Timing (FWFT Mode) 30 BUS FIFO IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 8K 9/18, 2K 32K 9/18, x 9/18, 9/18,x256K 9/18, 512K64K x9 x 9/18, 128K x 9 512xx18, 18,16K 1K xx 9/18, xx 9/18, 4K64K x 9/18, 8K 128K x 9/18,x 16K 9/18, x32K x 9/18, RCLK 2 1 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 3 tENH tENS REN Q0 - Qn tA tA tA Wx W1(3) Wx+1 tA W2(3) tA W3(3) W4 tSKEW2 1 WCLK 2 tRTS WEN tENS tENH RT EF(1) tPAES PAE tHF HF tPAFS PAF 4666 drw16 NOTES: 1. If the part is empty at the point of Retransmit, the Empty Flag (EF) will be updated based on RCLK (Retransmit clock cycle). Valid data will also appear on the output. 2. OE = LOW: enables data to be read on outputs Q0-Qn. 3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset. 4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure. If x18 Input or x18 Output bus Width is selected, D = 512 for the IDT72V223, 1,024 for the IDT72V233, 2,048 for the IDT72V243, 4,096 for the IDT72V253, 8,192 for the IDT72V263, 16,384 for the IDT72V273, 32,768 for the IDT72V283 and 65,536 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, D = 1,024 for the IDT72V223, 2,048 for the IDT72V233, 4,096 for the IDT72V243, 8,192 for the IDT72V253, 16,384 for the IDT72V263, 32,768 for the IDT72V273, 65,536 for the IDT72V283 and 131,072 for the IDT72V293. 5. There must be at least two words written to and read from the FIFO before a Retransmit operation can be invoked. 6. RM is set LOW during MRS. Figure 13. Zero Latency Retransmit Timing (IDT Standard Mode) 31 IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 RCLK 2 1 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 4 3 5 tENH tENS REN tA Q0 - Qn Wx tA Wx+1 tA tA W1 W2 (3) W3 tA (3) W4 (3) W5 tSKEW2 1 WCLK 2 tRTS WEN tENS tENH RT OR tPAES PAE tHF HF tPAFS PAF 4666 drw17 NOTES: 1. If the part is empty at the point of Retransmit, the output ready flag (OR), will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output. 2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure. If x18 Input or x18 Output bus Width is selected, D = 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263, 16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, D = 1,025 for the IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the IDT72V253, 16,385 for the IDT72V263, 32,769 for the IDT72V273, 65,537 for the IDT72V283 and 131,073 for the IDT72V293. 3. OE = LOW 4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset. 5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked. 6. RM is set LOW during MRS. Figure 14. Zero Latency Retransmit Timing (FWFT Mode) WCLK tENS tENH tENH SEN tLDS tLDH tLDH LD tDS SI tDH BIT X(1) BIT 0 BIT X(1) BIT 0 FULL OFFSET EMPTY OFFSET 4666 drw18 NOTES: 1. x9 to x9 mode: X = 9 for the IDT72V223, X = 10 for the IDT72V233, X = 11 for the IDT72V243, X = 12 for the IDT72V253, X = 13 for the IDT72V263, X = 14 for the IDT72V273, X = 15 for the IDT72V283 and X = 16 for the IDT72V293. 2. All other modes: X = 8 for the IDT72V223, X = 9 for the IDT72V233, X = 10 for the IDT72V243, X = 11 for the IDT72V253, X = 12 for the IDT72V263, X = 13 for the IDT72V273, X = 14 for the IDT72V283 and X = 15 for the IDT72V293. Figure 15. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes) 32 BUS FIFO IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 8K 9/18, 2K 32K 9/18, x 9/18, 9/18,x256K 9/18, 512K64K x9 x 9/18, 128K x 9 512xx18, 18,16K 1K xx 9/18, xx 9/18, 4K64K x 9/18, 8K 128K x 9/18,x 16K 9/18, x32K x 9/18, COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES tCLK tCLKH tCLKL WCLK tLDS tLDH tLDH tENS tENH tENH tDS tDH LD WEN tDS tDS tDH tDS tDH tDH D0 - D16 PAE OFFSET (LSB) PAE OFFSET (MSB) PAF OFFSET (LSB) PAF OFFSET (MSB) 4666 drw19 NOTE: 1. This diagram is based on programming the IDT72V293 x18 bus width. Add one extra cycle to both the PAE offset and PAF offset for x9 bus width. Figure 16. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes) tCLK tCLKH tCLKL RCLK tLDS tLDH tLDH tENS tENH tENH LD REN tA Q0 - Q16 tA tA tA PAE OFFSET (LSB) DATA IN OUTPUT REGISTER PAF OFFSET (LSB) PAE OFFSET (MSB) PAF OFFSET (MSB) NOTES: 1. OE = LOW. 2. This diagram is based on programming the IDT72V293 x18 bus width. Add one extra cycle to both the PAE offset and PAF offset for x9 bus width. 4666 drw20 Figure 17. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes) tCLKH tCLKL WCLK 1 tENS 1 2 2 tENH WEN tPAFS PAF tPAFS (2) (2) D-(m+1) words in FIFO D - m words in FIFO tSKEW2(3) D-(m+1) words in FIFO(2) RCLK tENS tENH REN 4666 drw21 NOTES: 1. m = PAF offset . 2. D = maximum FIFO depth. In IDT Standard mode: if x18 Input or x18 Output bus Width is selected, D = 512 for the IDT72V223, 1,024 for the IDT72V233, 2,048 for the IDT72V243, 4,096 for the IDT72V253, 8,192 for the IDT72V263, 16,384 for the IDT72V273, 32,768 for the IDT72V283 and 65,536 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, D = 1,024 for the IDT72V223, 2,048 for the IDT72V233, 4,096 for the IDT72V243, 8,192 for the IDT72V253, 16,384 for the IDT72V263, 32,768 for the IDT72V273, 65,536 for the IDT72V283 and 131,072 for the IDT72V293. In FWFT mode: if x18 Input or x18 Output bus Width is selected, D = 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263, 16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, D = 1,025 for the IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the IDT72V253, 16,385 for the IDT72V263, 32,769 for the IDT72V273, 65,537 for the IDT72V283 and 131,073 for the IDT72V293. 3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAFS). If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle. 4. PAF is asserted and updated on the rising edge of WCLK only. 5. Select this mode by setting PFM HIGH during Master Reset. Figure 18. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes) 33 IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 tCLKH COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES tCLKL WCLK tENS tENH WEN PAE n words in FIFO (2), n+1 words in FIFO (3) tSKEW2(4) RCLK tPAES 1 n words in FIFO (2), n+1 words in FIFO(3) n+1 words in FIFO (2), n+2 words in FIFO (3) 2 tPAES 1 2 tENH tENS REN 4666 drw22 NOTES: 1. n = PAE offset. 2. For IDT Standard mode 3. For FWFT mode. 4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAES). If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle. 5. PAE is asserted and updated on the rising edge of WCLK only. 6. Select this mode by setting PFM HIGH during Master Reset. Figure 19. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes) tCLKH tCLKL WCLK tENS tENH WEN tPAFA PAF D ⎯ m words in FIFO D ⎯ (m + 1) words in FIFO D ⎯ (m + 1) words in FIFO tPAFA RCLK tENS REN 4666 drw23 NOTES: 1. m = PAF offset. 2. D = maximum FIFO Depth. In IDT Standard mode: if x18 Input or x18 Output bus Width is selected, D = 512 for the IDT72V223, 1,024 for the IDT72V233, 2,048 for the IDT72V243, 4,096 for the IDT72V253, 8,192 for the IDT72V263, 16,384 for the IDT72V273, 32,768 for the IDT72V283 and 65,536 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, D = 1,024 for the IDT72V223, 2,048 for the IDT72V233, 4,096 for the IDT72V243, 8,192 for the IDT72V253, 16,384 for the IDT72V263, 32,768 for the IDT72V273, 65,536 for the IDT72V283 and 131,072 for the IDT72V293. In FWFT mode: if x18 Input or x18 Output bus Width is selected, D = 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263, 16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, D = 1,025 for the IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the IDT72V253, 16,385 for the IDT72V263, 32,769 for the IDT72V273, 65,537 for the IDT72V283 and 131,073 for the IDT72V293. 3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition. 4. Select this mode by setting PFM LOW during Master Reset. Figure 20. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes) 34 BUS FIFO IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 8K 9/18, 2K 32K 9/18, x 9/18, 9/18,x256K 9/18, 512K64K x9 x 9/18, 128K x 9 512xx18, 18,16K 1K xx 9/18, xx 9/18, 4K64K x 9/18, 8K 128K x 9/18,x 16K 9/18, x32K x 9/18, tCLKH COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES tCLKL WCLK tENS tENH WEN tPAEA n words in FIFO(2), n + 1 words in FIFO(3) PAE n words in FIFO(2), n + 1 words in FIFO(3) n + 1 words in FIFO(2), n + 2 words in FIFO(3) tPAEA RCLK tENS REN 4666 drw24 NOTES: 1. n = PAE offset. 2. For IDT Standard Mode. 3. For FWFT Mode. 4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition. 5. Select this mode by setting PFM LOW during Master Reset. Figure 21. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes) tCLKH tCLKL WCLK tENH tENS WEN [ D2 + 1] words in FIFO(1), [ D +2 1 ] + 1 words in FIFO tHF HF D/2 words in [ D+1 2 FIFO(1), D/2 words in FIFO(1), (2) ] words in FIFO (2) [ D+1 2 ] words in FIFO(2) tHF RCLK tENS REN 4666 drw25 NOTES: 1. In IDT Standard mode: D = maximum FIFO depth. If x18 Input or x18 Output bus Width is selected, D = 512 for the IDT72V223, 1,024 for the IDT72V233, 2,048 for the IDT72V243, 4,096 for the IDT72V253, 8,192 for the IDT72V263, 16,384 for the IDT72V273, 32,768 for the IDT72V283 and 65,536 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, D = 1,024 for the IDT72V223, 2,048 for the IDT72V233, 4,096 for the IDT72V243, 8,192 for the IDT72V253, 16,384 for the IDT72V263, 32,768 for the IDT72V273, 65,536 for the IDT72V283 and 131,072 for the IDT72V293. 2. In FWFT mode: D = maximum FIFO depth. If x18 Input or x18 Output bus Width is selected, D = 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263, 16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, D = 1,025 for the IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the IDT72V253, 16,385 for the IDT72V263, 32,769 for the IDT72V273, 65,537 for the IDT72V283 and 131,073 for the IDT72V293. Figure 22. Half-Full Flag Timing (IDT Standard and FWFT Modes) 35 IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES RCLK tENS REN tENH tA Qn W0 W1 tFFA FF tFFA tFFA tCYC WR tDS Dn tCYH tDH WD WD+1 4666 drw26 NOTE: 1. OE = LOW and WEN = LOW. Figure 23. Asynchronous Write, Synchronous Read, Full Flag Operation (IDT Standard Mode) 1 RCLK 2 tENS REN tENH tA tA Qn Last Word W1 W0 tREF tREF EF tCYL tSKEW WR tCYH tCYC tDH tDS Dn W0 tDH tDS W1 4666 drw27 NOTE: 1. OE = LOW and WEN = LOW. Figure 24. Asynchronous Write, Synchronous Read, Empty Flag Operation (IDT Standard Mode) 36 BUS FIFO IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 8K 9/18, 2K 32K 9/18, x 9/18, 9/18,x256K 9/18, 512K64K x9 x 9/18, 128K x 9 512xx18, 18,16K 1K xx 9/18, xx 9/18, 4K64K x 9/18, 8K 128K x 9/18,x 16K 9/18, x32K x 9/18, COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES No Write WCLK 1 2 WEN Dn DF tWFF DF+1 tWFF FF tCYC tSKEW tCYL tCYH RD tAA tAA Qn Last Word WX WX+1 4666 drw28 NOTE: 1. OE = LOW and REN = LOW. 2. Asynchronous Read is available in IDT Standard Mode only. Figure 25. Synchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode) WCLK tENS tENH WEN tDS Dn EF tDH W0 tEFA tRPE tEFA RD tCYH tAA Qn Last Word in Output Register W0 4666 drw29 NOTE: 1. OE = LOW and REN = LOW. 2. Asynchronous Read is available in IDT Standard Mode only. Figure 26. Synchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode) 37 IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 tCYH tCYC COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES tCYL WR tDH Dn tDH tDS W0 W1 RD tAA tAA Qn W1 W0 Last Word in O/P Register tRPE tEFA tEFA EF 4666 drw30 NOTES: 1. OE = LOW, WEN = LOW, and REN = LOW. 2. Asynchronous Read is available in IDT Standard Mode only. Figure 27. Asynchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode) tCYC tCYH tCYL WR tDH tDS Dn tDH tDS Wy+1 Wy tCYC tCYH tCYL RD tAA Qn Wx tAA Wx+1 Wx+2 tFFA tFFA FF 4666 drw31 NOTES: 1. OE = LOW, WEN = LOW, and REN = LOW. 2. Asynchronous Read is available in IDT Standard Mode only. Figure 28. Asynchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode) 38 BUS FIFO IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 8K 9/18, 2K 32K 9/18, x 9/18, 9/18,x256K 9/18, 512K64K x9 x 9/18, 128K x 9 512xx18, 18,16K 1K xx 9/18, xx 9/18, 4K64K x 9/18, 8K 128K x 9/18,x 16K 9/18, x32K x 9/18, OPTIONAL CONFIGURATIONS COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES composite flags can be created by ORing OR of every FIFO, and separately ORing IR of every FIFO. Figure 29 demonstrates a width expansion using two IDT72V223/72V233/ 72V243/72V253/72V263/72V273/72V283/72V293 devices. If x18 Input or x18 Output bus Width is selected, D0-D17 from each device form a 36-bit wide input bus and Q0-Q17 from each device form a 36-bit wide output bus. If both x9 Input and x9 Output bus Widths are selected, D0-D8 from each device form an 18-bit wide input bus and Q0-Q8 from each device form an 18-bit wide output bus. Any word width can be attained by adding additional IDT72V223/72V233/ 72V243/72V253/72V263/72V273/72V283/72V293 devices. WIDTH EXPANSION CONFIGURATION Word width may be increased simply by connecting together the control signals of multiple devices. Status flags can be detected from any one device. The exceptions are the EF and FF functions in IDT Standard mode and the IR and OR functions in FWFT mode. Because of variations in skew between RCLK and WCLK, it is possible for EF/FF deassertion and IR/OR assertion to vary by one cycle between FIFOs. In IDT Standard mode, such problems can be avoided by creating composite flags, that is, ANDing EF of every FIFO, and separately ANDing FF of every FIFO. In FWFT mode, PARTIAL RESET (PRS) MASTER RESET (MRS) FIRST WORD FALL THROUGH/ SERIAL INPUT (FWFT/SI) RETRANSMIT (RT) DATA IN m+n Dm+1 - Dn D0 - Dm m n READ CLOCK (RCLK) WRITE CLOCK (WCLK) WRITE ENABLE (WEN) LOAD (LD) FULL FLAG/INPUT READY (FF/IR) #1 (1) GATE FULL FLAG/INPUT READY (FF/IR) #2 PROGRAMMABLE (PAF) HALF-FULL FLAG (HF) IDT 72V223 72V233 72V243 72V253 72V263 72V273 72V283 72V293 IDT 72V223 72V233 72V243 72V253 72V263 72V273 72V283 72V293 READ ENABLE (REN) OUTPUT ENABLE (OE) PROGRAMMABLE (PAE) EMPTY FLAG/OUTPUT READY (EF/OR) #1 EMPTY FLAG/OUTPUT READY (EF/OR) #2 n FIFO #1 m FIFO #2 Q0 - Qm Qm+1 - Qn m+n (1) GATE DATA OUT 4666 drw32 NOTES: 1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode. 2. Do not connect any output control signals directly together. 3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths. Figure 29. Block Diagram of Width Expansion For the x18 Input or x18 Output bus Width: 512 x 36, 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36 and 65,536 x 36 For both x9 Input and x9 Output bus Widths: 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18, 16,284 x 18, 32,768 x 18, 65,536 x 18 and 131,072 x 18 39 IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES FWFT/SI TRANSFER CLOCK WRITE CLOCK WCLK WRITE ENABLE WEN INPUT READY IR DATA IN n Dn FWFT/SI IDT 72V223 72V233 72V243 72V253 72V263 72V273 72V283 72V293 WCLK RCLK OR WEN REN OE Qn IR GND n Dn FWFT/SI IDT 72V223 72V233 72V243 72V253 72V263 72V273 72V283 72V293 READ CLOCK RCLK REN READ ENABLE OR OUTPUT READY OE OUTPUT ENABLE Qn n DATA OUT 4666 drw33 Figure 30. Block Diagram of Depth Expansion For the x18 Input or x18 Output bus Width: 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18, 16,384 x 18, 32,768 x 18, 65,536 x 18 and 131,072 x 18 For both x9 Input and x9 Output bus Widths: 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9, 65,536 x 9, 131,072 x 9 and 262,144 x 9 Note that extra cycles should be added for the possibility that the tSKEW1 specification is not met between WCLK and transfer clock, or RCLK and transfer clock, for the OR flag. The "ripple down" delay is only noticeable for the first word written to an empty depth expansion configuration. There will be no delay evident for subsequent words written to the configuration. The first free location created by reading from a full depth expansion configuration will "bubble up" from the last FIFO to the previous one until it finally moves into the first FIFO of the chain. Each time a free location is created in one FIFO of the chain, that FIFO's IR line goes LOW, enabling the preceding FIFO to write a word to fill it. For a full expansion configuration, the amount of time it takes for IR of the first FIFO in the chain to go LOW after a word has been read from the last FIFO is the sum of the delays for each individual FIFO: DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY) The IDT72V223 can easily be adapted to applications requiring depths greater than 512 when the x18 Input or x18 Output bus Width is selected, 1,024 for the IDT72V233, 2,048 for the IDT72V243, 4,096 for the IDT72V253, 8,192 for the IDT72V263, 16,384 for the IDT72V273, 32,768 for the IDT72V283 and 65,536 for the IDT72V293. When both x9 Input and x9 Output bus Widths are selected, depths greater than 1,024 can be adapted for the IDT72V223, 2,048 for the IDT72V233, 4,096 for the IDT72V243, 8,192 for the IDT72V253, 16,384 for the IDT72V263, 32,768 for the IDT72V273, 65,536 for the IDT72V283 and 131,072 for the IDT72V293. In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs of the next) with no external logic necessary. The resulting configuration provides a total depth equivalent to the sum of the depths associated with each single FIFO. Figure 30 shows a depth expansion using two IDT72V223/72V233/72V243/ 72V253/72V263/72V273/72V283/72V293 devices. Care should be taken to select FWFT mode during Master Reset for all FIFOs in the depth expansion configuration. The first word written to an empty configuration will pass from one FIFO to the next ("ripple down") until it finally appears at the outputs of the last FIFO in the chain–no read operation is necessary but the RCLK of each FIFO must be free-running. Each time the data word appears at the outputs of one FIFO, that device's OR line goes LOW, enabling a write to the next FIFO in line. For an empty expansion configuration, the amount of time it takes for OR of the last FIFO in the chain to go LOW (i.e. valid data to appear on the last FIFO's outputs) after a word has been written to the first FIFO is the sum of the delays for each individual FIFO: (N – 1)*(4*transfer clock) + 3*TRCLK where N is the number of FIFOs in the expansion and TRCLK is the RCLK period. (N – 1)*(3*transfer clock) + 2 TWCLK where N is the number of FIFOs in the expansion and TWCLK is the WCLK period. Note that extra cycles should be added for the possibility that the tSKEW1 specification is not met between RCLK and transfer clock, or WCLK and transfer clock, for the IR flag. The Transfer Clock line should be tied to either WCLK or RCLK, whichever is faster. Both these actions result in data moving, as quickly as possible, to the end of the chain and free locations to the beginning of the chain. 40 BUS FIFO IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 8K 9/18, 2K 32K 9/18, x 9/18, 9/18,x256K 9/18, 512K64K x9 x 9/18, 128K x 9 512xx18, 18,16K 1K xx 9/18, xx 9/18, 4K64K x 9/18, 8K 128K x 9/18,x 16K 9/18, x32K x 9/18, COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES tTCK t3 t4 t1 t2 TCK TDI/ TMS tDS tDH TDO TDO t6 tDO TRST 4666 drw34 Notes to diagram: t1 = tTCKLOW t2 = tTCKHIGH t3 = tTCKFALL t4 = tTCKRise t5 = tRST (reset pulse width) t6 = tRSR (reset recovery) t5 Figure 31. Standard JTAG Timing JTAG AC ELECTRICAL CHARACTERISTICS SYSTEM INTERFACE PARAMETERS (VCC = 3.3V ± 5%; Tcase = 0°C to +85°C) IDT72V223 IDT72V233 IDT72V243 IDT72V253 IDT72V263 IDT72V273 IDT72V283 IDT72V293 Test Conditions Test Conditions Min. Max. Units JTAG Clock Input Period tTCK - 100 - ns JTAG Clock HIGH tTCKHIGH - 40 - ns JTAG Clock Low tTCKLOW - 40 - ns JTAG Clock Rise Time tTCKRise - - 5(1) ns Symbol Data Output tDO = Max - 20 ns JTAG Clock Fall Time tTCKFall - - 5(1) ns Data Output Hold tDOH 0 - ns JTAG Reset tRST - 50 - ns Data Input tDS tDH 10 10 - ns JTAG Reset Recovery tRSR - 50 - ns trise=3ns tfall=3ns Max. Units Symbol Parameter (1) Min. Parameter NOTE: 1. Guaranteed by design. NOTE: 1. 50pf loading on external output signals. 41 IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 JTAG INTERFACE COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES The Standard JTAG interface consists of four basic elements: • Test Access Port (TAP) • TAP controller • Instruction Register (IR) • Data Register Port (DR) Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to support the JTAG boundary scan interface. The IDT72V223/72V233/72V243/ 72V253/72V263/72V273/72V283/72V293 incorporates the necessary tap controller and modified pad cells to implement the JTAG facility. Note that IDT provides appropriate Boundary Scan Description Language program files for these devices. The following sections provide a brief description of each element. For a complete description refer to the IEEE Standard Test Access Port Specification (IEEE Std. 1149.1-1990). The Figure below shows the standard Boundary-Scan Architecture DeviceID Reg. Mux Boundary Scan Reg. Bypass Reg. TDO TDI T A TMS TCLK TRST P TAP Controller clkDR, ShiftDR UpdateDR Instruction Decode clklR, ShiftlR UpdatelR Instruction Register Control Signals 4666 drw35 Figure 32. Boundary Scan Architecture THE TAP CONTROLLER The Tap controller is a synchronous finite state machine that responds to TMS and TCLK signals to generate clock and control signals to the Instruction and Data Registers for capture and update of data. TEST ACCESS PORT (TAP) The Tap interface is a general-purpose port that provides access to the internal of the processor. It consists of four input ports (TCLK, TMS, TDI, TRST) and one output port (TDO). 42 BUS FIFO IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 8K 9/18, 2K 32K 9/18, x 9/18, 9/18,x256K 9/18, 512K64K x9 x 9/18, 128K x 9 512xx18, 18,16K 1K xx 9/18, xx 9/18, 4K64K x 9/18, 8K 128K x 9/18,x 16K 9/18, x32K x 9/18, 1 Test-Logic Reset 0 0 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Run-Test/ Idle 1 SelectDR-Scan 1 SelectIR-Scan 1 0 1 0 Capture-IR 1 Capture-DR 0 0 0 Shift-DR 1 Input = TMS EXit1-DR Shift-IR 1 1 0 1 Exit2-DR Exit2-IR 0 1 1 Update-DR 0 0 Pause-IR 1 1 1 Exit1-IR 0 0 Pause-DR 0 0 Update-IR 1 0 4666 drw36 NOTES: 1. Five consecutive TCK cycles with TMS = 1 will reset the TAP. 2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS). 3. TAP controller must be reset before normal FIFO operations can begin. Figure 33. TAP Controller State Diagram UPDATE-DR The shifting process has been completed. The data is latched into their parallel outputs in this state to be accessed through the internal bus. Refer to the IEEE Standard Test Access Port Specification (IEEE Std. 1149.1) for the full state diagram All state transitions within the TAP controller occur at the rising edge of the TCLK pulse. The TMS signal level (0 or 1) determines the state progression that occurs on each TCLK rising edge. The TAP controller takes precedence over the FIFO memory and must be reset after power up of the device. See TRST description for more details on TAP controller reset. EXIT1-DR / EXIT2-DR This is a temporary controller state. If TMS is held high, a rising edge applied to TCK while in this state causes the controller to enter the Update-DR state. This terminates the scanning process. All test data registers selected by the current instruction retain their previous state unchanged. CAPTURE-DR Data is loaded from the parallel input pins or core outputs into the Data Register. PAUSE-DR This controller state allows shifting of the test data register in the serial path between TDI and TDO to be temporarily halted. All test data registers selected by the current instruction retain their previous state unchanged. SHIFT-DR The previously captured data is shifted in serially, LSB first at the rising edge of TCLK in the TDI/TDO path and shifted out serially, LSB first at the falling edge of TCLK towards the output. Capture-IR, Shift-IR and Update-IR, Exit-IR and Pause-IR are similar to Data registers. These instructions operate on the instruction registers. 43 IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 THE INSTRUCTION REGISTER 31(MSB) 28 27 12 11 1 0(LSB) Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit) 0X0 0X33 1 The Instruction register allows an instruction to be shifted in serially into the processor at the rising edge of TCLK. The Instruction is used to select the test to be performed, or the test data register to be accessed, or both. The instruction shifted into the register is latched at the completion of the shifting process when the TAP controller is at UpdateIR state. The instruction register must contain 4 bit instruction register-based cells which can hold instruction data. These mandatory cells are located nearest the serial outputs they are the least significant bits. IDT72V223/233/243/253/263/273/283/293 JTAG Device Identification Register JTAG INSTRUCTION REGISTER The Instruction register allows instruction to be serially input into the device when the TAP controller is in the Shift-IR state. The instruction is decoded to perform the following: • Select test data registers that may operate while the instruction is current. The other test data registers should not interfere with chip operation and the selected data register. • Define the serial test data register path that is used to shift data between TDI and TDO during data register scanning. The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode 16 different possible instructions. Instructions are decoded as follows. TEST DATA REGISTER The Test Data register contains three test data registers: the Bypass, the Boundary Scan register and Device ID register. These registers are connected in parallel between a common serial input and a common serial data output. The following sections provide a brief description of each element. For a complete description, refer to the IEEE Standard Test Access Port Specification (IEEE Std. 1149.1-1990). Hex Value 0x00 0x02 0x01 0x03 0x0F TEST BYPASS REGISTER The register is used to allow test data to flow through the device from TDI to TDO. It contains a single stage shift register for a minimum length in serial path. When the bypass register is selected by an instruction, the shift register stage is set to a logic zero on the rising edge of TCLK when the TAP controller is in the Capture-DR state. The operation of the bypass register should not have any effect on the operation of the device in response to the BYPASS instruction. Instruction Function EXTEST IDCODE SAMPLE/PRELOAD HI-Z BYPASS Select Boundary Scan Register Select Chip Identification data register Select Boundary Scan Register JTAG Select Bypass Register Table 6. JTAG Instruction Register Decoding The following sections provide a brief description of each instruction. For a complete description refer to the IEEE Standard Test Access Port Specification (IEEE Std. 1149.1-1990). THE BOUNDARY-SCAN REGISTER The Boundary Scan Register allows serial data TDI be loaded in to or read out of the processor input/output ports. The Boundary Scan Register is a part of the IEEE 1149.1-1990 Standard JTAG Implementation. EXTEST The mandatory EXTEST instruction is provided for external circuity and board level interconnection check. IDCODE This instruction is provided to select Device Identification Register to read out manufacture’s identity, part number and version number. THE DEVICE IDENTIFICATION REGISTER The Device Identification Register is a Read Only 32-bit register used to specify the manufacturer, part number and version of the processor to be determined through the TAP in response to the IDCODE instruction. IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity is dropped in the 11-bit Manufacturer ID field. For the IDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/ 72V293, the Part Number field contains the following values: Device IDT72V223 IDT72V233 IDT72V243 IDT72V253 IDT72V263 IDT72V273 IDT72V283 IDT72V293 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES SAMPLE/PRELOAD The mandatory SAMPLE/PRELOAD instruction allows data values to be loaded onto the latched parallel outputs of the boundary-scan shift register prior to selection of the boundary-scan test instruction. The SAMPLE instruction allows a snapshot of data flowing from the system pins to the on-chip logic or vice versa. Part# Field 04EF 04EE 04ED 04EC 04EB 04EA 04E9 04E8 HIGH-Z This instruction places all the output pins on the device into a high impedance state. BYPASS The Bypass instruction contains a single shift-register stage and is set to provide a minimum-length serial path between the TDI and the TDO pins of the device when no test operation of the device is required. 44 ORDERING INFORMATION XXXXX X XX X Device Type Power Speed Package X X Process / Temperature Range X BLANK 8 Tube or Tray Tape and Reel BLANK I(1) Commercial (0°C to +70°C) Industrial (-40°C to +85°C) (3) G Green PF BC Thin Plastic Quad Flatpack (TQFP, PN80) Ball Grid Array (BGA, BC100) 6 7-5 10 15 Commercial Only, BGA & TQFP Com‘l & Ind’l, BGA & TQFP Com‘l & Ind’l, TQFP Only Commercial, TQFP Only L Low Power 72V223(2) 72V233(2) 72V243(2) 72V253(2) 72V263 72V273 72V283 72V293 Clock Cycle Time (tCLK) Speed in Nanoseconds 512 x 18/1,024 x 9 ⎯ 3.3V SuperSync II FIFO 1,024 x 18/2,048 x 9 ⎯ 3.3V SuperSync II FIFO 2,048 x 18/4,096 x 9 ⎯ 3.3V SuperSync II FIFO 4,096 x 18/8,192 x 9 ⎯ 3.3V SuperSync II FIFO 8,192 x 18/16,384 x 9 ⎯ 3.3V SuperSync II FIFO 16,384 x 18/32,768 x 9 ⎯ 3.3V SuperSync II FIFO 32,768 x 18/65,536 x 9 ⎯ 3.3V SuperSync II FIFO 65,536 x 18/131,072 x 9 ⎯ 3.3V SuperSync II FIFO 4666 drw37 NOTES: 1. Industrial temperature range product for 7-5ns and 10ns (IDT72V263/72V273/72V283/72V293 only) are available as standard device. All other speed grades are available by special order. 2. The IDT72V223/72V233/72V243/72V253 are only available in 6ns and 7-5ns speed grades. 3. Green parts are available. For specific speeds and packages contact you sales office. LEAD FINISH (SnPb) parts are in EOL process. Product Discontinuation Notice - PDN# SP-17-02 DATASHEET DOCUMENT HISTORY 12/18/2000 03/27/2001 04/06/2001 12/14/2001 12/20/2001 02/01/2002 03/25/2002 05/24/2002 01/20/2003 02/11/2003 07/15/2003 09/29/2003 11/02/2005 04/06/2006 02/11/2009 07/15/2014 03/08/2018 pgs.7, 8, 9, and 37. pgs.9, and 37. pgs.4, 5, and 21. pgs.1-45. pg. 9. pgs.9, and 45. pgs.2, and 41. pgs.3, and 11. pgs.1, 7, 9, 10, and 15. pgs.7, and 43. pgs.3, 19, and 36-38. pg. 8. pgs.1, 8-10, and 45. pg. 4. pg. 45. pgs. 2 and 45. Product Discontinuation Notice - PDN# SP-17-02 Last time buy expires June 15, 2018. CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 45 for Tech Support: 408-360-1753 email: FIFOhelp@idt.com IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. © 2020 Renesas Electronics Corporation. All rights reserved.